3 ** PCI Lower Bus Adapter (LBA) manager
5 ** (c) Copyright 1999,2000 Grant Grundler
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
8 ** This program is free software; you can redistribute it and/or modify
9 ** it under the terms of the GNU General Public License as published by
10 ** the Free Software Foundation; either version 2 of the License, or
11 ** (at your option) any later version.
14 ** This module primarily provides access to PCI bus (config/IOport
15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
16 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
18 ** LBA driver isn't as simple as the Dino driver because:
19 ** (a) this chip has substantial bug fixes between revisions
20 ** (Only one Dino bug has a software workaround :^( )
21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
24 ** (dino only deals with "Legacy" PDC)
26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
27 ** (I/O SAPIC is integratd in the LBA chip).
29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
30 ** FIXME: Add support for PCI card hot-plug (OLARD).
33 #include <linux/delay.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/spinlock.h>
37 #include <linux/init.h> /* for __init and __devinit */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <asm/byteorder.h>
44 #include <asm/pdcpat.h>
46 #include <asm/system.h>
48 #include <asm/ropes.h>
49 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
50 #include <asm/parisc-device.h>
51 #include <asm/io.h> /* read/write stuff */
53 #undef DEBUG_LBA /* general stuff */
54 #undef DEBUG_LBA_PORT /* debug I/O Port access */
55 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
56 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
58 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
62 #define DBG(x...) printk(x)
68 #define DBG_PORT(x...) printk(x)
70 #define DBG_PORT(x...)
74 #define DBG_CFG(x...) printk(x)
80 #define DBG_PAT(x...) printk(x)
87 ** Config accessor functions only pass in the 8-bit bus number and not
88 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
89 ** number based on what firmware wrote into the scratch register.
91 ** The "secondary" bus number is set to this before calling
92 ** pci_register_ops(). If any PPB's are present, the scan will
93 ** discover them and update the "secondary" and "subordinate"
94 ** fields in the pci_bus structure.
96 ** Changes in the configuration *may* result in a different
97 ** bus number for each LBA depending on what firmware does.
100 #define MODULE_NAME "LBA"
102 /* non-postable I/O port space, densely packed */
103 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
104 static void __iomem
*astro_iop_base __read_mostly
;
109 #define LBA_FLAG_SKIP_PROBE 0x10
111 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
114 /* Looks nice and keeps the compiler happy */
115 #define LBA_DEV(d) ((struct lba_device *) (d))
119 ** Only allow 8 subsidiary busses per LBA
120 ** Problem is the PCI bus numbering is globally shared.
122 #define LBA_MAX_NUM_BUSES 8
124 /************************************
125 * LBA register read and write support
127 * BE WARNED: register writes are posted.
128 * (ie follow writes which must reach HW with a read)
130 #define READ_U8(addr) __raw_readb(addr)
131 #define READ_U16(addr) __raw_readw(addr)
132 #define READ_U32(addr) __raw_readl(addr)
133 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
134 #define WRITE_U16(value, addr) __raw_writew(value, addr)
135 #define WRITE_U32(value, addr) __raw_writel(value, addr)
137 #define READ_REG8(addr) readb(addr)
138 #define READ_REG16(addr) readw(addr)
139 #define READ_REG32(addr) readl(addr)
140 #define READ_REG64(addr) readq(addr)
141 #define WRITE_REG8(value, addr) writeb(value, addr)
142 #define WRITE_REG16(value, addr) writew(value, addr)
143 #define WRITE_REG32(value, addr) writel(value, addr)
146 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
147 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
148 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
149 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
153 ** Extract LBA (Rope) number from HPA
154 ** REVISIT: 16 ropes for Stretch/Ike?
156 #define ROPES_PER_IOC 8
157 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
161 lba_dump_res(struct resource
*r
, int d
)
168 printk(KERN_DEBUG
"(%p)", r
->parent
);
169 for (i
= d
; i
; --i
) printk(" ");
170 printk(KERN_DEBUG
"%p [%lx,%lx]/%lx\n", r
,
171 (long)r
->start
, (long)r
->end
, r
->flags
);
172 lba_dump_res(r
->child
, d
+2);
173 lba_dump_res(r
->sibling
, d
);
178 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
179 ** workaround for cfg cycles:
180 ** -- preserve LBA state
181 ** -- prevent any DMA from occurring
182 ** -- turn on smart mode
183 ** -- probe with config writes before doing config reads
184 ** -- check ERROR_STATUS
185 ** -- clear ERROR_STATUS
186 ** -- restore LBA state
188 ** The workaround is only used for device discovery.
191 static int lba_device_present(u8 bus
, u8 dfn
, struct lba_device
*d
)
193 u8 first_bus
= d
->hba
.hba_bus
->secondary
;
194 u8 last_sub_bus
= d
->hba
.hba_bus
->subordinate
;
196 if ((bus
< first_bus
) ||
197 (bus
> last_sub_bus
) ||
198 ((bus
- first_bus
) >= LBA_MAX_NUM_BUSES
)) {
207 #define LBA_CFG_SETUP(d, tok) { \
208 /* Save contents of error config register. */ \
209 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
211 /* Save contents of status control register. */ \
212 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
214 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
215 ** arbitration for full bus walks. \
217 /* Save contents of arb mask register. */ \
218 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
221 * Turn off all device arbitration bits (i.e. everything \
222 * except arbitration enable bit). \
224 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
227 * Set the smart mode bit so that master aborts don't cause \
228 * LBA to go into PCI fatal mode (required). \
230 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
234 #define LBA_CFG_PROBE(d, tok) { \
236 * Setup Vendor ID write and read back the address register \
237 * to make sure that LBA is the bus master. \
239 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
241 * Read address register to ensure that LBA is the bus master, \
242 * which implies that DMA traffic has stopped when DMA arb is off. \
244 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
246 * Generate a cfg write cycle (will have no affect on \
247 * Vendor ID register since read-only). \
249 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
251 * Make sure write has completed before proceeding further, \
252 * i.e. before setting clear enable. \
254 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
260 * -- Can't tell if config cycle got the error.
262 * OV bit is broken until rev 4.0, so can't use OV bit and
263 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
265 * As of rev 4.0, no longer need the error check.
267 * -- Even if we could tell, we still want to return -1
268 * for **ANY** error (not just master abort).
270 * -- Only clear non-fatal errors (we don't want to bring
271 * LBA out of pci-fatal mode).
273 * Actually, there is still a race in which
274 * we could be clearing a fatal error. We will
275 * live with this during our initial bus walk
276 * until rev 4.0 (no driver activity during
277 * initial bus walk). The initial bus walk
278 * has race conditions concerning the use of
279 * smart mode as well.
282 #define LBA_MASTER_ABORT_ERROR 0xc
283 #define LBA_FATAL_ERROR 0x10
285 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
286 u32 error_status = 0; \
288 * Set clear enable (CE) bit. Unset by HW when new \
289 * errors are logged -- LBA HW ERS section 14.3.3). \
291 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
292 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
293 if ((error_status & 0x1f) != 0) { \
295 * Fail the config read request. \
298 if ((error_status & LBA_FATAL_ERROR) == 0) { \
300 * Clear error status (if fatal bit not set) by setting \
301 * clear error log bit (CL). \
303 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
308 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
309 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
311 #define LBA_CFG_ADDR_SETUP(d, addr) { \
312 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
314 * Read address register to ensure that LBA is the bus master, \
315 * which implies that DMA traffic has stopped when DMA arb is off. \
317 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
321 #define LBA_CFG_RESTORE(d, base) { \
323 * Restore status control register (turn off clear enable). \
325 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
327 * Restore error config register (turn off smart mode). \
329 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
331 * Restore arb mask register (reenables DMA arbitration). \
333 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
339 lba_rd_cfg(struct lba_device
*d
, u32 tok
, u8 reg
, u32 size
)
343 u32 arb_mask
= 0; /* used by LBA_CFG_SETUP/RESTORE */
344 u32 error_config
= 0; /* used by LBA_CFG_SETUP/RESTORE */
345 u32 status_control
= 0; /* used by LBA_CFG_SETUP/RESTORE */
347 LBA_CFG_SETUP(d
, tok
);
348 LBA_CFG_PROBE(d
, tok
);
349 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
351 void __iomem
*data_reg
= d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
;
353 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
355 case 1: data
= (u32
) READ_REG8(data_reg
+ (reg
& 3)); break;
356 case 2: data
= (u32
) READ_REG16(data_reg
+ (reg
& 2)); break;
357 case 4: data
= READ_REG32(data_reg
); break;
360 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
365 static int elroy_cfg_read(struct pci_bus
*bus
, unsigned int devfn
, int pos
, int size
, u32
*data
)
367 struct lba_device
*d
= LBA_DEV(parisc_walk_tree(bus
->bridge
));
368 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
369 u32 tok
= LBA_CFG_TOK(local_bus
, devfn
);
370 void __iomem
*data_reg
= d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
;
372 if ((pos
> 255) || (devfn
> 255))
375 /* FIXME: B2K/C3600 workaround is always use old method... */
376 /* if (!LBA_SKIP_PROBE(d)) */ {
377 /* original - Generate config cycle on broken elroy
378 with risk we will miss PCI bus errors. */
379 *data
= lba_rd_cfg(d
, tok
, pos
, size
);
380 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__
, tok
, pos
, *data
);
384 if (LBA_SKIP_PROBE(d
) && !lba_device_present(bus
->secondary
, devfn
, d
)) {
385 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__
, tok
, pos
);
386 /* either don't want to look or know device isn't present. */
392 ** Should only get here on fully working LBA rev.
393 ** This is how simple the code should have been.
395 LBA_CFG_ADDR_SETUP(d
, tok
| pos
);
397 case 1: *data
= READ_REG8 (data_reg
+ (pos
& 3)); break;
398 case 2: *data
= READ_REG16(data_reg
+ (pos
& 2)); break;
399 case 4: *data
= READ_REG32(data_reg
); break;
401 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__
, tok
, pos
, *data
);
407 lba_wr_cfg(struct lba_device
*d
, u32 tok
, u8 reg
, u32 data
, u32 size
)
411 u32 error_config
= 0;
412 u32 status_control
= 0;
413 void __iomem
*data_reg
= d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
;
415 LBA_CFG_SETUP(d
, tok
);
416 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
418 case 1: WRITE_REG8 (data
, data_reg
+ (reg
& 3)); break;
419 case 2: WRITE_REG16(data
, data_reg
+ (reg
& 2)); break;
420 case 4: WRITE_REG32(data
, data_reg
); break;
422 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
423 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
428 * LBA 4.0 config write code implements non-postable semantics
429 * by doing a read of CONFIG ADDR after the write.
432 static int elroy_cfg_write(struct pci_bus
*bus
, unsigned int devfn
, int pos
, int size
, u32 data
)
434 struct lba_device
*d
= LBA_DEV(parisc_walk_tree(bus
->bridge
));
435 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
436 u32 tok
= LBA_CFG_TOK(local_bus
,devfn
);
438 if ((pos
> 255) || (devfn
> 255))
441 if (!LBA_SKIP_PROBE(d
)) {
442 /* Original Workaround */
443 lba_wr_cfg(d
, tok
, pos
, (u32
) data
, size
);
444 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__
, tok
, pos
,data
);
448 if (LBA_SKIP_PROBE(d
) && (!lba_device_present(bus
->secondary
, devfn
, d
))) {
449 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__
, tok
, pos
,data
);
450 return 1; /* New Workaround */
453 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__
, tok
, pos
, data
);
455 /* Basic Algorithm */
456 LBA_CFG_ADDR_SETUP(d
, tok
| pos
);
458 case 1: WRITE_REG8 (data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (pos
& 3));
460 case 2: WRITE_REG16(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (pos
& 2));
462 case 4: WRITE_REG32(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
465 /* flush posted write */
466 lba_t32
= READ_REG32(d
->hba
.base_addr
+ LBA_PCI_CFG_ADDR
);
471 static struct pci_ops elroy_cfg_ops
= {
472 .read
= elroy_cfg_read
,
473 .write
= elroy_cfg_write
,
477 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
478 * TR4.0 as no additional bugs were found in this areea between Elroy and
482 static int mercury_cfg_read(struct pci_bus
*bus
, unsigned int devfn
, int pos
, int size
, u32
*data
)
484 struct lba_device
*d
= LBA_DEV(parisc_walk_tree(bus
->bridge
));
485 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
486 u32 tok
= LBA_CFG_TOK(local_bus
, devfn
);
487 void __iomem
*data_reg
= d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
;
489 if ((pos
> 255) || (devfn
> 255))
492 LBA_CFG_TR4_ADDR_SETUP(d
, tok
| pos
);
495 *data
= READ_REG8(data_reg
+ (pos
& 3));
498 *data
= READ_REG16(data_reg
+ (pos
& 2));
501 *data
= READ_REG32(data_reg
); break;
505 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok
, pos
, *data
);
510 * LBA 4.0 config write code implements non-postable semantics
511 * by doing a read of CONFIG ADDR after the write.
514 static int mercury_cfg_write(struct pci_bus
*bus
, unsigned int devfn
, int pos
, int size
, u32 data
)
516 struct lba_device
*d
= LBA_DEV(parisc_walk_tree(bus
->bridge
));
517 void __iomem
*data_reg
= d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
;
518 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
519 u32 tok
= LBA_CFG_TOK(local_bus
,devfn
);
521 if ((pos
> 255) || (devfn
> 255))
524 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__
, tok
, pos
, data
);
526 LBA_CFG_TR4_ADDR_SETUP(d
, tok
| pos
);
529 WRITE_REG8 (data
, data_reg
+ (pos
& 3));
532 WRITE_REG16(data
, data_reg
+ (pos
& 2));
535 WRITE_REG32(data
, data_reg
);
539 /* flush posted write */
540 lba_t32
= READ_U32(d
->hba
.base_addr
+ LBA_PCI_CFG_ADDR
);
544 static struct pci_ops mercury_cfg_ops
= {
545 .read
= mercury_cfg_read
,
546 .write
= mercury_cfg_write
,
553 DBG(MODULE_NAME
": lba_bios_init\n");
560 * truncate_pat_collision: Deal with overlaps or outright collisions
561 * between PAT PDC reported ranges.
563 * Broken PA8800 firmware will report lmmio range that
564 * overlaps with CPU HPA. Just truncate the lmmio range.
566 * BEWARE: conflicts with this lmmio range may be an
567 * elmmio range which is pointing down another rope.
569 * FIXME: only deals with one collision per range...theoretically we
570 * could have several. Supporting more than one collision will get messy.
573 truncate_pat_collision(struct resource
*root
, struct resource
*new)
575 unsigned long start
= new->start
;
576 unsigned long end
= new->end
;
577 struct resource
*tmp
= root
->child
;
579 if (end
<= start
|| start
< root
->start
|| !tmp
)
582 /* find first overlap */
583 while (tmp
&& tmp
->end
< start
)
586 /* no entries overlap */
589 /* found one that starts behind the new one
590 ** Don't need to do anything.
592 if (tmp
->start
>= end
) return 0;
594 if (tmp
->start
<= start
) {
595 /* "front" of new one overlaps */
596 new->start
= tmp
->end
+ 1;
598 if (tmp
->end
>= end
) {
599 /* AACCKK! totally overlaps! drop this range. */
604 if (tmp
->end
< end
) {
605 /* "end" of new one overlaps */
606 new->end
= tmp
->start
- 1;
609 printk(KERN_WARNING
"LBA: Truncating lmmio_space [%lx/%lx] "
612 (long)new->start
, (long)new->end
);
614 return 0; /* truncation successful */
618 #define truncate_pat_collision(r,n) (0)
622 ** The algorithm is generic code.
623 ** But it needs to access local data structures to get the IRQ base.
624 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
627 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
628 ** Resources aren't allocated until recursive buswalk below HBA is completed.
631 lba_fixup_bus(struct pci_bus
*bus
)
633 struct list_head
*ln
;
637 struct lba_device
*ldev
= LBA_DEV(parisc_walk_tree(bus
->bridge
));
639 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
640 bus
, bus
->secondary
, bus
->bridge
->platform_data
);
643 ** Properly Setup MMIO resources for this bus.
644 ** pci_alloc_primary_bus() mangles this.
649 pci_read_bridge_bases(bus
);
650 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
651 pci_claim_resource(bus
->self
, i
);
654 /* Host-PCI Bridge */
657 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
658 ldev
->hba
.io_space
.name
,
659 ldev
->hba
.io_space
.start
, ldev
->hba
.io_space
.end
,
660 ldev
->hba
.io_space
.flags
);
661 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
662 ldev
->hba
.lmmio_space
.name
,
663 ldev
->hba
.lmmio_space
.start
, ldev
->hba
.lmmio_space
.end
,
664 ldev
->hba
.lmmio_space
.flags
);
666 err
= request_resource(&ioport_resource
, &(ldev
->hba
.io_space
));
668 lba_dump_res(&ioport_resource
, 2);
672 if (ldev
->hba
.elmmio_space
.start
) {
673 err
= request_resource(&iomem_resource
,
674 &(ldev
->hba
.elmmio_space
));
677 printk("FAILED: lba_fixup_bus() request for "
678 "elmmio_space [%lx/%lx]\n",
679 (long)ldev
->hba
.elmmio_space
.start
,
680 (long)ldev
->hba
.elmmio_space
.end
);
682 /* lba_dump_res(&iomem_resource, 2); */
687 if (ldev
->hba
.lmmio_space
.flags
) {
688 err
= request_resource(&iomem_resource
, &(ldev
->hba
.lmmio_space
));
690 printk(KERN_ERR
"FAILED: lba_fixup_bus() request for "
691 "lmmio_space [%lx/%lx]\n",
692 (long)ldev
->hba
.lmmio_space
.start
,
693 (long)ldev
->hba
.lmmio_space
.end
);
698 /* GMMIO is distributed range. Every LBA/Rope gets part it. */
699 if (ldev
->hba
.gmmio_space
.flags
) {
700 err
= request_resource(&iomem_resource
, &(ldev
->hba
.gmmio_space
));
702 printk("FAILED: lba_fixup_bus() request for "
703 "gmmio_space [%lx/%lx]\n",
704 (long)ldev
->hba
.gmmio_space
.start
,
705 (long)ldev
->hba
.gmmio_space
.end
);
706 lba_dump_res(&iomem_resource
, 2);
714 list_for_each(ln
, &bus
->devices
) {
716 struct pci_dev
*dev
= pci_dev_b(ln
);
718 DBG("lba_fixup_bus() %s\n", pci_name(dev
));
720 /* Virtualize Device/Bridge Resources. */
721 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
722 struct resource
*res
= &dev
->resource
[i
];
724 /* If resource not allocated - skip it */
729 ** FIXME: this will result in whinging for devices
730 ** that share expansion ROMs (think quad tulip), but
733 pci_claim_resource(dev
, i
);
738 ** If one device does not support FBB transfers,
739 ** No one on the bus can be allowed to use them.
741 (void) pci_read_config_word(dev
, PCI_STATUS
, &status
);
742 bus
->bridge_ctl
&= ~(status
& PCI_STATUS_FAST_BACK
);
746 ** P2PB's have no IRQs. ignore them.
748 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
)
751 /* Adjust INTERRUPT_LINE for this dev */
752 iosapic_fixup_irq(ldev
->iosapic_obj
, dev
);
756 /* FIXME/REVISIT - finish figuring out to set FBB on both
757 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
758 ** Can't fixup here anyway....garr...
764 (void) pci_read_config_byte(bus
->self
, PCI_BRIDGE_CONTROL
, &control
);
765 (void) pci_write_config_byte(bus
->self
, PCI_BRIDGE_CONTROL
, control
| PCI_STATUS_FAST_BACK
);
770 fbb_enable
= PCI_COMMAND_FAST_BACK
;
773 /* Lastly enable FBB/PERR/SERR on all devices too */
774 list_for_each(ln
, &bus
->devices
) {
775 (void) pci_read_config_word(dev
, PCI_COMMAND
, &status
);
776 status
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| fbb_enable
;
777 (void) pci_write_config_word(dev
, PCI_COMMAND
, status
);
783 static struct pci_bios_ops lba_bios_ops
= {
784 .init
= lba_bios_init
,
785 .fixup_bus
= lba_fixup_bus
,
791 /*******************************************************
793 ** LBA Sprockets "I/O Port" Space Accessor Functions
795 ** This set of accessor functions is intended for use with
796 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
798 ** Many PCI devices don't require use of I/O port space (eg Tulip,
799 ** NCR720) since they export the same registers to both MMIO and
800 ** I/O port space. In general I/O port space is slower than
801 ** MMIO since drivers are designed so PIO writes can be posted.
803 ********************************************************/
805 #define LBA_PORT_IN(size, mask) \
806 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
809 t = READ_REG##size(astro_iop_base + addr); \
810 DBG_PORT(" 0x%x\n", t); \
821 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
823 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
824 ** guarantee non-postable completion semantics - not avoid X4107.
825 ** The READ_U32 only guarantees the write data gets to elroy but
826 ** out to the PCI bus. We can't read stuff from I/O port space
827 ** since we don't know what has side-effects. Attempting to read
828 ** from configuration space would be suicidal given the number of
829 ** bugs in that elroy functionality.
832 ** DMA read results can improperly pass PIO writes (X4107). The
833 ** result of this bug is that if a processor modifies a location in
834 ** memory after having issued PIO writes, the PIO writes are not
835 ** guaranteed to be completed before a PCI device is allowed to see
836 ** the modified data in a DMA read.
838 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
842 ** The workaround for this bug is to always follow a PIO write with
843 ** a PIO read to the same bus before starting DMA on that PCI bus.
846 #define LBA_PORT_OUT(size, mask) \
847 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
849 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
850 WRITE_REG##size(val, astro_iop_base + addr); \
851 if (LBA_DEV(d)->hw_rev < 3) \
852 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
860 static struct pci_port_ops lba_astro_port_ops
= {
861 .inb
= lba_astro_in8
,
862 .inw
= lba_astro_in16
,
863 .inl
= lba_astro_in32
,
864 .outb
= lba_astro_out8
,
865 .outw
= lba_astro_out16
,
866 .outl
= lba_astro_out32
871 #define PIOP_TO_GMMIO(lba, addr) \
872 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
874 /*******************************************************
876 ** LBA PAT "I/O Port" Space Accessor Functions
878 ** This set of accessor functions is intended for use with
879 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
881 ** This uses the PIOP space located in the first 64MB of GMMIO.
882 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
883 ** bits 1:0 stay the same. bits 15:2 become 25:12.
884 ** Then add the base and we can generate an I/O Port cycle.
885 ********************************************************/
887 #define LBA_PORT_IN(size, mask) \
888 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
891 DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
892 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
893 DBG_PORT(" 0x%x\n", t); \
903 #define LBA_PORT_OUT(size, mask) \
904 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
906 void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
907 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
908 WRITE_REG##size(val, where); \
909 /* flush the I/O down to the elroy at least */ \
910 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
918 static struct pci_port_ops lba_pat_port_ops
= {
922 .outb
= lba_pat_out8
,
923 .outw
= lba_pat_out16
,
924 .outl
= lba_pat_out32
930 ** make range information from PDC available to PCI subsystem.
931 ** We make the PDC call here in order to get the PCI bus range
932 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
933 ** We don't have a struct pci_bus assigned to us yet.
936 lba_pat_resources(struct parisc_device
*pa_dev
, struct lba_device
*lba_dev
)
938 unsigned long bytecnt
;
940 long status
; /* PDC return status */
942 pdc_pat_cell_mod_maddr_block_t
*pa_pdc_cell
; /* PA_VIEW */
943 pdc_pat_cell_mod_maddr_block_t
*io_pdc_cell
; /* IO_VIEW */
946 pa_pdc_cell
= kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t
), GFP_KERNEL
);
950 io_pdc_cell
= kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t
), GFP_KERNEL
);
956 /* return cell module (IO view) */
957 status
= pdc_pat_cell_module(&bytecnt
, pa_dev
->pcell_loc
, pa_dev
->mod_index
,
958 PA_VIEW
, pa_pdc_cell
);
959 pa_count
= pa_pdc_cell
->mod
[1];
961 status
|= pdc_pat_cell_module(&bytecnt
, pa_dev
->pcell_loc
, pa_dev
->mod_index
,
962 IO_VIEW
, io_pdc_cell
);
963 io_count
= io_pdc_cell
->mod
[1];
965 /* We've already done this once for device discovery...*/
966 if (status
!= PDC_OK
) {
967 panic("pdc_pat_cell_module() call failed for LBA!\n");
970 if (PAT_GET_ENTITY(pa_pdc_cell
->mod_info
) != PAT_ENTITY_LBA
) {
971 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
975 ** Inspect the resources PAT tells us about
977 for (i
= 0; i
< pa_count
; i
++) {
981 unsigned long end
; /* aka finish */
985 p
= (void *) &(pa_pdc_cell
->mod
[2+i
*3]);
986 io
= (void *) &(io_pdc_cell
->mod
[2+i
*3]);
988 /* Convert the PAT range data to PCI "struct resource" */
989 switch(p
->type
& 0xff) {
991 lba_dev
->hba
.bus_num
.start
= p
->start
;
992 lba_dev
->hba
.bus_num
.end
= p
->end
;
996 /* used to fix up pre-initialized MEM BARs */
997 if (!lba_dev
->hba
.lmmio_space
.start
) {
998 sprintf(lba_dev
->hba
.lmmio_name
,
1000 (int)lba_dev
->hba
.bus_num
.start
);
1001 lba_dev
->hba
.lmmio_space_offset
= p
->start
-
1003 r
= &lba_dev
->hba
.lmmio_space
;
1004 r
->name
= lba_dev
->hba
.lmmio_name
;
1005 } else if (!lba_dev
->hba
.elmmio_space
.start
) {
1006 sprintf(lba_dev
->hba
.elmmio_name
,
1008 (int)lba_dev
->hba
.bus_num
.start
);
1009 r
= &lba_dev
->hba
.elmmio_space
;
1010 r
->name
= lba_dev
->hba
.elmmio_name
;
1012 printk(KERN_WARNING MODULE_NAME
1013 " only supports 2 LMMIO resources!\n");
1017 r
->start
= p
->start
;
1019 r
->flags
= IORESOURCE_MEM
;
1020 r
->parent
= r
->sibling
= r
->child
= NULL
;
1024 /* MMIO space > 4GB phys addr; for 64-bit BAR */
1025 sprintf(lba_dev
->hba
.gmmio_name
, "PCI%02x GMMIO",
1026 (int)lba_dev
->hba
.bus_num
.start
);
1027 r
= &lba_dev
->hba
.gmmio_space
;
1028 r
->name
= lba_dev
->hba
.gmmio_name
;
1029 r
->start
= p
->start
;
1031 r
->flags
= IORESOURCE_MEM
;
1032 r
->parent
= r
->sibling
= r
->child
= NULL
;
1036 printk(KERN_WARNING MODULE_NAME
1037 " range[%d] : ignoring NPIOP (0x%lx)\n",
1043 ** Postable I/O port space is per PCI host adapter.
1044 ** base of 64MB PIOP region
1046 lba_dev
->iop_base
= ioremap_nocache(p
->start
, 64 * 1024 * 1024);
1048 sprintf(lba_dev
->hba
.io_name
, "PCI%02x Ports",
1049 (int)lba_dev
->hba
.bus_num
.start
);
1050 r
= &lba_dev
->hba
.io_space
;
1051 r
->name
= lba_dev
->hba
.io_name
;
1052 r
->start
= HBA_PORT_BASE(lba_dev
->hba
.hba_num
);
1053 r
->end
= r
->start
+ HBA_PORT_SPACE_SIZE
- 1;
1054 r
->flags
= IORESOURCE_IO
;
1055 r
->parent
= r
->sibling
= r
->child
= NULL
;
1059 printk(KERN_WARNING MODULE_NAME
1060 " range[%d] : unknown pat range type (0x%lx)\n",
1070 /* keep compiler from complaining about missing declarations */
1071 #define lba_pat_port_ops lba_astro_port_ops
1072 #define lba_pat_resources(pa_dev, lba_dev)
1073 #endif /* CONFIG_64BIT */
1076 extern void sba_distributed_lmmio(struct parisc_device
*, struct resource
*);
1077 extern void sba_directed_lmmio(struct parisc_device
*, struct resource
*);
1081 lba_legacy_resources(struct parisc_device
*pa_dev
, struct lba_device
*lba_dev
)
1086 lba_dev
->hba
.lmmio_space_offset
= PCI_F_EXTEND
;
1089 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1090 ** represents bus->secondary and the second byte represents
1091 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1092 ** PCI bus walk *should* end up with the same result.
1093 ** FIXME: But we don't have sanity checks in PCI or LBA.
1095 lba_num
= READ_REG32(lba_dev
->hba
.base_addr
+ LBA_FW_SCRATCH
);
1096 r
= &(lba_dev
->hba
.bus_num
);
1097 r
->name
= "LBA PCI Busses";
1098 r
->start
= lba_num
& 0xff;
1099 r
->end
= (lba_num
>>8) & 0xff;
1101 /* Set up local PCI Bus resources - we don't need them for
1102 ** Legacy boxes but it's nice to see in /proc/iomem.
1104 r
= &(lba_dev
->hba
.lmmio_space
);
1105 sprintf(lba_dev
->hba
.lmmio_name
, "PCI%02x LMMIO",
1106 (int)lba_dev
->hba
.bus_num
.start
);
1107 r
->name
= lba_dev
->hba
.lmmio_name
;
1110 /* We want the CPU -> IO routing of addresses.
1111 * The SBA BASE/MASK registers control CPU -> IO routing.
1112 * Ask SBA what is routed to this rope/LBA.
1114 sba_distributed_lmmio(pa_dev
, r
);
1117 * The LBA BASE/MASK registers control IO -> System routing.
1119 * The following code works but doesn't get us what we want.
1120 * Well, only because firmware (v5.0) on C3000 doesn't program
1121 * the LBA BASE/MASE registers to be the exact inverse of
1122 * the corresponding SBA registers. Other Astro/Pluto
1123 * based platform firmware may do it right.
1125 * Should someone want to mess with MSI, they may need to
1126 * reprogram LBA BASE/MASK registers. Thus preserve the code
1127 * below until MSI is known to work on C3000/A500/N4000/RP3440.
1129 * Using the code below, /proc/iomem shows:
1131 * f0000000-f0ffffff : PCI00 LMMIO
1132 * f05d0000-f05d0000 : lcd_data
1133 * f05d0008-f05d0008 : lcd_cmd
1134 * f1000000-f1ffffff : PCI01 LMMIO
1135 * f4000000-f4ffffff : PCI02 LMMIO
1136 * f4000000-f4001fff : sym53c8xx
1137 * f4002000-f4003fff : sym53c8xx
1138 * f4004000-f40043ff : sym53c8xx
1139 * f4005000-f40053ff : sym53c8xx
1140 * f4007000-f4007fff : ohci_hcd
1141 * f4008000-f40083ff : tulip
1142 * f6000000-f6ffffff : PCI03 LMMIO
1143 * f8000000-fbffffff : PCI00 ELMMIO
1144 * fa100000-fa4fffff : stifb mmio
1145 * fb000000-fb1fffff : stifb fb
1147 * But everything listed under PCI02 actually lives under PCI00.
1148 * This is clearly wrong.
1150 * Asking SBA how things are routed tells the correct story:
1151 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1152 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1153 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1154 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1155 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1157 * Which looks like this in /proc/iomem:
1158 * f4000000-f47fffff : PCI00 LMMIO
1159 * f4000000-f4001fff : sym53c8xx
1160 * ...[deteled core devices - same as above]...
1161 * f4008000-f40083ff : tulip
1162 * f4800000-f4ffffff : PCI01 LMMIO
1163 * f6000000-f67fffff : PCI02 LMMIO
1164 * f7000000-f77fffff : PCI03 LMMIO
1165 * f9000000-f9ffffff : PCI02 ELMMIO
1166 * fa000000-fbffffff : PCI03 ELMMIO
1167 * fa100000-fa4fffff : stifb mmio
1168 * fb000000-fb1fffff : stifb fb
1170 * ie all Built-in core are under now correctly under PCI00.
1171 * The "PCI02 ELMMIO" directed range is for:
1172 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
1176 r
->start
= READ_REG32(lba_dev
->hba
.base_addr
+ LBA_LMMIO_BASE
);
1178 unsigned long rsize
;
1180 r
->flags
= IORESOURCE_MEM
;
1181 /* mmio_mask also clears Enable bit */
1182 r
->start
&= mmio_mask
;
1183 r
->start
= PCI_HOST_ADDR(HBA_DATA(lba_dev
), r
->start
);
1184 rsize
= ~ READ_REG32(lba_dev
->hba
.base_addr
+ LBA_LMMIO_MASK
);
1187 ** Each rope only gets part of the distributed range.
1188 ** Adjust "window" for this rope.
1190 rsize
/= ROPES_PER_IOC
;
1191 r
->start
+= (rsize
+ 1) * LBA_NUM(pa_dev
->hpa
.start
);
1192 r
->end
= r
->start
+ rsize
;
1194 r
->end
= r
->start
= 0; /* Not enabled. */
1199 ** "Directed" ranges are used when the "distributed range" isn't
1200 ** sufficient for all devices below a given LBA. Typically devices
1201 ** like graphics cards or X25 may need a directed range when the
1202 ** bus has multiple slots (ie multiple devices) or the device
1203 ** needs more than the typical 4 or 8MB a distributed range offers.
1205 ** The main reason for ignoring it now frigging complications.
1206 ** Directed ranges may overlap (and have precedence) over
1207 ** distributed ranges. Or a distributed range assigned to a unused
1208 ** rope may be used by a directed range on a different rope.
1209 ** Support for graphics devices may require fixing this
1210 ** since they may be assigned a directed range which overlaps
1211 ** an existing (but unused portion of) distributed range.
1213 r
= &(lba_dev
->hba
.elmmio_space
);
1214 sprintf(lba_dev
->hba
.elmmio_name
, "PCI%02x ELMMIO",
1215 (int)lba_dev
->hba
.bus_num
.start
);
1216 r
->name
= lba_dev
->hba
.elmmio_name
;
1219 /* See comment which precedes call to sba_directed_lmmio() */
1220 sba_directed_lmmio(pa_dev
, r
);
1222 r
->start
= READ_REG32(lba_dev
->hba
.base_addr
+ LBA_ELMMIO_BASE
);
1225 unsigned long rsize
;
1226 r
->flags
= IORESOURCE_MEM
;
1227 /* mmio_mask also clears Enable bit */
1228 r
->start
&= mmio_mask
;
1229 r
->start
= PCI_HOST_ADDR(HBA_DATA(lba_dev
), r
->start
);
1230 rsize
= READ_REG32(lba_dev
->hba
.base_addr
+ LBA_ELMMIO_MASK
);
1231 r
->end
= r
->start
+ ~rsize
;
1235 r
= &(lba_dev
->hba
.io_space
);
1236 sprintf(lba_dev
->hba
.io_name
, "PCI%02x Ports",
1237 (int)lba_dev
->hba
.bus_num
.start
);
1238 r
->name
= lba_dev
->hba
.io_name
;
1239 r
->flags
= IORESOURCE_IO
;
1240 r
->start
= READ_REG32(lba_dev
->hba
.base_addr
+ LBA_IOS_BASE
) & ~1L;
1241 r
->end
= r
->start
+ (READ_REG32(lba_dev
->hba
.base_addr
+ LBA_IOS_MASK
) ^ (HBA_PORT_SPACE_SIZE
- 1));
1243 /* Virtualize the I/O Port space ranges */
1244 lba_num
= HBA_PORT_BASE(lba_dev
->hba
.hba_num
);
1245 r
->start
|= lba_num
;
1250 /**************************************************************************
1252 ** LBA initialization code (HW and SW)
1254 ** o identify LBA chip itself
1255 ** o initialize LBA chip modes (HardFail)
1256 ** o FIXME: initialize DMA hints for reasonable defaults
1257 ** o enable configuration functions
1258 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1260 **************************************************************************/
1263 lba_hw_init(struct lba_device
*d
)
1266 u32 bus_reset
; /* PDC_PAT_BUG */
1269 printk(KERN_DEBUG
"LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1271 READ_REG64(d
->hba
.base_addr
+ LBA_STAT_CTL
),
1272 READ_REG64(d
->hba
.base_addr
+ LBA_ERROR_CONFIG
),
1273 READ_REG64(d
->hba
.base_addr
+ LBA_ERROR_STATUS
),
1274 READ_REG64(d
->hba
.base_addr
+ LBA_DMA_CTL
) );
1275 printk(KERN_DEBUG
" ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1276 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_MASK
),
1277 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_PRI
),
1278 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_MODE
),
1279 READ_REG64(d
->hba
.base_addr
+ LBA_ARB_MTLT
) );
1280 printk(KERN_DEBUG
" HINT cfg 0x%Lx\n",
1281 READ_REG64(d
->hba
.base_addr
+ LBA_HINT_CFG
));
1282 printk(KERN_DEBUG
" HINT reg ");
1284 for (i
=LBA_HINT_BASE
; i
< (14*8 + LBA_HINT_BASE
); i
+=8)
1285 printk(" %Lx", READ_REG64(d
->hba
.base_addr
+ i
));
1288 #endif /* DEBUG_LBA_PAT */
1292 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1293 * Only N-Class and up can really make use of Get slot status.
1294 * maybe L-class too but I've never played with it there.
1298 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1299 bus_reset
= READ_REG32(d
->hba
.base_addr
+ LBA_STAT_CTL
+ 4) & 1;
1301 printk(KERN_DEBUG
"NOTICE: PCI bus reset still asserted! (clearing)\n");
1304 stat
= READ_REG32(d
->hba
.base_addr
+ LBA_ERROR_CONFIG
);
1305 if (stat
& LBA_SMART_MODE
) {
1306 printk(KERN_DEBUG
"NOTICE: LBA in SMART mode! (cleared)\n");
1307 stat
&= ~LBA_SMART_MODE
;
1308 WRITE_REG32(stat
, d
->hba
.base_addr
+ LBA_ERROR_CONFIG
);
1311 /* Set HF mode as the default (vs. -1 mode). */
1312 stat
= READ_REG32(d
->hba
.base_addr
+ LBA_STAT_CTL
);
1313 WRITE_REG32(stat
| HF_ENABLE
, d
->hba
.base_addr
+ LBA_STAT_CTL
);
1316 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1317 ** if it's not already set. If we just cleared the PCI Bus Reset
1318 ** signal, wait a bit for the PCI devices to recover and setup.
1321 mdelay(pci_post_reset_delay
);
1323 if (0 == READ_REG32(d
->hba
.base_addr
+ LBA_ARB_MASK
)) {
1325 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1326 ** B2000/C3600/J6000 also have this problem?
1328 ** Elroys with hot pluggable slots don't get configured
1329 ** correctly if the slot is empty. ARB_MASK is set to 0
1330 ** and we can't master transactions on the bus if it's
1331 ** not at least one. 0x3 enables elroy and first slot.
1333 printk(KERN_DEBUG
"NOTICE: Enabling PCI Arbitration\n");
1334 WRITE_REG32(0x3, d
->hba
.base_addr
+ LBA_ARB_MASK
);
1338 ** FIXME: Hint registers are programmed with default hint
1339 ** values by firmware. Hints should be sane even if we
1340 ** can't reprogram them the way drivers want.
1346 * Unfortunately, when firmware numbers busses, it doesn't take into account
1347 * Cardbus bridges. So we have to renumber the busses to suit ourselves.
1348 * Elroy/Mercury don't actually know what bus number they're attached to;
1349 * we use bus 0 to indicate the directly attached bus and any other bus
1350 * number will be taken care of by the PCI-PCI bridge.
1352 static unsigned int lba_next_bus
= 0;
1355 * Determine if lba should claim this chip (return 0) or not (return 1).
1356 * If so, initialize the chip and tell other partners in crime they
1360 lba_driver_probe(struct parisc_device
*dev
)
1362 struct lba_device
*lba_dev
;
1363 LIST_HEAD(resources
);
1364 struct pci_bus
*lba_bus
;
1365 struct pci_ops
*cfg_ops
;
1369 void __iomem
*addr
= ioremap_nocache(dev
->hpa
.start
, 4096);
1371 /* Read HW Rev First */
1372 func_class
= READ_REG32(addr
+ LBA_FCLASS
);
1374 if (IS_ELROY(dev
)) {
1376 switch (func_class
) {
1377 case 0: version
= "TR1.0"; break;
1378 case 1: version
= "TR2.0"; break;
1379 case 2: version
= "TR2.1"; break;
1380 case 3: version
= "TR2.2"; break;
1381 case 4: version
= "TR3.0"; break;
1382 case 5: version
= "TR4.0"; break;
1383 default: version
= "TR4+";
1386 printk(KERN_INFO
"Elroy version %s (0x%x) found at 0x%lx\n",
1387 version
, func_class
& 0xf, (long)dev
->hpa
.start
);
1389 if (func_class
< 2) {
1390 printk(KERN_WARNING
"Can't support LBA older than "
1391 "TR2.1 - continuing under adversity.\n");
1395 /* Elroy TR4.0 should work with simple algorithm.
1396 But it doesn't. Still missing something. *sigh*
1398 if (func_class
> 4) {
1399 cfg_ops
= &mercury_cfg_ops
;
1403 cfg_ops
= &elroy_cfg_ops
;
1406 } else if (IS_MERCURY(dev
) || IS_QUICKSILVER(dev
)) {
1410 major
= func_class
>> 4, minor
= func_class
& 0xf;
1412 /* We could use one printk for both Elroy and Mercury,
1413 * but for the mask for func_class.
1415 printk(KERN_INFO
"%s version TR%d.%d (0x%x) found at 0x%lx\n",
1416 IS_MERCURY(dev
) ? "Mercury" : "Quicksilver", major
,
1417 minor
, func_class
, (long)dev
->hpa
.start
);
1419 cfg_ops
= &mercury_cfg_ops
;
1421 printk(KERN_ERR
"Unknown LBA found at 0x%lx\n",
1422 (long)dev
->hpa
.start
);
1426 /* Tell I/O SAPIC driver we have a IRQ handler/region. */
1427 tmp_obj
= iosapic_register(dev
->hpa
.start
+ LBA_IOSAPIC_BASE
);
1429 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1430 ** have an IRT entry will get NULL back from iosapic code.
1433 lba_dev
= kzalloc(sizeof(struct lba_device
), GFP_KERNEL
);
1435 printk(KERN_ERR
"lba_init_chip - couldn't alloc lba_device\n");
1440 /* ---------- First : initialize data we already have --------- */
1442 lba_dev
->hw_rev
= func_class
;
1443 lba_dev
->hba
.base_addr
= addr
;
1444 lba_dev
->hba
.dev
= dev
;
1445 lba_dev
->iosapic_obj
= tmp_obj
; /* save interrupt handle */
1446 lba_dev
->hba
.iommu
= sba_get_iommu(dev
); /* get iommu data */
1447 parisc_set_drvdata(dev
, lba_dev
);
1449 /* ------------ Second : initialize common stuff ---------- */
1450 pci_bios
= &lba_bios_ops
;
1451 pcibios_register_hba(HBA_DATA(lba_dev
));
1452 spin_lock_init(&lba_dev
->lba_lock
);
1454 if (lba_hw_init(lba_dev
))
1457 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1460 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1461 pci_port
= &lba_pat_port_ops
;
1462 /* Go ask PDC PAT what resources this LBA has */
1463 lba_pat_resources(dev
, lba_dev
);
1465 if (!astro_iop_base
) {
1466 /* Sprockets PDC uses NPIOP region */
1467 astro_iop_base
= ioremap_nocache(LBA_PORT_BASE
, 64 * 1024);
1468 pci_port
= &lba_astro_port_ops
;
1471 /* Poke the chip a bit for /proc output */
1472 lba_legacy_resources(dev
, lba_dev
);
1475 if (lba_dev
->hba
.bus_num
.start
< lba_next_bus
)
1476 lba_dev
->hba
.bus_num
.start
= lba_next_bus
;
1478 /* Overlaps with elmmio can (and should) fail here.
1479 * We will prune (or ignore) the distributed range.
1481 * FIXME: SBA code should register all elmmio ranges first.
1482 * that would take care of elmmio ranges routed
1483 * to a different rope (already discovered) from
1484 * getting registered *after* LBA code has already
1485 * registered it's distributed lmmio range.
1487 if (truncate_pat_collision(&iomem_resource
,
1488 &(lba_dev
->hba
.lmmio_space
))) {
1489 printk(KERN_WARNING
"LBA: lmmio_space [%lx/%lx] duplicate!\n",
1490 (long)lba_dev
->hba
.lmmio_space
.start
,
1491 (long)lba_dev
->hba
.lmmio_space
.end
);
1492 lba_dev
->hba
.lmmio_space
.flags
= 0;
1495 pci_add_resource_offset(&resources
, &lba_dev
->hba
.io_space
,
1496 HBA_PORT_BASE(lba_dev
->hba
.hba_num
));
1497 if (lba_dev
->hba
.elmmio_space
.start
)
1498 pci_add_resource_offset(&resources
, &lba_dev
->hba
.elmmio_space
,
1499 lba_dev
->hba
.lmmio_space_offset
);
1500 if (lba_dev
->hba
.lmmio_space
.flags
)
1501 pci_add_resource_offset(&resources
, &lba_dev
->hba
.lmmio_space
,
1502 lba_dev
->hba
.lmmio_space_offset
);
1503 if (lba_dev
->hba
.gmmio_space
.flags
)
1504 pci_add_resource(&resources
, &lba_dev
->hba
.gmmio_space
);
1506 dev
->dev
.platform_data
= lba_dev
;
1507 lba_bus
= lba_dev
->hba
.hba_bus
=
1508 pci_create_root_bus(&dev
->dev
, lba_dev
->hba
.bus_num
.start
,
1509 cfg_ops
, NULL
, &resources
);
1511 pci_free_resource_list(&resources
);
1515 lba_bus
->subordinate
= pci_scan_child_bus(lba_bus
);
1517 /* This is in lieu of calling pci_assign_unassigned_resources() */
1519 /* assign resources to un-initialized devices */
1521 DBG_PAT("LBA pci_bus_size_bridges()\n");
1522 pci_bus_size_bridges(lba_bus
);
1524 DBG_PAT("LBA pci_bus_assign_resources()\n");
1525 pci_bus_assign_resources(lba_bus
);
1527 #ifdef DEBUG_LBA_PAT
1528 DBG_PAT("\nLBA PIOP resource tree\n");
1529 lba_dump_res(&lba_dev
->hba
.io_space
, 2);
1530 DBG_PAT("\nLBA LMMIO resource tree\n");
1531 lba_dump_res(&lba_dev
->hba
.lmmio_space
, 2);
1534 pci_enable_bridges(lba_bus
);
1537 ** Once PCI register ops has walked the bus, access to config
1538 ** space is restricted. Avoids master aborts on config cycles.
1539 ** Early LBA revs go fatal on *any* master abort.
1541 if (cfg_ops
== &elroy_cfg_ops
) {
1542 lba_dev
->flags
|= LBA_FLAG_SKIP_PROBE
;
1545 lba_next_bus
= lba_bus
->subordinate
+ 1;
1546 pci_bus_add_devices(lba_bus
);
1548 /* Whew! Finally done! Tell services we got this one covered. */
1552 static struct parisc_device_id lba_tbl
[] = {
1553 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, ELROY_HVERS
, 0xa },
1554 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, MERCURY_HVERS
, 0xa },
1555 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, QUICKSILVER_HVERS
, 0xa },
1559 static struct parisc_driver lba_driver
= {
1560 .name
= MODULE_NAME
,
1561 .id_table
= lba_tbl
,
1562 .probe
= lba_driver_probe
,
1566 ** One time initialization to let the world know the LBA was found.
1567 ** Must be called exactly once before pci_init().
1569 void __init
lba_init(void)
1571 register_parisc_driver(&lba_driver
);
1575 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1576 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1577 ** sba_iommu is responsible for locking (none needed at init time).
1579 void lba_set_iregs(struct parisc_device
*lba
, u32 ibase
, u32 imask
)
1581 void __iomem
* base_addr
= ioremap_nocache(lba
->hpa
.start
, 4096);
1583 imask
<<= 2; /* adjust for hints - 2 more bits */
1585 /* Make sure we aren't trying to set bits that aren't writeable. */
1586 WARN_ON((ibase
& 0x001fffff) != 0);
1587 WARN_ON((imask
& 0x001fffff) != 0);
1589 DBG("%s() ibase 0x%x imask 0x%x\n", __func__
, ibase
, imask
);
1590 WRITE_REG32( imask
, base_addr
+ LBA_IMASK
);
1591 WRITE_REG32( ibase
, base_addr
+ LBA_IBASE
);