2 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/resource.h>
25 #include <linux/types.h>
27 #include "pcie-designware.h"
29 /* PCIe controller wrapper DRA7XX configuration registers */
31 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
32 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
33 #define ERR_SYS BIT(0)
34 #define ERR_FATAL BIT(1)
35 #define ERR_NONFATAL BIT(2)
36 #define ERR_COR BIT(3)
37 #define ERR_AXI BIT(4)
38 #define ERR_ECRC BIT(5)
39 #define PME_TURN_OFF BIT(8)
40 #define PME_TO_ACK BIT(9)
41 #define PM_PME BIT(10)
42 #define LINK_REQ_RST BIT(11)
43 #define LINK_UP_EVT BIT(12)
44 #define CFG_BME_EVT BIT(13)
45 #define CFG_MSE_EVT BIT(14)
46 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
47 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
48 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
50 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
51 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
57 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
59 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
62 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
63 #define LINK_UP BIT(16)
73 #define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
75 static inline u32
dra7xx_pcie_readl(struct dra7xx_pcie
*pcie
, u32 offset
)
77 return readl(pcie
->base
+ offset
);
80 static inline void dra7xx_pcie_writel(struct dra7xx_pcie
*pcie
, u32 offset
,
83 writel(value
, pcie
->base
+ offset
);
86 static int dra7xx_pcie_link_up(struct pcie_port
*pp
)
88 struct dra7xx_pcie
*dra7xx
= to_dra7xx_pcie(pp
);
89 u32 reg
= dra7xx_pcie_readl(dra7xx
, PCIECTRL_DRA7XX_CONF_PHY_CS
);
91 return !!(reg
& LINK_UP
);
94 static int dra7xx_pcie_establish_link(struct pcie_port
*pp
)
96 struct dra7xx_pcie
*dra7xx
= to_dra7xx_pcie(pp
);
100 if (dw_pcie_link_up(pp
)) {
101 dev_err(pp
->dev
, "link is already up\n");
105 reg
= dra7xx_pcie_readl(dra7xx
, PCIECTRL_DRA7XX_CONF_DEVICE_CMD
);
107 dra7xx_pcie_writel(dra7xx
, PCIECTRL_DRA7XX_CONF_DEVICE_CMD
, reg
);
109 for (retries
= 0; retries
< 1000; retries
++) {
110 if (dw_pcie_link_up(pp
))
112 usleep_range(10, 20);
115 dev_err(pp
->dev
, "link is not up\n");
119 static void dra7xx_pcie_enable_interrupts(struct pcie_port
*pp
)
121 struct dra7xx_pcie
*dra7xx
= to_dra7xx_pcie(pp
);
123 dra7xx_pcie_writel(dra7xx
, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
,
125 dra7xx_pcie_writel(dra7xx
,
126 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN
, INTERRUPTS
);
127 dra7xx_pcie_writel(dra7xx
, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI
,
128 ~LEG_EP_INTERRUPTS
& ~MSI
);
130 if (IS_ENABLED(CONFIG_PCI_MSI
))
131 dra7xx_pcie_writel(dra7xx
,
132 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI
, MSI
);
134 dra7xx_pcie_writel(dra7xx
,
135 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI
,
139 static void dra7xx_pcie_host_init(struct pcie_port
*pp
)
141 dw_pcie_setup_rc(pp
);
142 dra7xx_pcie_establish_link(pp
);
143 if (IS_ENABLED(CONFIG_PCI_MSI
))
144 dw_pcie_msi_init(pp
);
145 dra7xx_pcie_enable_interrupts(pp
);
148 static struct pcie_host_ops dra7xx_pcie_host_ops
= {
149 .link_up
= dra7xx_pcie_link_up
,
150 .host_init
= dra7xx_pcie_host_init
,
153 static int dra7xx_pcie_intx_map(struct irq_domain
*domain
, unsigned int irq
,
154 irq_hw_number_t hwirq
)
156 irq_set_chip_and_handler(irq
, &dummy_irq_chip
, handle_simple_irq
);
157 irq_set_chip_data(irq
, domain
->host_data
);
158 set_irq_flags(irq
, IRQF_VALID
);
163 static const struct irq_domain_ops intx_domain_ops
= {
164 .map
= dra7xx_pcie_intx_map
,
167 static int dra7xx_pcie_init_irq_domain(struct pcie_port
*pp
)
169 struct device
*dev
= pp
->dev
;
170 struct device_node
*node
= dev
->of_node
;
171 struct device_node
*pcie_intc_node
= of_get_next_child(node
, NULL
);
173 if (!pcie_intc_node
) {
174 dev_err(dev
, "No PCIe Intc node found\n");
175 return PTR_ERR(pcie_intc_node
);
178 pp
->irq_domain
= irq_domain_add_linear(pcie_intc_node
, 4,
179 &intx_domain_ops
, pp
);
180 if (!pp
->irq_domain
) {
181 dev_err(dev
, "Failed to get a INTx IRQ domain\n");
182 return PTR_ERR(pp
->irq_domain
);
188 static irqreturn_t
dra7xx_pcie_msi_irq_handler(int irq
, void *arg
)
190 struct pcie_port
*pp
= arg
;
191 struct dra7xx_pcie
*dra7xx
= to_dra7xx_pcie(pp
);
194 reg
= dra7xx_pcie_readl(dra7xx
, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI
);
198 dw_handle_msi_irq(pp
);
204 generic_handle_irq(irq_find_mapping(pp
->irq_domain
, ffs(reg
)));
208 dra7xx_pcie_writel(dra7xx
, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI
, reg
);
214 static irqreturn_t
dra7xx_pcie_irq_handler(int irq
, void *arg
)
216 struct dra7xx_pcie
*dra7xx
= arg
;
219 reg
= dra7xx_pcie_readl(dra7xx
, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
);
222 dev_dbg(dra7xx
->dev
, "System Error\n");
225 dev_dbg(dra7xx
->dev
, "Fatal Error\n");
227 if (reg
& ERR_NONFATAL
)
228 dev_dbg(dra7xx
->dev
, "Non Fatal Error\n");
231 dev_dbg(dra7xx
->dev
, "Correctable Error\n");
234 dev_dbg(dra7xx
->dev
, "AXI tag lookup fatal Error\n");
237 dev_dbg(dra7xx
->dev
, "ECRC Error\n");
239 if (reg
& PME_TURN_OFF
)
241 "Power Management Event Turn-Off message received\n");
243 if (reg
& PME_TO_ACK
)
245 "Power Management Turn-Off Ack message received\n");
249 "PM Power Management Event message received\n");
251 if (reg
& LINK_REQ_RST
)
252 dev_dbg(dra7xx
->dev
, "Link Request Reset\n");
254 if (reg
& LINK_UP_EVT
)
255 dev_dbg(dra7xx
->dev
, "Link-up state change\n");
257 if (reg
& CFG_BME_EVT
)
258 dev_dbg(dra7xx
->dev
, "CFG 'Bus Master Enable' change\n");
260 if (reg
& CFG_MSE_EVT
)
261 dev_dbg(dra7xx
->dev
, "CFG 'Memory Space Enable' change\n");
263 dra7xx_pcie_writel(dra7xx
, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
, reg
);
268 static int __init
dra7xx_add_pcie_port(struct dra7xx_pcie
*dra7xx
,
269 struct platform_device
*pdev
)
272 struct pcie_port
*pp
;
273 struct resource
*res
;
274 struct device
*dev
= &pdev
->dev
;
278 pp
->ops
= &dra7xx_pcie_host_ops
;
280 pp
->irq
= platform_get_irq(pdev
, 1);
282 dev_err(dev
, "missing IRQ resource\n");
286 ret
= devm_request_irq(&pdev
->dev
, pp
->irq
,
287 dra7xx_pcie_msi_irq_handler
, IRQF_SHARED
,
288 "dra7-pcie-msi", pp
);
290 dev_err(&pdev
->dev
, "failed to request irq\n");
294 if (!IS_ENABLED(CONFIG_PCI_MSI
)) {
295 ret
= dra7xx_pcie_init_irq_domain(pp
);
300 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "rc_dbics");
301 pp
->dbi_base
= devm_ioremap(dev
, res
->start
, resource_size(res
));
305 ret
= dw_pcie_host_init(pp
);
307 dev_err(dra7xx
->dev
, "failed to initialize host\n");
314 static int __init
dra7xx_pcie_probe(struct platform_device
*pdev
)
323 struct resource
*res
;
324 struct dra7xx_pcie
*dra7xx
;
325 struct device
*dev
= &pdev
->dev
;
326 struct device_node
*np
= dev
->of_node
;
329 dra7xx
= devm_kzalloc(dev
, sizeof(*dra7xx
), GFP_KERNEL
);
333 irq
= platform_get_irq(pdev
, 0);
335 dev_err(dev
, "missing IRQ resource\n");
339 ret
= devm_request_irq(dev
, irq
, dra7xx_pcie_irq_handler
,
340 IRQF_SHARED
, "dra7xx-pcie-main", dra7xx
);
342 dev_err(dev
, "failed to request irq\n");
346 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "ti_conf");
347 base
= devm_ioremap_nocache(dev
, res
->start
, resource_size(res
));
351 phy_count
= of_property_count_strings(np
, "phy-names");
353 dev_err(dev
, "unable to find the strings\n");
357 phy
= devm_kzalloc(dev
, sizeof(*phy
) * phy_count
, GFP_KERNEL
);
361 for (i
= 0; i
< phy_count
; i
++) {
362 snprintf(name
, sizeof(name
), "pcie-phy%d", i
);
363 phy
[i
] = devm_phy_get(dev
, name
);
365 return PTR_ERR(phy
[i
]);
367 ret
= phy_init(phy
[i
]);
371 ret
= phy_power_on(phy
[i
]);
381 dra7xx
->phy_count
= phy_count
;
383 pm_runtime_enable(dev
);
384 ret
= pm_runtime_get_sync(dev
);
385 if (IS_ERR_VALUE(ret
)) {
386 dev_err(dev
, "pm_runtime_get_sync failed\n");
390 reg
= dra7xx_pcie_readl(dra7xx
, PCIECTRL_DRA7XX_CONF_DEVICE_CMD
);
392 dra7xx_pcie_writel(dra7xx
, PCIECTRL_DRA7XX_CONF_DEVICE_CMD
, reg
);
394 platform_set_drvdata(pdev
, dra7xx
);
396 ret
= dra7xx_add_pcie_port(dra7xx
, pdev
);
406 pm_runtime_disable(dev
);
410 phy_power_off(phy
[i
]);
417 static int __exit
dra7xx_pcie_remove(struct platform_device
*pdev
)
419 struct dra7xx_pcie
*dra7xx
= platform_get_drvdata(pdev
);
420 struct pcie_port
*pp
= &dra7xx
->pp
;
421 struct device
*dev
= &pdev
->dev
;
422 int count
= dra7xx
->phy_count
;
425 irq_domain_remove(pp
->irq_domain
);
427 pm_runtime_disable(dev
);
429 phy_power_off(dra7xx
->phy
[count
]);
430 phy_exit(dra7xx
->phy
[count
]);
436 static const struct of_device_id of_dra7xx_pcie_match
[] = {
437 { .compatible
= "ti,dra7-pcie", },
440 MODULE_DEVICE_TABLE(of
, of_dra7xx_pcie_match
);
442 static struct platform_driver dra7xx_pcie_driver
= {
443 .remove
= __exit_p(dra7xx_pcie_remove
),
446 .of_match_table
= of_dra7xx_pcie_match
,
450 module_platform_driver_probe(dra7xx_pcie_driver
, dra7xx_pcie_probe
);
452 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
453 MODULE_DESCRIPTION("TI PCIe controller driver");
454 MODULE_LICENSE("GPL v2");