2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
30 #include "pcie-designware.h"
32 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
35 struct gpio_desc
*reset_gpio
;
40 struct regmap
*iomuxc_gpr
;
41 void __iomem
*mem_base
;
44 /* PCIe Root Complex registers (memory-mapped) */
45 #define PCIE_RC_LCR 0x7c
46 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
47 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
48 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
50 #define PCIE_RC_LCSR 0x80
52 /* PCIe Port Logic registers (memory-mapped) */
53 #define PL_OFFSET 0x700
54 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
55 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
56 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
57 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
58 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
59 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
60 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
62 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
63 #define PCIE_PHY_CTRL_DATA_LOC 0
64 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
65 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
66 #define PCIE_PHY_CTRL_WR_LOC 18
67 #define PCIE_PHY_CTRL_RD_LOC 19
69 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
70 #define PCIE_PHY_STAT_ACK_LOC 16
72 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
73 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
75 /* PHY registers (not memory-mapped) */
76 #define PCIE_PHY_RX_ASIC_OUT 0x100D
77 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
79 #define PHY_RX_OVRD_IN_LO 0x1005
80 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
81 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
83 static int pcie_phy_poll_ack(void __iomem
*dbi_base
, int exp_val
)
86 u32 max_iterations
= 10;
90 val
= readl(dbi_base
+ PCIE_PHY_STAT
);
91 val
= (val
>> PCIE_PHY_STAT_ACK_LOC
) & 0x1;
98 } while (wait_counter
< max_iterations
);
103 static int pcie_phy_wait_ack(void __iomem
*dbi_base
, int addr
)
108 val
= addr
<< PCIE_PHY_CTRL_DATA_LOC
;
109 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
111 val
|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC
);
112 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
114 ret
= pcie_phy_poll_ack(dbi_base
, 1);
118 val
= addr
<< PCIE_PHY_CTRL_DATA_LOC
;
119 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
121 return pcie_phy_poll_ack(dbi_base
, 0);
124 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
125 static int pcie_phy_read(void __iomem
*dbi_base
, int addr
, int *data
)
130 ret
= pcie_phy_wait_ack(dbi_base
, addr
);
134 /* assert Read signal */
135 phy_ctl
= 0x1 << PCIE_PHY_CTRL_RD_LOC
;
136 writel(phy_ctl
, dbi_base
+ PCIE_PHY_CTRL
);
138 ret
= pcie_phy_poll_ack(dbi_base
, 1);
142 val
= readl(dbi_base
+ PCIE_PHY_STAT
);
143 *data
= val
& 0xffff;
145 /* deassert Read signal */
146 writel(0x00, dbi_base
+ PCIE_PHY_CTRL
);
148 return pcie_phy_poll_ack(dbi_base
, 0);
151 static int pcie_phy_write(void __iomem
*dbi_base
, int addr
, int data
)
158 ret
= pcie_phy_wait_ack(dbi_base
, addr
);
162 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
163 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
166 var
|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC
);
167 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
169 ret
= pcie_phy_poll_ack(dbi_base
, 1);
173 /* deassert cap data */
174 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
175 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
177 /* wait for ack de-assertion */
178 ret
= pcie_phy_poll_ack(dbi_base
, 0);
182 /* assert wr signal */
183 var
= 0x1 << PCIE_PHY_CTRL_WR_LOC
;
184 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
187 ret
= pcie_phy_poll_ack(dbi_base
, 1);
191 /* deassert wr signal */
192 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
193 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
195 /* wait for ack de-assertion */
196 ret
= pcie_phy_poll_ack(dbi_base
, 0);
200 writel(0x0, dbi_base
+ PCIE_PHY_CTRL
);
205 static void imx6_pcie_reset_phy(struct pcie_port
*pp
)
209 pcie_phy_read(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, &tmp
);
210 tmp
|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
|
211 PHY_RX_OVRD_IN_LO_RX_PLL_EN
);
212 pcie_phy_write(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, tmp
);
214 usleep_range(2000, 3000);
216 pcie_phy_read(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, &tmp
);
217 tmp
&= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
|
218 PHY_RX_OVRD_IN_LO_RX_PLL_EN
);
219 pcie_phy_write(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, tmp
);
222 /* Added for PCI abort handling */
223 static int imx6q_pcie_abort_handler(unsigned long addr
,
224 unsigned int fsr
, struct pt_regs
*regs
)
229 static int imx6_pcie_assert_core_reset(struct pcie_port
*pp
)
231 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
232 u32 val
, gpr1
, gpr12
;
235 * If the bootloader already enabled the link we need some special
236 * handling to get the core back into a state where it is safe to
237 * touch it for configuration. As there is no dedicated reset signal
238 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
239 * state before completely disabling LTSSM, which is a prerequisite
240 * for core configuration.
242 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
243 * indication that the bootloader activated the link.
245 regmap_read(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
, &gpr1
);
246 regmap_read(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
, &gpr12
);
248 if ((gpr1
& IMX6Q_GPR1_PCIE_REF_CLK_EN
) &&
249 (gpr12
& IMX6Q_GPR12_PCIE_CTL_2
)) {
250 val
= readl(pp
->dbi_base
+ PCIE_PL_PFLR
);
251 val
&= ~PCIE_PL_PFLR_LINK_STATE_MASK
;
252 val
|= PCIE_PL_PFLR_FORCE_LINK
;
253 writel(val
, pp
->dbi_base
+ PCIE_PL_PFLR
);
255 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
256 IMX6Q_GPR12_PCIE_CTL_2
, 0 << 10);
259 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
260 IMX6Q_GPR1_PCIE_TEST_PD
, 1 << 18);
261 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
262 IMX6Q_GPR1_PCIE_REF_CLK_EN
, 0 << 16);
267 static int imx6_pcie_deassert_core_reset(struct pcie_port
*pp
)
269 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
272 ret
= clk_prepare_enable(imx6_pcie
->pcie_phy
);
274 dev_err(pp
->dev
, "unable to enable pcie_phy clock\n");
278 ret
= clk_prepare_enable(imx6_pcie
->pcie_bus
);
280 dev_err(pp
->dev
, "unable to enable pcie_bus clock\n");
284 ret
= clk_prepare_enable(imx6_pcie
->pcie
);
286 dev_err(pp
->dev
, "unable to enable pcie clock\n");
290 /* power up core phy and enable ref clock */
291 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
292 IMX6Q_GPR1_PCIE_TEST_PD
, 0 << 18);
294 * the async reset input need ref clock to sync internally,
295 * when the ref clock comes after reset, internal synced
296 * reset time is too short, cannot meet the requirement.
297 * add one ~10us delay here.
300 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
301 IMX6Q_GPR1_PCIE_REF_CLK_EN
, 1 << 16);
303 /* allow the clocks to stabilize */
304 usleep_range(200, 500);
306 /* Some boards don't have PCIe reset GPIO. */
307 if (imx6_pcie
->reset_gpio
) {
308 gpiod_set_value_cansleep(imx6_pcie
->reset_gpio
, 0);
310 gpiod_set_value_cansleep(imx6_pcie
->reset_gpio
, 1);
315 clk_disable_unprepare(imx6_pcie
->pcie_bus
);
317 clk_disable_unprepare(imx6_pcie
->pcie_phy
);
323 static void imx6_pcie_init_phy(struct pcie_port
*pp
)
325 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
327 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
328 IMX6Q_GPR12_PCIE_CTL_2
, 0 << 10);
330 /* configure constant input signal to the pcie ctrl and phy */
331 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
332 IMX6Q_GPR12_DEVICE_TYPE
, PCI_EXP_TYPE_ROOT_PORT
<< 12);
333 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
334 IMX6Q_GPR12_LOS_LEVEL
, 9 << 4);
336 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
337 IMX6Q_GPR8_TX_DEEMPH_GEN1
, 0 << 0);
338 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
339 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB
, 0 << 6);
340 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
341 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB
, 20 << 12);
342 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
343 IMX6Q_GPR8_TX_SWING_FULL
, 127 << 18);
344 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
345 IMX6Q_GPR8_TX_SWING_LOW
, 127 << 25);
348 static int imx6_pcie_wait_for_link(struct pcie_port
*pp
)
350 unsigned int retries
;
352 for (retries
= 0; retries
< 200; retries
++) {
353 if (dw_pcie_link_up(pp
))
355 usleep_range(100, 1000);
358 dev_err(pp
->dev
, "phy link never came up\n");
359 dev_dbg(pp
->dev
, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
360 readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R0
),
361 readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
));
365 static int imx6_pcie_wait_for_speed_change(struct pcie_port
*pp
)
368 unsigned int retries
;
370 for (retries
= 0; retries
< 200; retries
++) {
371 tmp
= readl(pp
->dbi_base
+ PCIE_LINK_WIDTH_SPEED_CONTROL
);
372 /* Test if the speed change finished. */
373 if (!(tmp
& PORT_LOGIC_SPEED_CHANGE
))
375 usleep_range(100, 1000);
378 dev_err(pp
->dev
, "Speed change timeout\n");
382 static irqreturn_t
imx6_pcie_msi_handler(int irq
, void *arg
)
384 struct pcie_port
*pp
= arg
;
386 return dw_handle_msi_irq(pp
);
389 static int imx6_pcie_establish_link(struct pcie_port
*pp
)
391 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
396 * Force Gen1 operation when starting the link. In case the link is
397 * started in Gen2 mode, there is a possibility the devices on the
398 * bus will not be detected at all. This happens with PCIe switches.
400 tmp
= readl(pp
->dbi_base
+ PCIE_RC_LCR
);
401 tmp
&= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
;
402 tmp
|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1
;
403 writel(tmp
, pp
->dbi_base
+ PCIE_RC_LCR
);
406 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
407 IMX6Q_GPR12_PCIE_CTL_2
, 1 << 10);
409 ret
= imx6_pcie_wait_for_link(pp
);
413 /* Allow Gen2 mode after the link is up. */
414 tmp
= readl(pp
->dbi_base
+ PCIE_RC_LCR
);
415 tmp
&= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
;
416 tmp
|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2
;
417 writel(tmp
, pp
->dbi_base
+ PCIE_RC_LCR
);
420 * Start Directed Speed Change so the best possible speed both link
421 * partners support can be negotiated.
423 tmp
= readl(pp
->dbi_base
+ PCIE_LINK_WIDTH_SPEED_CONTROL
);
424 tmp
|= PORT_LOGIC_SPEED_CHANGE
;
425 writel(tmp
, pp
->dbi_base
+ PCIE_LINK_WIDTH_SPEED_CONTROL
);
427 ret
= imx6_pcie_wait_for_speed_change(pp
);
429 dev_err(pp
->dev
, "Failed to bring link up!\n");
433 /* Make sure link training is finished as well! */
434 ret
= imx6_pcie_wait_for_link(pp
);
436 dev_err(pp
->dev
, "Failed to bring link up!\n");
440 tmp
= readl(pp
->dbi_base
+ PCIE_RC_LCSR
);
441 dev_dbg(pp
->dev
, "Link up, Gen=%i\n", (tmp
>> 16) & 0xf);
445 static void imx6_pcie_host_init(struct pcie_port
*pp
)
447 imx6_pcie_assert_core_reset(pp
);
449 imx6_pcie_init_phy(pp
);
451 imx6_pcie_deassert_core_reset(pp
);
453 dw_pcie_setup_rc(pp
);
455 imx6_pcie_establish_link(pp
);
457 if (IS_ENABLED(CONFIG_PCI_MSI
))
458 dw_pcie_msi_init(pp
);
461 static int imx6_pcie_link_up(struct pcie_port
*pp
)
463 u32 rc
, debug_r0
, rx_valid
;
467 * Test if the PHY reports that the link is up and also that the LTSSM
468 * training finished. There are three possible states of the link when
469 * this code is called:
470 * 1) The link is DOWN (unlikely)
471 * The link didn't come up yet for some reason. This usually means
472 * we have a real problem somewhere. Reset the PHY and exit. This
473 * state calls for inspection of the DEBUG registers.
474 * 2) The link is UP, but still in LTSSM training
475 * Wait for the training to finish, which should take a very short
476 * time. If the training does not finish, we have a problem and we
477 * need to inspect the DEBUG registers. If the training does finish,
478 * the link is up and operating correctly.
479 * 3) The link is UP and no longer in LTSSM training
480 * The link is up and operating correctly.
483 rc
= readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
);
484 if (!(rc
& PCIE_PHY_DEBUG_R1_XMLH_LINK_UP
))
486 if (!(rc
& PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING
))
490 dev_dbg(pp
->dev
, "Link is up, but still in training\n");
492 * Wait a little bit, then re-check if the link finished
495 usleep_range(1000, 2000);
498 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
499 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
500 * If (MAC/LTSSM.state == Recovery.RcvrLock)
501 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
504 pcie_phy_read(pp
->dbi_base
, PCIE_PHY_RX_ASIC_OUT
, &rx_valid
);
505 debug_r0
= readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R0
);
507 if (rx_valid
& PCIE_PHY_RX_ASIC_OUT_VALID
)
510 if ((debug_r0
& 0x3f) != 0x0d)
513 dev_err(pp
->dev
, "transition to gen2 is stuck, reset PHY!\n");
514 dev_dbg(pp
->dev
, "debug_r0=%08x debug_r1=%08x\n", debug_r0
, rc
);
516 imx6_pcie_reset_phy(pp
);
521 static struct pcie_host_ops imx6_pcie_host_ops
= {
522 .link_up
= imx6_pcie_link_up
,
523 .host_init
= imx6_pcie_host_init
,
526 static int __init
imx6_add_pcie_port(struct pcie_port
*pp
,
527 struct platform_device
*pdev
)
531 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
532 pp
->msi_irq
= platform_get_irq_byname(pdev
, "msi");
533 if (pp
->msi_irq
<= 0) {
534 dev_err(&pdev
->dev
, "failed to get MSI irq\n");
538 ret
= devm_request_irq(&pdev
->dev
, pp
->msi_irq
,
539 imx6_pcie_msi_handler
,
540 IRQF_SHARED
| IRQF_NO_THREAD
,
543 dev_err(&pdev
->dev
, "failed to request MSI irq\n");
548 pp
->root_bus_nr
= -1;
549 pp
->ops
= &imx6_pcie_host_ops
;
551 ret
= dw_pcie_host_init(pp
);
553 dev_err(&pdev
->dev
, "failed to initialize host\n");
560 static int __init
imx6_pcie_probe(struct platform_device
*pdev
)
562 struct imx6_pcie
*imx6_pcie
;
563 struct pcie_port
*pp
;
564 struct resource
*dbi_base
;
567 imx6_pcie
= devm_kzalloc(&pdev
->dev
, sizeof(*imx6_pcie
), GFP_KERNEL
);
572 pp
->dev
= &pdev
->dev
;
574 /* Added for PCI abort handling */
575 hook_fault_code(16 + 6, imx6q_pcie_abort_handler
, SIGBUS
, 0,
576 "imprecise external abort");
578 dbi_base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
579 pp
->dbi_base
= devm_ioremap_resource(&pdev
->dev
, dbi_base
);
580 if (IS_ERR(pp
->dbi_base
))
581 return PTR_ERR(pp
->dbi_base
);
584 imx6_pcie
->reset_gpio
= devm_gpiod_get_optional(&pdev
->dev
, "reset",
588 imx6_pcie
->pcie_phy
= devm_clk_get(&pdev
->dev
, "pcie_phy");
589 if (IS_ERR(imx6_pcie
->pcie_phy
)) {
591 "pcie_phy clock source missing or invalid\n");
592 return PTR_ERR(imx6_pcie
->pcie_phy
);
595 imx6_pcie
->pcie_bus
= devm_clk_get(&pdev
->dev
, "pcie_bus");
596 if (IS_ERR(imx6_pcie
->pcie_bus
)) {
598 "pcie_bus clock source missing or invalid\n");
599 return PTR_ERR(imx6_pcie
->pcie_bus
);
602 imx6_pcie
->pcie
= devm_clk_get(&pdev
->dev
, "pcie");
603 if (IS_ERR(imx6_pcie
->pcie
)) {
605 "pcie clock source missing or invalid\n");
606 return PTR_ERR(imx6_pcie
->pcie
);
609 /* Grab GPR config register range */
610 imx6_pcie
->iomuxc_gpr
=
611 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
612 if (IS_ERR(imx6_pcie
->iomuxc_gpr
)) {
613 dev_err(&pdev
->dev
, "unable to find iomuxc registers\n");
614 return PTR_ERR(imx6_pcie
->iomuxc_gpr
);
617 ret
= imx6_add_pcie_port(pp
, pdev
);
621 platform_set_drvdata(pdev
, imx6_pcie
);
625 static void imx6_pcie_shutdown(struct platform_device
*pdev
)
627 struct imx6_pcie
*imx6_pcie
= platform_get_drvdata(pdev
);
629 /* bring down link, so bootloader gets clean state in case of reboot */
630 imx6_pcie_assert_core_reset(&imx6_pcie
->pp
);
633 static const struct of_device_id imx6_pcie_of_match
[] = {
634 { .compatible
= "fsl,imx6q-pcie", },
637 MODULE_DEVICE_TABLE(of
, imx6_pcie_of_match
);
639 static struct platform_driver imx6_pcie_driver
= {
641 .name
= "imx6q-pcie",
642 .of_match_table
= imx6_pcie_of_match
,
644 .shutdown
= imx6_pcie_shutdown
,
647 /* Freescale PCIe driver does not allow module unload */
649 static int __init
imx6_pcie_init(void)
651 return platform_driver_probe(&imx6_pcie_driver
, imx6_pcie_probe
);
653 module_init(imx6_pcie_init
);
655 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
656 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
657 MODULE_LICENSE("GPL v2");