drivers/pci/host/pci-layerscape.c

   1 /*
   2  * PCIe host controller driver for Freescale Layerscape SoCs
   3  *
   4  * Copyright (C) 2014 Freescale Semiconductor.
   5  *
   6   * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/resource.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/regmap.h>
  26
  27 #include "pcie-designware.h"
  28
  29 /* PEX1/2 Misc Ports Status Register */
  30 #define SCFG_PEXMSCPORTSR(pex_idx)      (0x94 + (pex_idx) * 4)
  31 #define LTSSM_STATE_SHIFT       20
  32 #define LTSSM_STATE_MASK        0x3f
  33 #define LTSSM_PCIE_L0           0x11 /* L0 state */
  34
  35 /* Symbol Timer Register and Filter Mask Register 1 */
  36 #define PCIE_STRFMR1 0x71c
  37
  38 struct ls_pcie {
  39         struct list_head node;
  40         struct device *dev;
  41         struct pci_bus *bus;
  42         void __iomem *dbi;
  43         struct regmap *scfg;
  44         struct pcie_port pp;
  45         int index;
  46         int msi_irq;
  47 };
  48
  49 #define to_ls_pcie(x)   container_of(x, struct ls_pcie, pp)
  50
  51 static int ls_pcie_link_up(struct pcie_port *pp)
  52 {
  53         u32 state;
  54         struct ls_pcie *pcie = to_ls_pcie(pp);
  55
  56         regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
  57         state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  58
  59         if (state < LTSSM_PCIE_L0)
  60                 return 0;
  61
  62         return 1;
  63 }
  64
  65 static int ls_pcie_establish_link(struct pcie_port *pp)
  66 {
  67         int count = 0;
  68
  69         while (!dw_pcie_link_up(pp)) {
  70                 usleep_range(100, 1000);
  71                 count++;
  72                 if (count >= 200) {
  73                         dev_err(pp->dev, "phy link never came up\n");
  74                         return -EINVAL;
  75                 }
  76         }
  77
  78         return 0;
  79 }
  80
  81 static void ls_pcie_host_init(struct pcie_port *pp)
  82 {
  83         struct ls_pcie *pcie = to_ls_pcie(pp);
  84         u32 val;
  85
  86         dw_pcie_setup_rc(pp);
  87         ls_pcie_establish_link(pp);
  88
  89         /*
  90          * LS1021A Workaround for internal TKT228622
  91          * to fix the INTx hang issue
  92          */
  93         val = ioread32(pcie->dbi + PCIE_STRFMR1);
  94         val &= 0xffff;
  95         iowrite32(val, pcie->dbi + PCIE_STRFMR1);
  96 }
  97
  98 static struct pcie_host_ops ls_pcie_host_ops = {
  99         .link_up = ls_pcie_link_up,
 100         .host_init = ls_pcie_host_init,
 101 };
 102
 103 static int ls_add_pcie_port(struct ls_pcie *pcie)
 104 {
 105         struct pcie_port *pp;
 106         int ret;
 107
 108         pp = &pcie->pp;
 109         pp->dev = pcie->dev;
 110         pp->dbi_base = pcie->dbi;
 111         pp->root_bus_nr = -1;
 112         pp->ops = &ls_pcie_host_ops;
 113
 114         ret = dw_pcie_host_init(pp);
 115         if (ret) {
 116                 dev_err(pp->dev, "failed to initialize host\n");
 117                 return ret;
 118         }
 119
 120         return 0;
 121 }
 122
 123 static int __init ls_pcie_probe(struct platform_device *pdev)
 124 {
 125         struct ls_pcie *pcie;
 126         struct resource *dbi_base;
 127         u32 index[2];
 128         int ret;
 129
 130         pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
 131         if (!pcie)
 132                 return -ENOMEM;
 133
 134         pcie->dev = &pdev->dev;
 135
 136         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 137         pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
 138         if (IS_ERR(pcie->dbi)) {
 139                 dev_err(&pdev->dev, "missing *regs* space\n");
 140                 return PTR_ERR(pcie->dbi);
 141         }
 142
 143         pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 144                                                      "fsl,pcie-scfg");
 145         if (IS_ERR(pcie->scfg)) {
 146                 dev_err(&pdev->dev, "No syscfg phandle specified\n");
 147                 return PTR_ERR(pcie->scfg);
 148         }
 149
 150         ret = of_property_read_u32_array(pdev->dev.of_node,
 151                                          "fsl,pcie-scfg", index, 2);
 152         if (ret)
 153                 return ret;
 154         pcie->index = index[1];
 155
 156         ret = ls_add_pcie_port(pcie);
 157         if (ret < 0)
 158                 return ret;
 159
 160         platform_set_drvdata(pdev, pcie);
 161
 162         return 0;
 163 }
 164
 165 static const struct of_device_id ls_pcie_of_match[] = {
 166         { .compatible = "fsl,ls1021a-pcie" },
 167         { },
 168 };
 169 MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
 170
 171 static struct platform_driver ls_pcie_driver = {
 172         .driver = {
 173                 .name = "layerscape-pcie",
 174                 .of_match_table = ls_pcie_of_match,
 175         },
 176 };
 177
 178 module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
 179
 180 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
 181 MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
 182 MODULE_LICENSE("GPL v2");