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PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlock
[deliverable/linux.git] / drivers / pci / host / pci-mvebu.c
1 /*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24
25 /*
26 * PCIe unit register offsets.
27 */
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63 /* PCI configuration space of a PCI-to-PCI bridge */
64 struct mvebu_sw_pci_bridge {
65 u16 vendor;
66 u16 device;
67 u16 command;
68 u16 class;
69 u8 interface;
70 u8 revision;
71 u8 bist;
72 u8 header_type;
73 u8 latency_timer;
74 u8 cache_line_size;
75 u32 bar[2];
76 u8 primary_bus;
77 u8 secondary_bus;
78 u8 subordinate_bus;
79 u8 secondary_latency_timer;
80 u8 iobase;
81 u8 iolimit;
82 u16 secondary_status;
83 u16 membase;
84 u16 memlimit;
85 u16 iobaseupper;
86 u16 iolimitupper;
87 u8 cappointer;
88 u8 reserved1;
89 u16 reserved2;
90 u32 romaddr;
91 u8 intline;
92 u8 intpin;
93 u16 bridgectrl;
94 };
95
96 struct mvebu_pcie_port;
97
98 /* Structure representing all PCIe interfaces */
99 struct mvebu_pcie {
100 struct platform_device *pdev;
101 struct mvebu_pcie_port *ports;
102 struct msi_chip *msi;
103 struct resource io;
104 char io_name[30];
105 struct resource realio;
106 char mem_name[30];
107 struct resource mem;
108 struct resource busn;
109 int nports;
110 };
111
112 /* Structure representing one PCIe interface */
113 struct mvebu_pcie_port {
114 char *name;
115 void __iomem *base;
116 u32 port;
117 u32 lane;
118 int devfn;
119 unsigned int mem_target;
120 unsigned int mem_attr;
121 unsigned int io_target;
122 unsigned int io_attr;
123 struct clk *clk;
124 int reset_gpio;
125 int reset_active_low;
126 char *reset_name;
127 struct mvebu_sw_pci_bridge bridge;
128 struct device_node *dn;
129 struct mvebu_pcie *pcie;
130 phys_addr_t memwin_base;
131 size_t memwin_size;
132 phys_addr_t iowin_base;
133 size_t iowin_size;
134 };
135
136 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
137 {
138 writel(val, port->base + reg);
139 }
140
141 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
142 {
143 return readl(port->base + reg);
144 }
145
146 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
147 {
148 return port->io_target != -1 && port->io_attr != -1;
149 }
150
151 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
152 {
153 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
154 }
155
156 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
157 {
158 u32 stat;
159
160 stat = mvebu_readl(port, PCIE_STAT_OFF);
161 stat &= ~PCIE_STAT_BUS;
162 stat |= nr << 8;
163 mvebu_writel(port, stat, PCIE_STAT_OFF);
164 }
165
166 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
167 {
168 u32 stat;
169
170 stat = mvebu_readl(port, PCIE_STAT_OFF);
171 stat &= ~PCIE_STAT_DEV;
172 stat |= nr << 16;
173 mvebu_writel(port, stat, PCIE_STAT_OFF);
174 }
175
176 /*
177 * Setup PCIE BARs and Address Decode Wins:
178 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
179 * WIN[0-3] -> DRAM bank[0-3]
180 */
181 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
182 {
183 const struct mbus_dram_target_info *dram;
184 u32 size;
185 int i;
186
187 dram = mv_mbus_dram_info();
188
189 /* First, disable and clear BARs and windows. */
190 for (i = 1; i < 3; i++) {
191 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
192 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
193 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
194 }
195
196 for (i = 0; i < 5; i++) {
197 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
198 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
199 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
200 }
201
202 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
203 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
204 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
205
206 /* Setup windows for DDR banks. Count total DDR size on the fly. */
207 size = 0;
208 for (i = 0; i < dram->num_cs; i++) {
209 const struct mbus_dram_window *cs = dram->cs + i;
210
211 mvebu_writel(port, cs->base & 0xffff0000,
212 PCIE_WIN04_BASE_OFF(i));
213 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
214 mvebu_writel(port,
215 ((cs->size - 1) & 0xffff0000) |
216 (cs->mbus_attr << 8) |
217 (dram->mbus_dram_target_id << 4) | 1,
218 PCIE_WIN04_CTRL_OFF(i));
219
220 size += cs->size;
221 }
222
223 /* Round up 'size' to the nearest power of two. */
224 if ((size & (size - 1)) != 0)
225 size = 1 << fls(size);
226
227 /* Setup BAR[1] to all DRAM banks. */
228 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
229 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
230 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
231 PCIE_BAR_CTRL_OFF(1));
232 }
233
234 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
235 {
236 u32 cmd, mask;
237
238 /* Point PCIe unit MBUS decode windows to DRAM space. */
239 mvebu_pcie_setup_wins(port);
240
241 /* Master + slave enable. */
242 cmd = mvebu_readl(port, PCIE_CMD_OFF);
243 cmd |= PCI_COMMAND_IO;
244 cmd |= PCI_COMMAND_MEMORY;
245 cmd |= PCI_COMMAND_MASTER;
246 mvebu_writel(port, cmd, PCIE_CMD_OFF);
247
248 /* Enable interrupt lines A-D. */
249 mask = mvebu_readl(port, PCIE_MASK_OFF);
250 mask |= PCIE_MASK_ENABLE_INTS;
251 mvebu_writel(port, mask, PCIE_MASK_OFF);
252 }
253
254 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
255 struct pci_bus *bus,
256 u32 devfn, int where, int size, u32 *val)
257 {
258 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
259 PCIE_CONF_ADDR_OFF);
260
261 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
262
263 if (size == 1)
264 *val = (*val >> (8 * (where & 3))) & 0xff;
265 else if (size == 2)
266 *val = (*val >> (8 * (where & 3))) & 0xffff;
267
268 return PCIBIOS_SUCCESSFUL;
269 }
270
271 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
272 struct pci_bus *bus,
273 u32 devfn, int where, int size, u32 val)
274 {
275 u32 _val, shift = 8 * (where & 3);
276
277 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
278 PCIE_CONF_ADDR_OFF);
279 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
280
281 if (size == 4)
282 _val = val;
283 else if (size == 2)
284 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
285 else if (size == 1)
286 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
287 else
288 return PCIBIOS_BAD_REGISTER_NUMBER;
289
290 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
291
292 return PCIBIOS_SUCCESSFUL;
293 }
294
295 /*
296 * Remove windows, starting from the largest ones to the smallest
297 * ones.
298 */
299 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
300 phys_addr_t base, size_t size)
301 {
302 while (size) {
303 size_t sz = 1 << (fls(size) - 1);
304
305 mvebu_mbus_del_window(base, sz);
306 base += sz;
307 size -= sz;
308 }
309 }
310
311 /*
312 * MBus windows can only have a power of two size, but PCI BARs do not
313 * have this constraint. Therefore, we have to split the PCI BAR into
314 * areas each having a power of two size. We start from the largest
315 * one (i.e highest order bit set in the size).
316 */
317 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
318 unsigned int target, unsigned int attribute,
319 phys_addr_t base, size_t size,
320 phys_addr_t remap)
321 {
322 size_t size_mapped = 0;
323
324 while (size) {
325 size_t sz = 1 << (fls(size) - 1);
326 int ret;
327
328 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
329 sz, remap);
330 if (ret) {
331 dev_err(&port->pcie->pdev->dev,
332 "Could not create MBus window at 0x%x, size 0x%x: %d\n",
333 base, sz, ret);
334 mvebu_pcie_del_windows(port, base - size_mapped,
335 size_mapped);
336 return;
337 }
338
339 size -= sz;
340 size_mapped += sz;
341 base += sz;
342 if (remap != MVEBU_MBUS_NO_REMAP)
343 remap += sz;
344 }
345 }
346
347 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
348 {
349 phys_addr_t iobase;
350
351 /* Are the new iobase/iolimit values invalid? */
352 if (port->bridge.iolimit < port->bridge.iobase ||
353 port->bridge.iolimitupper < port->bridge.iobaseupper ||
354 !(port->bridge.command & PCI_COMMAND_IO)) {
355
356 /* If a window was configured, remove it */
357 if (port->iowin_base) {
358 mvebu_pcie_del_windows(port, port->iowin_base,
359 port->iowin_size);
360 port->iowin_base = 0;
361 port->iowin_size = 0;
362 }
363
364 return;
365 }
366
367 if (!mvebu_has_ioport(port)) {
368 dev_WARN(&port->pcie->pdev->dev,
369 "Attempt to set IO when IO is disabled\n");
370 return;
371 }
372
373 /*
374 * We read the PCI-to-PCI bridge emulated registers, and
375 * calculate the base address and size of the address decoding
376 * window to setup, according to the PCI-to-PCI bridge
377 * specifications. iobase is the bus address, port->iowin_base
378 * is the CPU address.
379 */
380 iobase = ((port->bridge.iobase & 0xF0) << 8) |
381 (port->bridge.iobaseupper << 16);
382 port->iowin_base = port->pcie->io.start + iobase;
383 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
384 (port->bridge.iolimitupper << 16)) -
385 iobase) + 1;
386
387 mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
388 port->iowin_base, port->iowin_size,
389 iobase);
390 }
391
392 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
393 {
394 /* Are the new membase/memlimit values invalid? */
395 if (port->bridge.memlimit < port->bridge.membase ||
396 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
397
398 /* If a window was configured, remove it */
399 if (port->memwin_base) {
400 mvebu_pcie_del_windows(port, port->memwin_base,
401 port->memwin_size);
402 port->memwin_base = 0;
403 port->memwin_size = 0;
404 }
405
406 return;
407 }
408
409 /*
410 * We read the PCI-to-PCI bridge emulated registers, and
411 * calculate the base address and size of the address decoding
412 * window to setup, according to the PCI-to-PCI bridge
413 * specifications.
414 */
415 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
416 port->memwin_size =
417 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
418 port->memwin_base + 1;
419
420 mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
421 port->memwin_base, port->memwin_size,
422 MVEBU_MBUS_NO_REMAP);
423 }
424
425 /*
426 * Initialize the configuration space of the PCI-to-PCI bridge
427 * associated with the given PCIe interface.
428 */
429 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
430 {
431 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
432
433 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
434
435 bridge->class = PCI_CLASS_BRIDGE_PCI;
436 bridge->vendor = PCI_VENDOR_ID_MARVELL;
437 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
438 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
439 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
440 bridge->cache_line_size = 0x10;
441
442 /* We support 32 bits I/O addressing */
443 bridge->iobase = PCI_IO_RANGE_TYPE_32;
444 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
445 }
446
447 /*
448 * Read the configuration space of the PCI-to-PCI bridge associated to
449 * the given PCIe interface.
450 */
451 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
452 unsigned int where, int size, u32 *value)
453 {
454 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
455
456 switch (where & ~3) {
457 case PCI_VENDOR_ID:
458 *value = bridge->device << 16 | bridge->vendor;
459 break;
460
461 case PCI_COMMAND:
462 *value = bridge->command;
463 break;
464
465 case PCI_CLASS_REVISION:
466 *value = bridge->class << 16 | bridge->interface << 8 |
467 bridge->revision;
468 break;
469
470 case PCI_CACHE_LINE_SIZE:
471 *value = bridge->bist << 24 | bridge->header_type << 16 |
472 bridge->latency_timer << 8 | bridge->cache_line_size;
473 break;
474
475 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
476 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
477 break;
478
479 case PCI_PRIMARY_BUS:
480 *value = (bridge->secondary_latency_timer << 24 |
481 bridge->subordinate_bus << 16 |
482 bridge->secondary_bus << 8 |
483 bridge->primary_bus);
484 break;
485
486 case PCI_IO_BASE:
487 if (!mvebu_has_ioport(port))
488 *value = bridge->secondary_status << 16;
489 else
490 *value = (bridge->secondary_status << 16 |
491 bridge->iolimit << 8 |
492 bridge->iobase);
493 break;
494
495 case PCI_MEMORY_BASE:
496 *value = (bridge->memlimit << 16 | bridge->membase);
497 break;
498
499 case PCI_PREF_MEMORY_BASE:
500 *value = 0;
501 break;
502
503 case PCI_IO_BASE_UPPER16:
504 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
505 break;
506
507 case PCI_ROM_ADDRESS1:
508 *value = 0;
509 break;
510
511 case PCI_INTERRUPT_LINE:
512 /* LINE PIN MIN_GNT MAX_LAT */
513 *value = 0;
514 break;
515
516 default:
517 *value = 0xffffffff;
518 return PCIBIOS_BAD_REGISTER_NUMBER;
519 }
520
521 if (size == 2)
522 *value = (*value >> (8 * (where & 3))) & 0xffff;
523 else if (size == 1)
524 *value = (*value >> (8 * (where & 3))) & 0xff;
525
526 return PCIBIOS_SUCCESSFUL;
527 }
528
529 /* Write to the PCI-to-PCI bridge configuration space */
530 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
531 unsigned int where, int size, u32 value)
532 {
533 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
534 u32 mask, reg;
535 int err;
536
537 if (size == 4)
538 mask = 0x0;
539 else if (size == 2)
540 mask = ~(0xffff << ((where & 3) * 8));
541 else if (size == 1)
542 mask = ~(0xff << ((where & 3) * 8));
543 else
544 return PCIBIOS_BAD_REGISTER_NUMBER;
545
546 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
547 if (err)
548 return err;
549
550 value = (reg & mask) | value << ((where & 3) * 8);
551
552 switch (where & ~3) {
553 case PCI_COMMAND:
554 {
555 u32 old = bridge->command;
556
557 if (!mvebu_has_ioport(port))
558 value &= ~PCI_COMMAND_IO;
559
560 bridge->command = value & 0xffff;
561 if ((old ^ bridge->command) & PCI_COMMAND_IO)
562 mvebu_pcie_handle_iobase_change(port);
563 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
564 mvebu_pcie_handle_membase_change(port);
565 break;
566 }
567
568 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
569 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
570 break;
571
572 case PCI_IO_BASE:
573 /*
574 * We also keep bit 1 set, it is a read-only bit that
575 * indicates we support 32 bits addressing for the
576 * I/O
577 */
578 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
579 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
580 mvebu_pcie_handle_iobase_change(port);
581 break;
582
583 case PCI_MEMORY_BASE:
584 bridge->membase = value & 0xffff;
585 bridge->memlimit = value >> 16;
586 mvebu_pcie_handle_membase_change(port);
587 break;
588
589 case PCI_IO_BASE_UPPER16:
590 bridge->iobaseupper = value & 0xffff;
591 bridge->iolimitupper = value >> 16;
592 mvebu_pcie_handle_iobase_change(port);
593 break;
594
595 case PCI_PRIMARY_BUS:
596 bridge->primary_bus = value & 0xff;
597 bridge->secondary_bus = (value >> 8) & 0xff;
598 bridge->subordinate_bus = (value >> 16) & 0xff;
599 bridge->secondary_latency_timer = (value >> 24) & 0xff;
600 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
601 break;
602
603 default:
604 break;
605 }
606
607 return PCIBIOS_SUCCESSFUL;
608 }
609
610 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
611 {
612 return sys->private_data;
613 }
614
615 static struct mvebu_pcie_port *
616 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
617 int devfn)
618 {
619 int i;
620
621 for (i = 0; i < pcie->nports; i++) {
622 struct mvebu_pcie_port *port = &pcie->ports[i];
623 if (bus->number == 0 && port->devfn == devfn)
624 return port;
625 if (bus->number != 0 &&
626 bus->number >= port->bridge.secondary_bus &&
627 bus->number <= port->bridge.subordinate_bus)
628 return port;
629 }
630
631 return NULL;
632 }
633
634 /* PCI configuration space write function */
635 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
636 int where, int size, u32 val)
637 {
638 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
639 struct mvebu_pcie_port *port;
640 int ret;
641
642 port = mvebu_pcie_find_port(pcie, bus, devfn);
643 if (!port)
644 return PCIBIOS_DEVICE_NOT_FOUND;
645
646 /* Access the emulated PCI-to-PCI bridge */
647 if (bus->number == 0)
648 return mvebu_sw_pci_bridge_write(port, where, size, val);
649
650 if (!mvebu_pcie_link_up(port))
651 return PCIBIOS_DEVICE_NOT_FOUND;
652
653 /*
654 * On the secondary bus, we don't want to expose any other
655 * device than the device physically connected in the PCIe
656 * slot, visible in slot 0. In slot 1, there's a special
657 * Marvell device that only makes sense when the Armada is
658 * used as a PCIe endpoint.
659 */
660 if (bus->number == port->bridge.secondary_bus &&
661 PCI_SLOT(devfn) != 0)
662 return PCIBIOS_DEVICE_NOT_FOUND;
663
664 /* Access the real PCIe interface */
665 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
666 where, size, val);
667
668 return ret;
669 }
670
671 /* PCI configuration space read function */
672 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
673 int size, u32 *val)
674 {
675 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
676 struct mvebu_pcie_port *port;
677 int ret;
678
679 port = mvebu_pcie_find_port(pcie, bus, devfn);
680 if (!port) {
681 *val = 0xffffffff;
682 return PCIBIOS_DEVICE_NOT_FOUND;
683 }
684
685 /* Access the emulated PCI-to-PCI bridge */
686 if (bus->number == 0)
687 return mvebu_sw_pci_bridge_read(port, where, size, val);
688
689 if (!mvebu_pcie_link_up(port)) {
690 *val = 0xffffffff;
691 return PCIBIOS_DEVICE_NOT_FOUND;
692 }
693
694 /*
695 * On the secondary bus, we don't want to expose any other
696 * device than the device physically connected in the PCIe
697 * slot, visible in slot 0. In slot 1, there's a special
698 * Marvell device that only makes sense when the Armada is
699 * used as a PCIe endpoint.
700 */
701 if (bus->number == port->bridge.secondary_bus &&
702 PCI_SLOT(devfn) != 0) {
703 *val = 0xffffffff;
704 return PCIBIOS_DEVICE_NOT_FOUND;
705 }
706
707 /* Access the real PCIe interface */
708 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
709 where, size, val);
710
711 return ret;
712 }
713
714 static struct pci_ops mvebu_pcie_ops = {
715 .read = mvebu_pcie_rd_conf,
716 .write = mvebu_pcie_wr_conf,
717 };
718
719 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
720 {
721 struct mvebu_pcie *pcie = sys_to_pcie(sys);
722 int i;
723 int domain = 0;
724
725 #ifdef CONFIG_PCI_DOMAINS
726 domain = sys->domain;
727 #endif
728
729 snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
730 domain);
731 pcie->mem.name = pcie->mem_name;
732
733 snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
734 pcie->realio.name = pcie->io_name;
735
736 if (request_resource(&iomem_resource, &pcie->mem))
737 return 0;
738
739 if (resource_size(&pcie->realio) != 0) {
740 if (request_resource(&ioport_resource, &pcie->realio)) {
741 release_resource(&pcie->mem);
742 return 0;
743 }
744 pci_add_resource_offset(&sys->resources, &pcie->realio,
745 sys->io_offset);
746 }
747 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
748 pci_add_resource(&sys->resources, &pcie->busn);
749
750 for (i = 0; i < pcie->nports; i++) {
751 struct mvebu_pcie_port *port = &pcie->ports[i];
752 if (!port->base)
753 continue;
754 mvebu_pcie_setup_hw(port);
755 }
756
757 return 1;
758 }
759
760 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
761 {
762 struct mvebu_pcie *pcie = sys_to_pcie(sys);
763 struct pci_bus *bus;
764
765 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
766 &mvebu_pcie_ops, sys, &sys->resources);
767 if (!bus)
768 return NULL;
769
770 pci_scan_child_bus(bus);
771
772 return bus;
773 }
774
775 static void mvebu_pcie_add_bus(struct pci_bus *bus)
776 {
777 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
778 bus->msi = pcie->msi;
779 }
780
781 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
782 const struct resource *res,
783 resource_size_t start,
784 resource_size_t size,
785 resource_size_t align)
786 {
787 if (dev->bus->number != 0)
788 return start;
789
790 /*
791 * On the PCI-to-PCI bridge side, the I/O windows must have at
792 * least a 64 KB size and the memory windows must have at
793 * least a 1 MB size. Moreover, MBus windows need to have a
794 * base address aligned on their size, and their size must be
795 * a power of two. This means that if the BAR doesn't have a
796 * power of two size, several MBus windows will actually be
797 * created. We need to ensure that the biggest MBus window
798 * (which will be the first one) is aligned on its size, which
799 * explains the rounddown_pow_of_two() being done here.
800 */
801 if (res->flags & IORESOURCE_IO)
802 return round_up(start, max_t(resource_size_t, SZ_64K,
803 rounddown_pow_of_two(size)));
804 else if (res->flags & IORESOURCE_MEM)
805 return round_up(start, max_t(resource_size_t, SZ_1M,
806 rounddown_pow_of_two(size)));
807 else
808 return start;
809 }
810
811 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
812 {
813 struct hw_pci hw;
814
815 memset(&hw, 0, sizeof(hw));
816
817 hw.nr_controllers = 1;
818 hw.private_data = (void **)&pcie;
819 hw.setup = mvebu_pcie_setup;
820 hw.scan = mvebu_pcie_scan_bus;
821 hw.map_irq = of_irq_parse_and_map_pci;
822 hw.ops = &mvebu_pcie_ops;
823 hw.align_resource = mvebu_pcie_align_resource;
824 hw.add_bus = mvebu_pcie_add_bus;
825
826 pci_common_init(&hw);
827 }
828
829 /*
830 * Looks up the list of register addresses encoded into the reg =
831 * <...> property for one that matches the given port/lane. Once
832 * found, maps it.
833 */
834 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
835 struct device_node *np, struct mvebu_pcie_port *port)
836 {
837 struct resource regs;
838 int ret = 0;
839
840 ret = of_address_to_resource(np, 0, &regs);
841 if (ret)
842 return ERR_PTR(ret);
843
844 return devm_ioremap_resource(&pdev->dev, &regs);
845 }
846
847 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
848 #define DT_TYPE_IO 0x1
849 #define DT_TYPE_MEM32 0x2
850 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
851 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
852
853 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
854 unsigned long type,
855 unsigned int *tgt,
856 unsigned int *attr)
857 {
858 const int na = 3, ns = 2;
859 const __be32 *range;
860 int rlen, nranges, rangesz, pna, i;
861
862 *tgt = -1;
863 *attr = -1;
864
865 range = of_get_property(np, "ranges", &rlen);
866 if (!range)
867 return -EINVAL;
868
869 pna = of_n_addr_cells(np);
870 rangesz = pna + na + ns;
871 nranges = rlen / sizeof(__be32) / rangesz;
872
873 for (i = 0; i < nranges; i++) {
874 u32 flags = of_read_number(range, 1);
875 u32 slot = of_read_number(range + 1, 1);
876 u64 cpuaddr = of_read_number(range + na, pna);
877 unsigned long rtype;
878
879 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
880 rtype = IORESOURCE_IO;
881 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
882 rtype = IORESOURCE_MEM;
883
884 if (slot == PCI_SLOT(devfn) && type == rtype) {
885 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
886 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
887 return 0;
888 }
889
890 range += rangesz;
891 }
892
893 return -ENOENT;
894 }
895
896 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
897 {
898 struct device_node *msi_node;
899
900 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
901 "msi-parent", 0);
902 if (!msi_node)
903 return;
904
905 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
906
907 if (pcie->msi)
908 pcie->msi->dev = &pcie->pdev->dev;
909 }
910
911 static int mvebu_pcie_probe(struct platform_device *pdev)
912 {
913 struct mvebu_pcie *pcie;
914 struct device_node *np = pdev->dev.of_node;
915 struct device_node *child;
916 int i, ret;
917
918 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
919 GFP_KERNEL);
920 if (!pcie)
921 return -ENOMEM;
922
923 pcie->pdev = pdev;
924 platform_set_drvdata(pdev, pcie);
925
926 /* Get the PCIe memory and I/O aperture */
927 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
928 if (resource_size(&pcie->mem) == 0) {
929 dev_err(&pdev->dev, "invalid memory aperture size\n");
930 return -EINVAL;
931 }
932
933 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
934
935 if (resource_size(&pcie->io) != 0) {
936 pcie->realio.flags = pcie->io.flags;
937 pcie->realio.start = PCIBIOS_MIN_IO;
938 pcie->realio.end = min_t(resource_size_t,
939 IO_SPACE_LIMIT,
940 resource_size(&pcie->io));
941 } else
942 pcie->realio = pcie->io;
943
944 /* Get the bus range */
945 ret = of_pci_parse_bus_range(np, &pcie->busn);
946 if (ret) {
947 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
948 ret);
949 return ret;
950 }
951
952 i = 0;
953 for_each_child_of_node(pdev->dev.of_node, child) {
954 if (!of_device_is_available(child))
955 continue;
956 i++;
957 }
958
959 pcie->ports = devm_kzalloc(&pdev->dev, i *
960 sizeof(struct mvebu_pcie_port),
961 GFP_KERNEL);
962 if (!pcie->ports)
963 return -ENOMEM;
964
965 i = 0;
966 for_each_child_of_node(pdev->dev.of_node, child) {
967 struct mvebu_pcie_port *port = &pcie->ports[i];
968 enum of_gpio_flags flags;
969
970 if (!of_device_is_available(child))
971 continue;
972
973 port->pcie = pcie;
974
975 if (of_property_read_u32(child, "marvell,pcie-port",
976 &port->port)) {
977 dev_warn(&pdev->dev,
978 "ignoring PCIe DT node, missing pcie-port property\n");
979 continue;
980 }
981
982 if (of_property_read_u32(child, "marvell,pcie-lane",
983 &port->lane))
984 port->lane = 0;
985
986 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
987 port->port, port->lane);
988
989 port->devfn = of_pci_get_devfn(child);
990 if (port->devfn < 0)
991 continue;
992
993 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
994 &port->mem_target, &port->mem_attr);
995 if (ret < 0) {
996 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
997 port->port, port->lane);
998 continue;
999 }
1000
1001 if (resource_size(&pcie->io) != 0)
1002 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
1003 &port->io_target, &port->io_attr);
1004 else {
1005 port->io_target = -1;
1006 port->io_attr = -1;
1007 }
1008
1009 port->reset_gpio = of_get_named_gpio_flags(child,
1010 "reset-gpios", 0, &flags);
1011 if (gpio_is_valid(port->reset_gpio)) {
1012 u32 reset_udelay = 20000;
1013
1014 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
1015 port->reset_name = kasprintf(GFP_KERNEL,
1016 "pcie%d.%d-reset", port->port, port->lane);
1017 of_property_read_u32(child, "reset-delay-us",
1018 &reset_udelay);
1019
1020 ret = devm_gpio_request_one(&pdev->dev,
1021 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
1022 if (ret) {
1023 if (ret == -EPROBE_DEFER)
1024 return ret;
1025 continue;
1026 }
1027
1028 gpio_set_value(port->reset_gpio,
1029 (port->reset_active_low) ? 1 : 0);
1030 msleep(reset_udelay/1000);
1031 }
1032
1033 port->clk = of_clk_get_by_name(child, NULL);
1034 if (IS_ERR(port->clk)) {
1035 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
1036 port->port, port->lane);
1037 continue;
1038 }
1039
1040 ret = clk_prepare_enable(port->clk);
1041 if (ret)
1042 continue;
1043
1044 port->base = mvebu_pcie_map_registers(pdev, child, port);
1045 if (IS_ERR(port->base)) {
1046 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
1047 port->port, port->lane);
1048 port->base = NULL;
1049 clk_disable_unprepare(port->clk);
1050 continue;
1051 }
1052
1053 mvebu_pcie_set_local_dev_nr(port, 1);
1054
1055 port->dn = child;
1056 mvebu_sw_pci_bridge_init(port);
1057 i++;
1058 }
1059
1060 pcie->nports = i;
1061
1062 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
1063 pci_ioremap_io(i, pcie->io.start + i);
1064
1065 mvebu_pcie_msi_enable(pcie);
1066 mvebu_pcie_enable(pcie);
1067
1068 return 0;
1069 }
1070
1071 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1072 { .compatible = "marvell,armada-xp-pcie", },
1073 { .compatible = "marvell,armada-370-pcie", },
1074 { .compatible = "marvell,dove-pcie", },
1075 { .compatible = "marvell,kirkwood-pcie", },
1076 {},
1077 };
1078 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1079
1080 static struct platform_driver mvebu_pcie_driver = {
1081 .driver = {
1082 .owner = THIS_MODULE,
1083 .name = "mvebu-pcie",
1084 .of_match_table = mvebu_pcie_of_match_table,
1085 /* driver unloading/unbinding currently not supported */
1086 .suppress_bind_attrs = true,
1087 },
1088 .probe = mvebu_pcie_probe,
1089 };
1090 module_platform_driver(mvebu_pcie_driver);
1091
1092 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1093 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1094 MODULE_LICENSE("GPLv2");
Linux kernel - Deliverables
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