drivers/pci/host/pci-rcar-gen2.c

   1 /*
   2  *  pci-rcar-gen2: internal PCI bus support
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  * Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/sizes.h>
  25 #include <linux/slab.h>
  26
  27 /* AHB-PCI Bridge PCI communication registers */
  28 #define RCAR_AHBPCI_PCICOM_OFFSET       0x800
  29
  30 #define RCAR_PCIAHB_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  31 #define RCAR_PCIAHB_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  32 #define RCAR_PCIAHB_PREFETCH0           0x0
  33 #define RCAR_PCIAHB_PREFETCH4           0x1
  34 #define RCAR_PCIAHB_PREFETCH8           0x2
  35 #define RCAR_PCIAHB_PREFETCH16          0x3
  36
  37 #define RCAR_AHBPCI_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  38 #define RCAR_AHBPCI_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  39 #define RCAR_AHBPCI_WIN_CTR_MEM         (3 << 1)
  40 #define RCAR_AHBPCI_WIN_CTR_CFG         (5 << 1)
  41 #define RCAR_AHBPCI_WIN1_HOST           (1 << 30)
  42 #define RCAR_AHBPCI_WIN1_DEVICE         (1 << 31)
  43
  44 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  45 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  46 #define RCAR_PCI_INT_SIGTABORT          (1 << 0)
  47 #define RCAR_PCI_INT_SIGRETABORT        (1 << 1)
  48 #define RCAR_PCI_INT_REMABORT           (1 << 2)
  49 #define RCAR_PCI_INT_PERR               (1 << 3)
  50 #define RCAR_PCI_INT_SIGSERR            (1 << 4)
  51 #define RCAR_PCI_INT_RESERR             (1 << 5)
  52 #define RCAR_PCI_INT_WIN1ERR            (1 << 12)
  53 #define RCAR_PCI_INT_WIN2ERR            (1 << 13)
  54 #define RCAR_PCI_INT_A                  (1 << 16)
  55 #define RCAR_PCI_INT_B                  (1 << 17)
  56 #define RCAR_PCI_INT_PME                (1 << 19)
  57 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT          | \
  58                                 RCAR_PCI_INT_SIGRETABORT        | \
  59                                 RCAR_PCI_INT_SIGRETABORT        | \
  60                                 RCAR_PCI_INT_REMABORT           | \
  61                                 RCAR_PCI_INT_PERR               | \
  62                                 RCAR_PCI_INT_SIGSERR            | \
  63                                 RCAR_PCI_INT_RESERR             | \
  64                                 RCAR_PCI_INT_WIN1ERR            | \
  65                                 RCAR_PCI_INT_WIN2ERR)
  66
  67 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  68 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
  69 #define RCAR_AHB_BUS_MMODE_BYTE_BURST   (1 << 1)
  70 #define RCAR_AHB_BUS_MMODE_WR_INCR      (1 << 2)
  71 #define RCAR_AHB_BUS_MMODE_HBUS_REQ     (1 << 7)
  72 #define RCAR_AHB_BUS_SMODE_READYCTR     (1 << 17)
  73 #define RCAR_AHB_BUS_MODE               (RCAR_AHB_BUS_MMODE_HTRANS |    \
  74                                         RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  75                                         RCAR_AHB_BUS_MMODE_WR_INCR |    \
  76                                         RCAR_AHB_BUS_MMODE_HBUS_REQ |   \
  77                                         RCAR_AHB_BUS_SMODE_READYCTR)
  78
  79 #define RCAR_USBCTR_REG                 (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  80 #define RCAR_USBCTR_USBH_RST            (1 << 0)
  81 #define RCAR_USBCTR_PCICLK_MASK         (1 << 1)
  82 #define RCAR_USBCTR_PLL_RST             (1 << 2)
  83 #define RCAR_USBCTR_DIRPD               (1 << 8)
  84 #define RCAR_USBCTR_PCIAHB_WIN2_EN      (1 << 9)
  85 #define RCAR_USBCTR_PCIAHB_WIN1_256M    (0 << 10)
  86 #define RCAR_USBCTR_PCIAHB_WIN1_512M    (1 << 10)
  87 #define RCAR_USBCTR_PCIAHB_WIN1_1G      (2 << 10)
  88 #define RCAR_USBCTR_PCIAHB_WIN1_2G      (3 << 10)
  89 #define RCAR_USBCTR_PCIAHB_WIN1_MASK    (3 << 10)
  90
  91 #define RCAR_PCI_ARBITER_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  92 #define RCAR_PCI_ARBITER_PCIREQ0        (1 << 0)
  93 #define RCAR_PCI_ARBITER_PCIREQ1        (1 << 1)
  94 #define RCAR_PCI_ARBITER_PCIBP_MODE     (1 << 12)
  95
  96 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  97
  98 struct rcar_pci_priv {
  99         struct device *dev;
 100         void __iomem *reg;
 101         struct resource mem_res;
 102         struct resource *cfg_res;
 103         unsigned busnr;
 104         int irq;
 105         unsigned long window_size;
 106         unsigned long window_addr;
 107         unsigned long window_pci;
 108 };
 109
 110 /* PCI configuration space operations */
 111 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
 112                                        int where)
 113 {
 114         struct pci_sys_data *sys = bus->sysdata;
 115         struct rcar_pci_priv *priv = sys->private_data;
 116         int slot, val;
 117
 118         if (sys->busnr != bus->number || PCI_FUNC(devfn))
 119                 return NULL;
 120
 121         /* Only one EHCI/OHCI device built-in */
 122         slot = PCI_SLOT(devfn);
 123         if (slot > 2)
 124                 return NULL;
 125
 126         /* bridge logic only has registers to 0x40 */
 127         if (slot == 0x0 && where >= 0x40)
 128                 return NULL;
 129
 130         val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
 131                      RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
 132
 133         iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
 134         return priv->reg + (slot >> 1) * 0x100 + where;
 135 }
 136
 137 /* PCI interrupt mapping */
 138 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 139 {
 140         struct pci_sys_data *sys = dev->bus->sysdata;
 141         struct rcar_pci_priv *priv = sys->private_data;
 142         int irq;
 143
 144         irq = of_irq_parse_and_map_pci(dev, slot, pin);
 145         if (!irq)
 146                 irq = priv->irq;
 147
 148         return irq;
 149 }
 150
 151 #ifdef CONFIG_PCI_DEBUG
 152 /* if debug enabled, then attach an error handler irq to the bridge */
 153
 154 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
 155 {
 156         struct rcar_pci_priv *priv = pw;
 157         u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
 158
 159         if (status & RCAR_PCI_INT_ALLERRORS) {
 160                 dev_err(priv->dev, "error irq: status %08x\n", status);
 161
 162                 /* clear the error(s) */
 163                 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
 164                           priv->reg + RCAR_PCI_INT_STATUS_REG);
 165                 return IRQ_HANDLED;
 166         }
 167
 168         return IRQ_NONE;
 169 }
 170
 171 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
 172 {
 173         int ret;
 174         u32 val;
 175
 176         ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
 177                                IRQF_SHARED, "error irq", priv);
 178         if (ret) {
 179                 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
 180                 return;
 181         }
 182
 183         val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
 184         val |= RCAR_PCI_INT_ALLERRORS;
 185         iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
 186 }
 187 #else
 188 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
 189 #endif
 190
 191 /* PCI host controller setup */
 192 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
 193 {
 194         struct rcar_pci_priv *priv = sys->private_data;
 195         void __iomem *reg = priv->reg;
 196         u32 val;
 197         int ret;
 198
 199         pm_runtime_enable(priv->dev);
 200         pm_runtime_get_sync(priv->dev);
 201
 202         val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
 203         dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
 204
 205         /* Disable Direct Power Down State and assert reset */
 206         val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
 207         val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
 208         iowrite32(val, reg + RCAR_USBCTR_REG);
 209         udelay(4);
 210
 211         /* De-assert reset and reset PCIAHB window1 size */
 212         val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
 213                  RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
 214
 215         /* Setup PCIAHB window1 size */
 216         switch (priv->window_size) {
 217         case SZ_2G:
 218                 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
 219                 break;
 220         case SZ_1G:
 221                 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
 222                 break;
 223         case SZ_512M:
 224                 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
 225                 break;
 226         default:
 227                 pr_warn("unknown window size %ld - defaulting to 256M\n",
 228                         priv->window_size);
 229                 priv->window_size = SZ_256M;
 230                 /* fall-through */
 231         case SZ_256M:
 232                 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
 233                 break;
 234         }
 235         iowrite32(val, reg + RCAR_USBCTR_REG);
 236
 237         /* Configure AHB master and slave modes */
 238         iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
 239
 240         /* Configure PCI arbiter */
 241         val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
 242         val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
 243                RCAR_PCI_ARBITER_PCIBP_MODE;
 244         iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
 245
 246         /* PCI-AHB mapping */
 247         iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
 248                   reg + RCAR_PCIAHB_WIN1_CTR_REG);
 249
 250         /* AHB-PCI mapping: OHCI/EHCI registers */
 251         val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
 252         iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
 253
 254         /* Enable AHB-PCI bridge PCI configuration access */
 255         iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
 256                   reg + RCAR_AHBPCI_WIN1_CTR_REG);
 257         /* Set PCI-AHB Window1 address */
 258         iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
 259                   reg + PCI_BASE_ADDRESS_1);
 260         /* Set AHB-PCI bridge PCI communication area address */
 261         val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
 262         iowrite32(val, reg + PCI_BASE_ADDRESS_0);
 263
 264         val = ioread32(reg + PCI_COMMAND);
 265         val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 266                PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 267         iowrite32(val, reg + PCI_COMMAND);
 268
 269         /* Enable PCI interrupts */
 270         iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
 271                   reg + RCAR_PCI_INT_ENABLE_REG);
 272
 273         if (priv->irq > 0)
 274                 rcar_pci_setup_errirq(priv);
 275
 276         /* Add PCI resources */
 277         pci_add_resource(&sys->resources, &priv->mem_res);
 278         ret = devm_request_pci_bus_resources(priv->dev, &sys->resources);
 279         if (ret < 0)
 280                 return ret;
 281
 282         /* Setup bus number based on platform device id / of bus-range */
 283         sys->busnr = priv->busnr;
 284         return 1;
 285 }
 286
 287 static struct pci_ops rcar_pci_ops = {
 288         .map_bus = rcar_pci_cfg_base,
 289         .read   = pci_generic_config_read,
 290         .write  = pci_generic_config_write,
 291 };
 292
 293 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
 294                                      struct device_node *node)
 295 {
 296         const int na = 3, ns = 2;
 297         int rlen;
 298
 299         parser->node = node;
 300         parser->pna = of_n_addr_cells(node);
 301         parser->np = parser->pna + na + ns;
 302
 303         parser->range = of_get_property(node, "dma-ranges", &rlen);
 304         if (!parser->range)
 305                 return -ENOENT;
 306
 307         parser->end = parser->range + rlen / sizeof(__be32);
 308         return 0;
 309 }
 310
 311 static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
 312                                          struct device_node *np)
 313 {
 314         struct of_pci_range range;
 315         struct of_pci_range_parser parser;
 316         int index = 0;
 317
 318         /* Failure to parse is ok as we fall back to defaults */
 319         if (pci_dma_range_parser_init(&parser, np))
 320                 return 0;
 321
 322         /* Get the dma-ranges from DT */
 323         for_each_of_pci_range(&parser, &range) {
 324                 /* Hardware only allows one inbound 32-bit range */
 325                 if (index)
 326                         return -EINVAL;
 327
 328                 pci->window_addr = (unsigned long)range.cpu_addr;
 329                 pci->window_pci = (unsigned long)range.pci_addr;
 330                 pci->window_size = (unsigned long)range.size;
 331
 332                 /* Catch HW limitations */
 333                 if (!(range.flags & IORESOURCE_PREFETCH)) {
 334                         dev_err(pci->dev, "window must be prefetchable\n");
 335                         return -EINVAL;
 336                 }
 337                 if (pci->window_addr) {
 338                         u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
 339
 340                         if (lowaddr < pci->window_size) {
 341                                 dev_err(pci->dev, "invalid window size/addr\n");
 342                                 return -EINVAL;
 343                         }
 344                 }
 345                 index++;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int rcar_pci_probe(struct platform_device *pdev)
 352 {
 353         struct resource *cfg_res, *mem_res;
 354         struct rcar_pci_priv *priv;
 355         void __iomem *reg;
 356         struct hw_pci hw;
 357         void *hw_private[1];
 358
 359         cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         reg = devm_ioremap_resource(&pdev->dev, cfg_res);
 361         if (IS_ERR(reg))
 362                 return PTR_ERR(reg);
 363
 364         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 365         if (!mem_res || !mem_res->start)
 366                 return -ENODEV;
 367
 368         if (mem_res->start & 0xFFFF)
 369                 return -EINVAL;
 370
 371         priv = devm_kzalloc(&pdev->dev,
 372                             sizeof(struct rcar_pci_priv), GFP_KERNEL);
 373         if (!priv)
 374                 return -ENOMEM;
 375
 376         priv->mem_res = *mem_res;
 377         priv->cfg_res = cfg_res;
 378
 379         priv->irq = platform_get_irq(pdev, 0);
 380         priv->reg = reg;
 381         priv->dev = &pdev->dev;
 382
 383         if (priv->irq < 0) {
 384                 dev_err(&pdev->dev, "no valid irq found\n");
 385                 return priv->irq;
 386         }
 387
 388         /* default window addr and size if not specified in DT */
 389         priv->window_addr = 0x40000000;
 390         priv->window_pci = 0x40000000;
 391         priv->window_size = SZ_1G;
 392
 393         if (pdev->dev.of_node) {
 394                 struct resource busnr;
 395                 int ret;
 396
 397                 ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
 398                 if (ret < 0) {
 399                         dev_err(&pdev->dev, "failed to parse bus-range\n");
 400                         return ret;
 401                 }
 402
 403                 priv->busnr = busnr.start;
 404                 if (busnr.end != busnr.start)
 405                         dev_warn(&pdev->dev, "only one bus number supported\n");
 406
 407                 ret = rcar_pci_parse_map_dma_ranges(priv, pdev->dev.of_node);
 408                 if (ret < 0) {
 409                         dev_err(&pdev->dev, "failed to parse dma-range\n");
 410                         return ret;
 411                 }
 412         } else {
 413                 priv->busnr = pdev->id;
 414         }
 415
 416         hw_private[0] = priv;
 417         memset(&hw, 0, sizeof(hw));
 418         hw.nr_controllers = ARRAY_SIZE(hw_private);
 419         hw.io_optional = 1;
 420         hw.private_data = hw_private;
 421         hw.map_irq = rcar_pci_map_irq;
 422         hw.ops = &rcar_pci_ops;
 423         hw.setup = rcar_pci_setup;
 424         pci_common_init_dev(&pdev->dev, &hw);
 425         return 0;
 426 }
 427
 428 static struct of_device_id rcar_pci_of_match[] = {
 429         { .compatible = "renesas,pci-rcar-gen2", },
 430         { .compatible = "renesas,pci-r8a7790", },
 431         { .compatible = "renesas,pci-r8a7791", },
 432         { .compatible = "renesas,pci-r8a7794", },
 433         { },
 434 };
 435
 436 static struct platform_driver rcar_pci_driver = {
 437         .driver = {
 438                 .name = "pci-rcar-gen2",
 439                 .suppress_bind_attrs = true,
 440                 .of_match_table = rcar_pci_of_match,
 441         },
 442         .probe = rcar_pci_probe,
 443 };
 444 builtin_platform_driver(rcar_pci_driver);