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PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs
[deliverable/linux.git] / drivers / pci / host / pci-tegra.c
1 /*
2 * PCIe host controller driver for Tegra SoCs
3 *
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 *
10 * Bits taken from arch/arm/mach-dove/pcie.c
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 */
26
27 #include <linux/clk.h>
28 #include <linux/debugfs.h>
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/irqdomain.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/msi.h>
37 #include <linux/of_address.h>
38 #include <linux/of_pci.h>
39 #include <linux/of_platform.h>
40 #include <linux/pci.h>
41 #include <linux/phy/phy.h>
42 #include <linux/platform_device.h>
43 #include <linux/reset.h>
44 #include <linux/sizes.h>
45 #include <linux/slab.h>
46 #include <linux/vmalloc.h>
47 #include <linux/regulator/consumer.h>
48
49 #include <soc/tegra/cpuidle.h>
50 #include <soc/tegra/pmc.h>
51
52 #include <asm/mach/irq.h>
53 #include <asm/mach/map.h>
54 #include <asm/mach/pci.h>
55
56 #define INT_PCI_MSI_NR (8 * 32)
57
58 /* register definitions */
59
60 #define AFI_AXI_BAR0_SZ 0x00
61 #define AFI_AXI_BAR1_SZ 0x04
62 #define AFI_AXI_BAR2_SZ 0x08
63 #define AFI_AXI_BAR3_SZ 0x0c
64 #define AFI_AXI_BAR4_SZ 0x10
65 #define AFI_AXI_BAR5_SZ 0x14
66
67 #define AFI_AXI_BAR0_START 0x18
68 #define AFI_AXI_BAR1_START 0x1c
69 #define AFI_AXI_BAR2_START 0x20
70 #define AFI_AXI_BAR3_START 0x24
71 #define AFI_AXI_BAR4_START 0x28
72 #define AFI_AXI_BAR5_START 0x2c
73
74 #define AFI_FPCI_BAR0 0x30
75 #define AFI_FPCI_BAR1 0x34
76 #define AFI_FPCI_BAR2 0x38
77 #define AFI_FPCI_BAR3 0x3c
78 #define AFI_FPCI_BAR4 0x40
79 #define AFI_FPCI_BAR5 0x44
80
81 #define AFI_CACHE_BAR0_SZ 0x48
82 #define AFI_CACHE_BAR0_ST 0x4c
83 #define AFI_CACHE_BAR1_SZ 0x50
84 #define AFI_CACHE_BAR1_ST 0x54
85
86 #define AFI_MSI_BAR_SZ 0x60
87 #define AFI_MSI_FPCI_BAR_ST 0x64
88 #define AFI_MSI_AXI_BAR_ST 0x68
89
90 #define AFI_MSI_VEC0 0x6c
91 #define AFI_MSI_VEC1 0x70
92 #define AFI_MSI_VEC2 0x74
93 #define AFI_MSI_VEC3 0x78
94 #define AFI_MSI_VEC4 0x7c
95 #define AFI_MSI_VEC5 0x80
96 #define AFI_MSI_VEC6 0x84
97 #define AFI_MSI_VEC7 0x88
98
99 #define AFI_MSI_EN_VEC0 0x8c
100 #define AFI_MSI_EN_VEC1 0x90
101 #define AFI_MSI_EN_VEC2 0x94
102 #define AFI_MSI_EN_VEC3 0x98
103 #define AFI_MSI_EN_VEC4 0x9c
104 #define AFI_MSI_EN_VEC5 0xa0
105 #define AFI_MSI_EN_VEC6 0xa4
106 #define AFI_MSI_EN_VEC7 0xa8
107
108 #define AFI_CONFIGURATION 0xac
109 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
110
111 #define AFI_FPCI_ERROR_MASKS 0xb0
112
113 #define AFI_INTR_MASK 0xb4
114 #define AFI_INTR_MASK_INT_MASK (1 << 0)
115 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
116
117 #define AFI_INTR_CODE 0xb8
118 #define AFI_INTR_CODE_MASK 0xf
119 #define AFI_INTR_INI_SLAVE_ERROR 1
120 #define AFI_INTR_INI_DECODE_ERROR 2
121 #define AFI_INTR_TARGET_ABORT 3
122 #define AFI_INTR_MASTER_ABORT 4
123 #define AFI_INTR_INVALID_WRITE 5
124 #define AFI_INTR_LEGACY 6
125 #define AFI_INTR_FPCI_DECODE_ERROR 7
126 #define AFI_INTR_AXI_DECODE_ERROR 8
127 #define AFI_INTR_FPCI_TIMEOUT 9
128 #define AFI_INTR_PE_PRSNT_SENSE 10
129 #define AFI_INTR_PE_CLKREQ_SENSE 11
130 #define AFI_INTR_CLKCLAMP_SENSE 12
131 #define AFI_INTR_RDY4PD_SENSE 13
132 #define AFI_INTR_P2P_ERROR 14
133
134 #define AFI_INTR_SIGNATURE 0xbc
135 #define AFI_UPPER_FPCI_ADDRESS 0xc0
136 #define AFI_SM_INTR_ENABLE 0xc4
137 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
138 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
139 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
140 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
141 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
142 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
143 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
144 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
145
146 #define AFI_AFI_INTR_ENABLE 0xc8
147 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
148 #define AFI_INTR_EN_INI_DECERR (1 << 1)
149 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
150 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
151 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
152 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
153 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
154 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
155 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
156
157 #define AFI_PCIE_CONFIG 0x0f8
158 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
159 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
160 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
161 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
162 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
163 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
164 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
165 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
166 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
167 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
168
169 #define AFI_FUSE 0x104
170 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
171
172 #define AFI_PEX0_CTRL 0x110
173 #define AFI_PEX1_CTRL 0x118
174 #define AFI_PEX2_CTRL 0x128
175 #define AFI_PEX_CTRL_RST (1 << 0)
176 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
177 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
178 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
179
180 #define AFI_PLLE_CONTROL 0x160
181 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
182 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
183
184 #define AFI_PEXBIAS_CTRL_0 0x168
185
186 #define RP_VEND_XP 0x00000f00
187 #define RP_VEND_XP_DL_UP (1 << 30)
188
189 #define RP_PRIV_MISC 0x00000fe0
190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
192
193 #define RP_LINK_CONTROL_STATUS 0x00000090
194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
196
197 #define PADS_CTL_SEL 0x0000009c
198
199 #define PADS_CTL 0x000000a0
200 #define PADS_CTL_IDDQ_1L (1 << 0)
201 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
202 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
203
204 #define PADS_PLL_CTL_TEGRA20 0x000000b8
205 #define PADS_PLL_CTL_TEGRA30 0x000000b4
206 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
207 #define PADS_PLL_CTL_LOCKDET (1 << 8)
208 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
209 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
210 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
211 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
212 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
213 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
214 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
215 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
216
217 #define PADS_REFCLK_CFG0 0x000000c8
218 #define PADS_REFCLK_CFG1 0x000000cc
219 #define PADS_REFCLK_BIAS 0x000000d0
220
221 /*
222 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
223 * entries, one entry per PCIe port. These field definitions and desired
224 * values aren't in the TRM, but do come from NVIDIA.
225 */
226 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
227 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
228 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
229 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
230
231 /* Default value provided by HW engineering is 0xfa5c */
232 #define PADS_REFCLK_CFG_VALUE \
233 ( \
234 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
235 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
236 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
237 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
238 )
239
240 struct tegra_msi {
241 struct msi_controller chip;
242 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
243 struct irq_domain *domain;
244 unsigned long pages;
245 struct mutex lock;
246 int irq;
247 };
248
249 /* used to differentiate between Tegra SoC generations */
250 struct tegra_pcie_soc_data {
251 unsigned int num_ports;
252 unsigned int msi_base_shift;
253 u32 pads_pll_ctl;
254 u32 tx_ref_sel;
255 bool has_pex_clkreq_en;
256 bool has_pex_bias_ctrl;
257 bool has_intr_prsnt_sense;
258 bool has_cml_clk;
259 bool has_gen2;
260 };
261
262 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
263 {
264 return container_of(chip, struct tegra_msi, chip);
265 }
266
267 struct tegra_pcie {
268 struct device *dev;
269
270 void __iomem *pads;
271 void __iomem *afi;
272 int irq;
273
274 struct list_head buses;
275 struct resource *cs;
276
277 struct resource all;
278 struct resource io;
279 struct resource pio;
280 struct resource mem;
281 struct resource prefetch;
282 struct resource busn;
283
284 struct {
285 resource_size_t mem;
286 resource_size_t io;
287 } offset;
288
289 struct clk *pex_clk;
290 struct clk *afi_clk;
291 struct clk *pll_e;
292 struct clk *cml_clk;
293
294 struct reset_control *pex_rst;
295 struct reset_control *afi_rst;
296 struct reset_control *pcie_xrst;
297
298 bool legacy_phy;
299 struct phy *phy;
300
301 struct tegra_msi msi;
302
303 struct list_head ports;
304 u32 xbar_config;
305
306 struct regulator_bulk_data *supplies;
307 unsigned int num_supplies;
308
309 const struct tegra_pcie_soc_data *soc_data;
310 struct dentry *debugfs;
311 };
312
313 struct tegra_pcie_port {
314 struct tegra_pcie *pcie;
315 struct device_node *np;
316 struct list_head list;
317 struct resource regs;
318 void __iomem *base;
319 unsigned int index;
320 unsigned int lanes;
321
322 struct phy **phys;
323 };
324
325 struct tegra_pcie_bus {
326 struct vm_struct *area;
327 struct list_head list;
328 unsigned int nr;
329 };
330
331 static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
332 {
333 return sys->private_data;
334 }
335
336 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
337 unsigned long offset)
338 {
339 writel(value, pcie->afi + offset);
340 }
341
342 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
343 {
344 return readl(pcie->afi + offset);
345 }
346
347 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
348 unsigned long offset)
349 {
350 writel(value, pcie->pads + offset);
351 }
352
353 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
354 {
355 return readl(pcie->pads + offset);
356 }
357
358 /*
359 * The configuration space mapping on Tegra is somewhat similar to the ECAM
360 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
361 * register accesses are mapped:
362 *
363 * [27:24] extended register number
364 * [23:16] bus number
365 * [15:11] device number
366 * [10: 8] function number
367 * [ 7: 0] register number
368 *
369 * Mapping the whole extended configuration space would require 256 MiB of
370 * virtual address space, only a small part of which will actually be used.
371 * To work around this, a 1 MiB of virtual addresses are allocated per bus
372 * when the bus is first accessed. When the physical range is mapped, the
373 * the bus number bits are hidden so that the extended register number bits
374 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
375 *
376 * [19:16] extended register number
377 * [15:11] device number
378 * [10: 8] function number
379 * [ 7: 0] register number
380 *
381 * This is achieved by stitching together 16 chunks of 64 KiB of physical
382 * address space via the MMU.
383 */
384 static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
385 {
386 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
387 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
388 }
389
390 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
391 unsigned int busnr)
392 {
393 pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
394 L_PTE_XN | L_PTE_MT_DEV_SHARED | L_PTE_SHARED);
395 phys_addr_t cs = pcie->cs->start;
396 struct tegra_pcie_bus *bus;
397 unsigned int i;
398 int err;
399
400 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
401 if (!bus)
402 return ERR_PTR(-ENOMEM);
403
404 INIT_LIST_HEAD(&bus->list);
405 bus->nr = busnr;
406
407 /* allocate 1 MiB of virtual addresses */
408 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
409 if (!bus->area) {
410 err = -ENOMEM;
411 goto free;
412 }
413
414 /* map each of the 16 chunks of 64 KiB each */
415 for (i = 0; i < 16; i++) {
416 unsigned long virt = (unsigned long)bus->area->addr +
417 i * SZ_64K;
418 phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
419
420 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
421 if (err < 0) {
422 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
423 err);
424 goto unmap;
425 }
426 }
427
428 return bus;
429
430 unmap:
431 vunmap(bus->area->addr);
432 free:
433 kfree(bus);
434 return ERR_PTR(err);
435 }
436
437 static int tegra_pcie_add_bus(struct pci_bus *bus)
438 {
439 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
440 struct tegra_pcie_bus *b;
441
442 b = tegra_pcie_bus_alloc(pcie, bus->number);
443 if (IS_ERR(b))
444 return PTR_ERR(b);
445
446 list_add_tail(&b->list, &pcie->buses);
447
448 return 0;
449 }
450
451 static void tegra_pcie_remove_bus(struct pci_bus *child)
452 {
453 struct tegra_pcie *pcie = sys_to_pcie(child->sysdata);
454 struct tegra_pcie_bus *bus, *tmp;
455
456 list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
457 if (bus->nr == child->number) {
458 vunmap(bus->area->addr);
459 list_del(&bus->list);
460 kfree(bus);
461 break;
462 }
463 }
464 }
465
466 static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
467 unsigned int devfn,
468 int where)
469 {
470 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
471 void __iomem *addr = NULL;
472
473 if (bus->number == 0) {
474 unsigned int slot = PCI_SLOT(devfn);
475 struct tegra_pcie_port *port;
476
477 list_for_each_entry(port, &pcie->ports, list) {
478 if (port->index + 1 == slot) {
479 addr = port->base + (where & ~3);
480 break;
481 }
482 }
483 } else {
484 struct tegra_pcie_bus *b;
485
486 list_for_each_entry(b, &pcie->buses, list)
487 if (b->nr == bus->number)
488 addr = (void __iomem *)b->area->addr;
489
490 if (!addr) {
491 dev_err(pcie->dev,
492 "failed to map cfg. space for bus %u\n",
493 bus->number);
494 return NULL;
495 }
496
497 addr += tegra_pcie_conf_offset(devfn, where);
498 }
499
500 return addr;
501 }
502
503 static struct pci_ops tegra_pcie_ops = {
504 .add_bus = tegra_pcie_add_bus,
505 .remove_bus = tegra_pcie_remove_bus,
506 .map_bus = tegra_pcie_map_bus,
507 .read = pci_generic_config_read32,
508 .write = pci_generic_config_write32,
509 };
510
511 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
512 {
513 unsigned long ret = 0;
514
515 switch (port->index) {
516 case 0:
517 ret = AFI_PEX0_CTRL;
518 break;
519
520 case 1:
521 ret = AFI_PEX1_CTRL;
522 break;
523
524 case 2:
525 ret = AFI_PEX2_CTRL;
526 break;
527 }
528
529 return ret;
530 }
531
532 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
533 {
534 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
535 unsigned long value;
536
537 /* pulse reset signal */
538 value = afi_readl(port->pcie, ctrl);
539 value &= ~AFI_PEX_CTRL_RST;
540 afi_writel(port->pcie, value, ctrl);
541
542 usleep_range(1000, 2000);
543
544 value = afi_readl(port->pcie, ctrl);
545 value |= AFI_PEX_CTRL_RST;
546 afi_writel(port->pcie, value, ctrl);
547 }
548
549 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
550 {
551 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
552 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
553 unsigned long value;
554
555 /* enable reference clock */
556 value = afi_readl(port->pcie, ctrl);
557 value |= AFI_PEX_CTRL_REFCLK_EN;
558
559 if (soc->has_pex_clkreq_en)
560 value |= AFI_PEX_CTRL_CLKREQ_EN;
561
562 value |= AFI_PEX_CTRL_OVERRIDE_EN;
563
564 afi_writel(port->pcie, value, ctrl);
565
566 tegra_pcie_port_reset(port);
567 }
568
569 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
570 {
571 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
572 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
573 unsigned long value;
574
575 /* assert port reset */
576 value = afi_readl(port->pcie, ctrl);
577 value &= ~AFI_PEX_CTRL_RST;
578 afi_writel(port->pcie, value, ctrl);
579
580 /* disable reference clock */
581 value = afi_readl(port->pcie, ctrl);
582
583 if (soc->has_pex_clkreq_en)
584 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
585
586 value &= ~AFI_PEX_CTRL_REFCLK_EN;
587 afi_writel(port->pcie, value, ctrl);
588 }
589
590 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
591 {
592 struct tegra_pcie *pcie = port->pcie;
593
594 devm_iounmap(pcie->dev, port->base);
595 devm_release_mem_region(pcie->dev, port->regs.start,
596 resource_size(&port->regs));
597 list_del(&port->list);
598 devm_kfree(pcie->dev, port);
599 }
600
601 /* Tegra PCIE root complex wrongly reports device class */
602 static void tegra_pcie_fixup_class(struct pci_dev *dev)
603 {
604 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
605 }
606 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
610
611 /* Tegra PCIE requires relaxed ordering */
612 static void tegra_pcie_relax_enable(struct pci_dev *dev)
613 {
614 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
615 }
616 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
617
618 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
619 {
620 struct tegra_pcie *pcie = sys_to_pcie(sys);
621 int err;
622
623 sys->mem_offset = pcie->offset.mem;
624 sys->io_offset = pcie->offset.io;
625
626 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->io);
627 if (err < 0)
628 return err;
629
630 err = devm_request_resource(pcie->dev, &ioport_resource, &pcie->pio);
631 if (err < 0)
632 return err;
633
634 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem);
635 if (err < 0)
636 return err;
637
638 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch);
639 if (err)
640 return err;
641
642 pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);
643 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
644 pci_add_resource_offset(&sys->resources, &pcie->prefetch,
645 sys->mem_offset);
646 pci_add_resource(&sys->resources, &pcie->busn);
647
648 pci_remap_iospace(&pcie->pio, pcie->io.start);
649
650 return 1;
651 }
652
653 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
654 {
655 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
656 int irq;
657
658 tegra_cpuidle_pcie_irqs_in_use();
659
660 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
661 if (!irq)
662 irq = pcie->irq;
663
664 return irq;
665 }
666
667 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
668 {
669 const char *err_msg[] = {
670 "Unknown",
671 "AXI slave error",
672 "AXI decode error",
673 "Target abort",
674 "Master abort",
675 "Invalid write",
676 "Legacy interrupt",
677 "Response decoding error",
678 "AXI response decoding error",
679 "Transaction timeout",
680 "Slot present pin change",
681 "Slot clock request change",
682 "TMS clock ramp change",
683 "TMS ready for power down",
684 "Peer2Peer error",
685 };
686 struct tegra_pcie *pcie = arg;
687 u32 code, signature;
688
689 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
690 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
691 afi_writel(pcie, 0, AFI_INTR_CODE);
692
693 if (code == AFI_INTR_LEGACY)
694 return IRQ_NONE;
695
696 if (code >= ARRAY_SIZE(err_msg))
697 code = 0;
698
699 /*
700 * do not pollute kernel log with master abort reports since they
701 * happen a lot during enumeration
702 */
703 if (code == AFI_INTR_MASTER_ABORT)
704 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
705 signature);
706 else
707 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
708 signature);
709
710 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
711 code == AFI_INTR_FPCI_DECODE_ERROR) {
712 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
713 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
714
715 if (code == AFI_INTR_MASTER_ABORT)
716 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address);
717 else
718 dev_err(pcie->dev, " FPCI address: %10llx\n", address);
719 }
720
721 return IRQ_HANDLED;
722 }
723
724 /*
725 * FPCI map is as follows:
726 * - 0xfdfc000000: I/O space
727 * - 0xfdfe000000: type 0 configuration space
728 * - 0xfdff000000: type 1 configuration space
729 * - 0xfe00000000: type 0 extended configuration space
730 * - 0xfe10000000: type 1 extended configuration space
731 */
732 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
733 {
734 u32 fpci_bar, size, axi_address;
735
736 /* Bar 0: type 1 extended configuration space */
737 fpci_bar = 0xfe100000;
738 size = resource_size(pcie->cs);
739 axi_address = pcie->cs->start;
740 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
741 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
742 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
743
744 /* Bar 1: downstream IO bar */
745 fpci_bar = 0xfdfc0000;
746 size = resource_size(&pcie->io);
747 axi_address = pcie->io.start;
748 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
749 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
750 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
751
752 /* Bar 2: prefetchable memory BAR */
753 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
754 size = resource_size(&pcie->prefetch);
755 axi_address = pcie->prefetch.start;
756 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
757 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
758 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
759
760 /* Bar 3: non prefetchable memory BAR */
761 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
762 size = resource_size(&pcie->mem);
763 axi_address = pcie->mem.start;
764 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
765 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
766 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
767
768 /* NULL out the remaining BARs as they are not used */
769 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
770 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
771 afi_writel(pcie, 0, AFI_FPCI_BAR4);
772
773 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
774 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
775 afi_writel(pcie, 0, AFI_FPCI_BAR5);
776
777 /* map all upstream transactions as uncached */
778 afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
779 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
780 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
781 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
782
783 /* MSI translations are setup only when needed */
784 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
785 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
786 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
787 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
788 }
789
790 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
791 {
792 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
793 u32 value;
794
795 timeout = jiffies + msecs_to_jiffies(timeout);
796
797 while (time_before(jiffies, timeout)) {
798 value = pads_readl(pcie, soc->pads_pll_ctl);
799 if (value & PADS_PLL_CTL_LOCKDET)
800 return 0;
801 }
802
803 return -ETIMEDOUT;
804 }
805
806 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
807 {
808 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
809 u32 value;
810 int err;
811
812 /* initialize internal PHY, enable up to 16 PCIE lanes */
813 pads_writel(pcie, 0x0, PADS_CTL_SEL);
814
815 /* override IDDQ to 1 on all 4 lanes */
816 value = pads_readl(pcie, PADS_CTL);
817 value |= PADS_CTL_IDDQ_1L;
818 pads_writel(pcie, value, PADS_CTL);
819
820 /*
821 * Set up PHY PLL inputs select PLLE output as refclock,
822 * set TX ref sel to div10 (not div5).
823 */
824 value = pads_readl(pcie, soc->pads_pll_ctl);
825 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
826 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
827 pads_writel(pcie, value, soc->pads_pll_ctl);
828
829 /* reset PLL */
830 value = pads_readl(pcie, soc->pads_pll_ctl);
831 value &= ~PADS_PLL_CTL_RST_B4SM;
832 pads_writel(pcie, value, soc->pads_pll_ctl);
833
834 usleep_range(20, 100);
835
836 /* take PLL out of reset */
837 value = pads_readl(pcie, soc->pads_pll_ctl);
838 value |= PADS_PLL_CTL_RST_B4SM;
839 pads_writel(pcie, value, soc->pads_pll_ctl);
840
841 /* wait for the PLL to lock */
842 err = tegra_pcie_pll_wait(pcie, 500);
843 if (err < 0) {
844 dev_err(pcie->dev, "PLL failed to lock: %d\n", err);
845 return err;
846 }
847
848 /* turn off IDDQ override */
849 value = pads_readl(pcie, PADS_CTL);
850 value &= ~PADS_CTL_IDDQ_1L;
851 pads_writel(pcie, value, PADS_CTL);
852
853 /* enable TX/RX data */
854 value = pads_readl(pcie, PADS_CTL);
855 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
856 pads_writel(pcie, value, PADS_CTL);
857
858 return 0;
859 }
860
861 static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
862 {
863 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
864 u32 value;
865
866 /* disable TX/RX data */
867 value = pads_readl(pcie, PADS_CTL);
868 value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
869 pads_writel(pcie, value, PADS_CTL);
870
871 /* override IDDQ */
872 value = pads_readl(pcie, PADS_CTL);
873 value |= PADS_CTL_IDDQ_1L;
874 pads_writel(pcie, PADS_CTL, value);
875
876 /* reset PLL */
877 value = pads_readl(pcie, soc->pads_pll_ctl);
878 value &= ~PADS_PLL_CTL_RST_B4SM;
879 pads_writel(pcie, value, soc->pads_pll_ctl);
880
881 usleep_range(20, 100);
882
883 return 0;
884 }
885
886 static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
887 {
888 struct device *dev = port->pcie->dev;
889 unsigned int i;
890 int err;
891
892 for (i = 0; i < port->lanes; i++) {
893 err = phy_power_on(port->phys[i]);
894 if (err < 0) {
895 dev_err(dev, "failed to power on PHY#%u: %d\n", i,
896 err);
897 return err;
898 }
899 }
900
901 return 0;
902 }
903
904 static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
905 {
906 struct device *dev = port->pcie->dev;
907 unsigned int i;
908 int err;
909
910 for (i = 0; i < port->lanes; i++) {
911 err = phy_power_off(port->phys[i]);
912 if (err < 0) {
913 dev_err(dev, "failed to power off PHY#%u: %d\n", i,
914 err);
915 return err;
916 }
917 }
918
919 return 0;
920 }
921
922 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
923 {
924 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
925 struct tegra_pcie_port *port;
926 u32 value;
927 int err;
928
929 if (pcie->legacy_phy) {
930 if (pcie->phy)
931 err = phy_power_on(pcie->phy);
932 else
933 err = tegra_pcie_phy_enable(pcie);
934
935 if (err < 0)
936 dev_err(pcie->dev, "failed to power on PHY: %d\n", err);
937
938 return err;
939 }
940
941 list_for_each_entry(port, &pcie->ports, list) {
942 err = tegra_pcie_port_phy_power_on(port);
943 if (err < 0) {
944 dev_err(pcie->dev,
945 "failed to power on PCIe port %u PHY: %d\n",
946 port->index, err);
947 return err;
948 }
949 }
950
951 /* Configure the reference clock driver */
952 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
953 pads_writel(pcie, value, PADS_REFCLK_CFG0);
954
955 if (soc->num_ports > 2)
956 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
957
958 return 0;
959 }
960
961 static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
962 {
963 struct tegra_pcie_port *port;
964 int err;
965
966 if (pcie->legacy_phy) {
967 if (pcie->phy)
968 err = phy_power_off(pcie->phy);
969 else
970 err = tegra_pcie_phy_disable(pcie);
971
972 if (err < 0)
973 dev_err(pcie->dev, "failed to power off PHY: %d\n",
974 err);
975
976 return err;
977 }
978
979 list_for_each_entry(port, &pcie->ports, list) {
980 err = tegra_pcie_port_phy_power_off(port);
981 if (err < 0) {
982 dev_err(pcie->dev,
983 "failed to power off PCIe port %u PHY: %d\n",
984 port->index, err);
985 return err;
986 }
987 }
988
989 return 0;
990 }
991
992 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
993 {
994 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
995 struct tegra_pcie_port *port;
996 unsigned long value;
997 int err;
998
999 /* enable PLL power down */
1000 if (pcie->phy) {
1001 value = afi_readl(pcie, AFI_PLLE_CONTROL);
1002 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
1003 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
1004 afi_writel(pcie, value, AFI_PLLE_CONTROL);
1005 }
1006
1007 /* power down PCIe slot clock bias pad */
1008 if (soc->has_pex_bias_ctrl)
1009 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
1010
1011 /* configure mode and disable all ports */
1012 value = afi_readl(pcie, AFI_PCIE_CONFIG);
1013 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
1014 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
1015
1016 list_for_each_entry(port, &pcie->ports, list)
1017 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
1018
1019 afi_writel(pcie, value, AFI_PCIE_CONFIG);
1020
1021 if (soc->has_gen2) {
1022 value = afi_readl(pcie, AFI_FUSE);
1023 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
1024 afi_writel(pcie, value, AFI_FUSE);
1025 } else {
1026 value = afi_readl(pcie, AFI_FUSE);
1027 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
1028 afi_writel(pcie, value, AFI_FUSE);
1029 }
1030
1031 err = tegra_pcie_phy_power_on(pcie);
1032 if (err < 0) {
1033 dev_err(pcie->dev, "failed to power on PHY(s): %d\n", err);
1034 return err;
1035 }
1036
1037 /* take the PCIe interface module out of reset */
1038 reset_control_deassert(pcie->pcie_xrst);
1039
1040 /* finally enable PCIe */
1041 value = afi_readl(pcie, AFI_CONFIGURATION);
1042 value |= AFI_CONFIGURATION_EN_FPCI;
1043 afi_writel(pcie, value, AFI_CONFIGURATION);
1044
1045 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
1046 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
1047 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
1048
1049 if (soc->has_intr_prsnt_sense)
1050 value |= AFI_INTR_EN_PRSNT_SENSE;
1051
1052 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
1053 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
1054
1055 /* don't enable MSI for now, only when needed */
1056 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
1057
1058 /* disable all exceptions */
1059 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
1060
1061 return 0;
1062 }
1063
1064 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
1065 {
1066 int err;
1067
1068 /* TODO: disable and unprepare clocks? */
1069
1070 err = tegra_pcie_phy_power_off(pcie);
1071 if (err < 0)
1072 dev_err(pcie->dev, "failed to power off PHY(s): %d\n", err);
1073
1074 reset_control_assert(pcie->pcie_xrst);
1075 reset_control_assert(pcie->afi_rst);
1076 reset_control_assert(pcie->pex_rst);
1077
1078 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1079
1080 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1081 if (err < 0)
1082 dev_warn(pcie->dev, "failed to disable regulators: %d\n", err);
1083 }
1084
1085 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
1086 {
1087 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1088 int err;
1089
1090 reset_control_assert(pcie->pcie_xrst);
1091 reset_control_assert(pcie->afi_rst);
1092 reset_control_assert(pcie->pex_rst);
1093
1094 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1095
1096 /* enable regulators */
1097 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
1098 if (err < 0)
1099 dev_err(pcie->dev, "failed to enable regulators: %d\n", err);
1100
1101 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
1102 pcie->pex_clk,
1103 pcie->pex_rst);
1104 if (err) {
1105 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
1106 return err;
1107 }
1108
1109 reset_control_deassert(pcie->afi_rst);
1110
1111 err = clk_prepare_enable(pcie->afi_clk);
1112 if (err < 0) {
1113 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
1114 return err;
1115 }
1116
1117 if (soc->has_cml_clk) {
1118 err = clk_prepare_enable(pcie->cml_clk);
1119 if (err < 0) {
1120 dev_err(pcie->dev, "failed to enable CML clock: %d\n",
1121 err);
1122 return err;
1123 }
1124 }
1125
1126 err = clk_prepare_enable(pcie->pll_e);
1127 if (err < 0) {
1128 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
1129 return err;
1130 }
1131
1132 return 0;
1133 }
1134
1135 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1136 {
1137 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1138
1139 pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
1140 if (IS_ERR(pcie->pex_clk))
1141 return PTR_ERR(pcie->pex_clk);
1142
1143 pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
1144 if (IS_ERR(pcie->afi_clk))
1145 return PTR_ERR(pcie->afi_clk);
1146
1147 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
1148 if (IS_ERR(pcie->pll_e))
1149 return PTR_ERR(pcie->pll_e);
1150
1151 if (soc->has_cml_clk) {
1152 pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
1153 if (IS_ERR(pcie->cml_clk))
1154 return PTR_ERR(pcie->cml_clk);
1155 }
1156
1157 return 0;
1158 }
1159
1160 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1161 {
1162 pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
1163 if (IS_ERR(pcie->pex_rst))
1164 return PTR_ERR(pcie->pex_rst);
1165
1166 pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
1167 if (IS_ERR(pcie->afi_rst))
1168 return PTR_ERR(pcie->afi_rst);
1169
1170 pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
1171 if (IS_ERR(pcie->pcie_xrst))
1172 return PTR_ERR(pcie->pcie_xrst);
1173
1174 return 0;
1175 }
1176
1177 static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
1178 {
1179 int err;
1180
1181 pcie->phy = devm_phy_optional_get(pcie->dev, "pcie");
1182 if (IS_ERR(pcie->phy)) {
1183 err = PTR_ERR(pcie->phy);
1184 dev_err(pcie->dev, "failed to get PHY: %d\n", err);
1185 return err;
1186 }
1187
1188 err = phy_init(pcie->phy);
1189 if (err < 0) {
1190 dev_err(pcie->dev, "failed to initialize PHY: %d\n", err);
1191 return err;
1192 }
1193
1194 pcie->legacy_phy = true;
1195
1196 return 0;
1197 }
1198
1199 static struct phy *devm_of_phy_optional_get_index(struct device *dev,
1200 struct device_node *np,
1201 const char *consumer,
1202 unsigned int index)
1203 {
1204 struct phy *phy;
1205 char *name;
1206
1207 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index);
1208 if (!name)
1209 return ERR_PTR(-ENOMEM);
1210
1211 phy = devm_of_phy_get(dev, np, name);
1212 kfree(name);
1213
1214 if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV)
1215 phy = NULL;
1216
1217 return phy;
1218 }
1219
1220 static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
1221 {
1222 struct device *dev = port->pcie->dev;
1223 struct phy *phy;
1224 unsigned int i;
1225 int err;
1226
1227 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1228 if (!port->phys)
1229 return -ENOMEM;
1230
1231 for (i = 0; i < port->lanes; i++) {
1232 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1233 if (IS_ERR(phy)) {
1234 dev_err(dev, "failed to get PHY#%u: %ld\n", i,
1235 PTR_ERR(phy));
1236 return PTR_ERR(phy);
1237 }
1238
1239 err = phy_init(phy);
1240 if (err < 0) {
1241 dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
1242 err);
1243 return err;
1244 }
1245
1246 port->phys[i] = phy;
1247 }
1248
1249 return 0;
1250 }
1251
1252 static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
1253 {
1254 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1255 struct device_node *np = pcie->dev->of_node;
1256 struct tegra_pcie_port *port;
1257 int err;
1258
1259 if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL)
1260 return tegra_pcie_phys_get_legacy(pcie);
1261
1262 list_for_each_entry(port, &pcie->ports, list) {
1263 err = tegra_pcie_port_get_phys(port);
1264 if (err < 0)
1265 return err;
1266 }
1267
1268 return 0;
1269 }
1270
1271 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1272 {
1273 struct platform_device *pdev = to_platform_device(pcie->dev);
1274 struct resource *pads, *afi, *res;
1275 int err;
1276
1277 err = tegra_pcie_clocks_get(pcie);
1278 if (err) {
1279 dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
1280 return err;
1281 }
1282
1283 err = tegra_pcie_resets_get(pcie);
1284 if (err) {
1285 dev_err(&pdev->dev, "failed to get resets: %d\n", err);
1286 return err;
1287 }
1288
1289 err = tegra_pcie_phys_get(pcie);
1290 if (err < 0) {
1291 dev_err(&pdev->dev, "failed to get PHYs: %d\n", err);
1292 return err;
1293 }
1294
1295 err = tegra_pcie_power_on(pcie);
1296 if (err) {
1297 dev_err(&pdev->dev, "failed to power up: %d\n", err);
1298 return err;
1299 }
1300
1301 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1302 pcie->pads = devm_ioremap_resource(&pdev->dev, pads);
1303 if (IS_ERR(pcie->pads)) {
1304 err = PTR_ERR(pcie->pads);
1305 goto poweroff;
1306 }
1307
1308 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1309 pcie->afi = devm_ioremap_resource(&pdev->dev, afi);
1310 if (IS_ERR(pcie->afi)) {
1311 err = PTR_ERR(pcie->afi);
1312 goto poweroff;
1313 }
1314
1315 /* request configuration space, but remap later, on demand */
1316 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1317 if (!res) {
1318 err = -EADDRNOTAVAIL;
1319 goto poweroff;
1320 }
1321
1322 pcie->cs = devm_request_mem_region(pcie->dev, res->start,
1323 resource_size(res), res->name);
1324 if (!pcie->cs) {
1325 err = -EADDRNOTAVAIL;
1326 goto poweroff;
1327 }
1328
1329 /* request interrupt */
1330 err = platform_get_irq_byname(pdev, "intr");
1331 if (err < 0) {
1332 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1333 goto poweroff;
1334 }
1335
1336 pcie->irq = err;
1337
1338 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1339 if (err) {
1340 dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
1341 goto poweroff;
1342 }
1343
1344 return 0;
1345
1346 poweroff:
1347 tegra_pcie_power_off(pcie);
1348 return err;
1349 }
1350
1351 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1352 {
1353 int err;
1354
1355 if (pcie->irq > 0)
1356 free_irq(pcie->irq, pcie);
1357
1358 tegra_pcie_power_off(pcie);
1359
1360 err = phy_exit(pcie->phy);
1361 if (err < 0)
1362 dev_err(pcie->dev, "failed to teardown PHY: %d\n", err);
1363
1364 return 0;
1365 }
1366
1367 static int tegra_msi_alloc(struct tegra_msi *chip)
1368 {
1369 int msi;
1370
1371 mutex_lock(&chip->lock);
1372
1373 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1374 if (msi < INT_PCI_MSI_NR)
1375 set_bit(msi, chip->used);
1376 else
1377 msi = -ENOSPC;
1378
1379 mutex_unlock(&chip->lock);
1380
1381 return msi;
1382 }
1383
1384 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1385 {
1386 struct device *dev = chip->chip.dev;
1387
1388 mutex_lock(&chip->lock);
1389
1390 if (!test_bit(irq, chip->used))
1391 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1392 else
1393 clear_bit(irq, chip->used);
1394
1395 mutex_unlock(&chip->lock);
1396 }
1397
1398 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1399 {
1400 struct tegra_pcie *pcie = data;
1401 struct tegra_msi *msi = &pcie->msi;
1402 unsigned int i, processed = 0;
1403
1404 for (i = 0; i < 8; i++) {
1405 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1406
1407 while (reg) {
1408 unsigned int offset = find_first_bit(&reg, 32);
1409 unsigned int index = i * 32 + offset;
1410 unsigned int irq;
1411
1412 /* clear the interrupt */
1413 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1414
1415 irq = irq_find_mapping(msi->domain, index);
1416 if (irq) {
1417 if (test_bit(index, msi->used))
1418 generic_handle_irq(irq);
1419 else
1420 dev_info(pcie->dev, "unhandled MSI\n");
1421 } else {
1422 /*
1423 * that's weird who triggered this?
1424 * just clear it
1425 */
1426 dev_info(pcie->dev, "unexpected MSI\n");
1427 }
1428
1429 /* see if there's any more pending in this vector */
1430 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1431
1432 processed++;
1433 }
1434 }
1435
1436 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1437 }
1438
1439 static int tegra_msi_setup_irq(struct msi_controller *chip,
1440 struct pci_dev *pdev, struct msi_desc *desc)
1441 {
1442 struct tegra_msi *msi = to_tegra_msi(chip);
1443 struct msi_msg msg;
1444 unsigned int irq;
1445 int hwirq;
1446
1447 hwirq = tegra_msi_alloc(msi);
1448 if (hwirq < 0)
1449 return hwirq;
1450
1451 irq = irq_create_mapping(msi->domain, hwirq);
1452 if (!irq) {
1453 tegra_msi_free(msi, hwirq);
1454 return -EINVAL;
1455 }
1456
1457 irq_set_msi_desc(irq, desc);
1458
1459 msg.address_lo = virt_to_phys((void *)msi->pages);
1460 /* 32 bit address only */
1461 msg.address_hi = 0;
1462 msg.data = hwirq;
1463
1464 pci_write_msi_msg(irq, &msg);
1465
1466 return 0;
1467 }
1468
1469 static void tegra_msi_teardown_irq(struct msi_controller *chip,
1470 unsigned int irq)
1471 {
1472 struct tegra_msi *msi = to_tegra_msi(chip);
1473 struct irq_data *d = irq_get_irq_data(irq);
1474 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1475
1476 irq_dispose_mapping(irq);
1477 tegra_msi_free(msi, hwirq);
1478 }
1479
1480 static struct irq_chip tegra_msi_irq_chip = {
1481 .name = "Tegra PCIe MSI",
1482 .irq_enable = pci_msi_unmask_irq,
1483 .irq_disable = pci_msi_mask_irq,
1484 .irq_mask = pci_msi_mask_irq,
1485 .irq_unmask = pci_msi_unmask_irq,
1486 };
1487
1488 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1489 irq_hw_number_t hwirq)
1490 {
1491 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1492 irq_set_chip_data(irq, domain->host_data);
1493
1494 tegra_cpuidle_pcie_irqs_in_use();
1495
1496 return 0;
1497 }
1498
1499 static const struct irq_domain_ops msi_domain_ops = {
1500 .map = tegra_msi_map,
1501 };
1502
1503 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1504 {
1505 struct platform_device *pdev = to_platform_device(pcie->dev);
1506 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1507 struct tegra_msi *msi = &pcie->msi;
1508 unsigned long base;
1509 int err;
1510 u32 reg;
1511
1512 mutex_init(&msi->lock);
1513
1514 msi->chip.dev = pcie->dev;
1515 msi->chip.setup_irq = tegra_msi_setup_irq;
1516 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1517
1518 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
1519 &msi_domain_ops, &msi->chip);
1520 if (!msi->domain) {
1521 dev_err(&pdev->dev, "failed to create IRQ domain\n");
1522 return -ENOMEM;
1523 }
1524
1525 err = platform_get_irq_byname(pdev, "msi");
1526 if (err < 0) {
1527 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1528 goto err;
1529 }
1530
1531 msi->irq = err;
1532
1533 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
1534 tegra_msi_irq_chip.name, pcie);
1535 if (err < 0) {
1536 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1537 goto err;
1538 }
1539
1540 /* setup AFI/FPCI range */
1541 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1542 base = virt_to_phys((void *)msi->pages);
1543
1544 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1545 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1546 /* this register is in 4K increments */
1547 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1548
1549 /* enable all MSI vectors */
1550 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1551 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1552 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1553 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1554 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1555 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1556 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1557 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1558
1559 /* and unmask the MSI interrupt */
1560 reg = afi_readl(pcie, AFI_INTR_MASK);
1561 reg |= AFI_INTR_MASK_MSI_MASK;
1562 afi_writel(pcie, reg, AFI_INTR_MASK);
1563
1564 return 0;
1565
1566 err:
1567 irq_domain_remove(msi->domain);
1568 return err;
1569 }
1570
1571 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1572 {
1573 struct tegra_msi *msi = &pcie->msi;
1574 unsigned int i, irq;
1575 u32 value;
1576
1577 /* mask the MSI interrupt */
1578 value = afi_readl(pcie, AFI_INTR_MASK);
1579 value &= ~AFI_INTR_MASK_MSI_MASK;
1580 afi_writel(pcie, value, AFI_INTR_MASK);
1581
1582 /* disable all MSI vectors */
1583 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1584 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1585 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1586 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1587 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1588 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1589 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1590 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1591
1592 free_pages(msi->pages, 0);
1593
1594 if (msi->irq > 0)
1595 free_irq(msi->irq, pcie);
1596
1597 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1598 irq = irq_find_mapping(msi->domain, i);
1599 if (irq > 0)
1600 irq_dispose_mapping(irq);
1601 }
1602
1603 irq_domain_remove(msi->domain);
1604
1605 return 0;
1606 }
1607
1608 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1609 u32 *xbar)
1610 {
1611 struct device_node *np = pcie->dev->of_node;
1612
1613 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1614 switch (lanes) {
1615 case 0x0000104:
1616 dev_info(pcie->dev, "4x1, 1x1 configuration\n");
1617 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
1618 return 0;
1619
1620 case 0x0000102:
1621 dev_info(pcie->dev, "2x1, 1x1 configuration\n");
1622 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
1623 return 0;
1624 }
1625 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1626 switch (lanes) {
1627 case 0x00000204:
1628 dev_info(pcie->dev, "4x1, 2x1 configuration\n");
1629 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1630 return 0;
1631
1632 case 0x00020202:
1633 dev_info(pcie->dev, "2x3 configuration\n");
1634 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1635 return 0;
1636
1637 case 0x00010104:
1638 dev_info(pcie->dev, "4x1, 1x2 configuration\n");
1639 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1640 return 0;
1641 }
1642 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1643 switch (lanes) {
1644 case 0x00000004:
1645 dev_info(pcie->dev, "single-mode configuration\n");
1646 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1647 return 0;
1648
1649 case 0x00000202:
1650 dev_info(pcie->dev, "dual-mode configuration\n");
1651 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1652 return 0;
1653 }
1654 }
1655
1656 return -EINVAL;
1657 }
1658
1659 /*
1660 * Check whether a given set of supplies is available in a device tree node.
1661 * This is used to check whether the new or the legacy device tree bindings
1662 * should be used.
1663 */
1664 static bool of_regulator_bulk_available(struct device_node *np,
1665 struct regulator_bulk_data *supplies,
1666 unsigned int num_supplies)
1667 {
1668 char property[32];
1669 unsigned int i;
1670
1671 for (i = 0; i < num_supplies; i++) {
1672 snprintf(property, 32, "%s-supply", supplies[i].supply);
1673
1674 if (of_find_property(np, property, NULL) == NULL)
1675 return false;
1676 }
1677
1678 return true;
1679 }
1680
1681 /*
1682 * Old versions of the device tree binding for this device used a set of power
1683 * supplies that didn't match the hardware inputs. This happened to work for a
1684 * number of cases but is not future proof. However to preserve backwards-
1685 * compatibility with old device trees, this function will try to use the old
1686 * set of supplies.
1687 */
1688 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1689 {
1690 struct device_node *np = pcie->dev->of_node;
1691
1692 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1693 pcie->num_supplies = 3;
1694 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1695 pcie->num_supplies = 2;
1696
1697 if (pcie->num_supplies == 0) {
1698 dev_err(pcie->dev, "device %s not supported in legacy mode\n",
1699 np->full_name);
1700 return -ENODEV;
1701 }
1702
1703 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1704 sizeof(*pcie->supplies),
1705 GFP_KERNEL);
1706 if (!pcie->supplies)
1707 return -ENOMEM;
1708
1709 pcie->supplies[0].supply = "pex-clk";
1710 pcie->supplies[1].supply = "vdd";
1711
1712 if (pcie->num_supplies > 2)
1713 pcie->supplies[2].supply = "avdd";
1714
1715 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1716 pcie->supplies);
1717 }
1718
1719 /*
1720 * Obtains the list of regulators required for a particular generation of the
1721 * IP block.
1722 *
1723 * This would've been nice to do simply by providing static tables for use
1724 * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
1725 * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
1726 * and either seems to be optional depending on which ports are being used.
1727 */
1728 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1729 {
1730 struct device_node *np = pcie->dev->of_node;
1731 unsigned int i = 0;
1732
1733 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1734 pcie->num_supplies = 7;
1735
1736 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1737 sizeof(*pcie->supplies),
1738 GFP_KERNEL);
1739 if (!pcie->supplies)
1740 return -ENOMEM;
1741
1742 pcie->supplies[i++].supply = "avddio-pex";
1743 pcie->supplies[i++].supply = "dvddio-pex";
1744 pcie->supplies[i++].supply = "avdd-pex-pll";
1745 pcie->supplies[i++].supply = "hvdd-pex";
1746 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1747 pcie->supplies[i++].supply = "vddio-pex-ctl";
1748 pcie->supplies[i++].supply = "avdd-pll-erefe";
1749 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1750 bool need_pexa = false, need_pexb = false;
1751
1752 /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
1753 if (lane_mask & 0x0f)
1754 need_pexa = true;
1755
1756 /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
1757 if (lane_mask & 0x30)
1758 need_pexb = true;
1759
1760 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
1761 (need_pexb ? 2 : 0);
1762
1763 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1764 sizeof(*pcie->supplies),
1765 GFP_KERNEL);
1766 if (!pcie->supplies)
1767 return -ENOMEM;
1768
1769 pcie->supplies[i++].supply = "avdd-pex-pll";
1770 pcie->supplies[i++].supply = "hvdd-pex";
1771 pcie->supplies[i++].supply = "vddio-pex-ctl";
1772 pcie->supplies[i++].supply = "avdd-plle";
1773
1774 if (need_pexa) {
1775 pcie->supplies[i++].supply = "avdd-pexa";
1776 pcie->supplies[i++].supply = "vdd-pexa";
1777 }
1778
1779 if (need_pexb) {
1780 pcie->supplies[i++].supply = "avdd-pexb";
1781 pcie->supplies[i++].supply = "vdd-pexb";
1782 }
1783 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1784 pcie->num_supplies = 5;
1785
1786 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1787 sizeof(*pcie->supplies),
1788 GFP_KERNEL);
1789 if (!pcie->supplies)
1790 return -ENOMEM;
1791
1792 pcie->supplies[0].supply = "avdd-pex";
1793 pcie->supplies[1].supply = "vdd-pex";
1794 pcie->supplies[2].supply = "avdd-pex-pll";
1795 pcie->supplies[3].supply = "avdd-plle";
1796 pcie->supplies[4].supply = "vddio-pex-clk";
1797 }
1798
1799 if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies,
1800 pcie->num_supplies))
1801 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1802 pcie->supplies);
1803
1804 /*
1805 * If not all regulators are available for this new scheme, assume
1806 * that the device tree complies with an older version of the device
1807 * tree binding.
1808 */
1809 dev_info(pcie->dev, "using legacy DT binding for power supplies\n");
1810
1811 devm_kfree(pcie->dev, pcie->supplies);
1812 pcie->num_supplies = 0;
1813
1814 return tegra_pcie_get_legacy_regulators(pcie);
1815 }
1816
1817 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1818 {
1819 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1820 struct device_node *np = pcie->dev->of_node, *port;
1821 struct of_pci_range_parser parser;
1822 struct of_pci_range range;
1823 u32 lanes = 0, mask = 0;
1824 unsigned int lane = 0;
1825 struct resource res;
1826 int err;
1827
1828 memset(&pcie->all, 0, sizeof(pcie->all));
1829 pcie->all.flags = IORESOURCE_MEM;
1830 pcie->all.name = np->full_name;
1831 pcie->all.start = ~0;
1832 pcie->all.end = 0;
1833
1834 if (of_pci_range_parser_init(&parser, np)) {
1835 dev_err(pcie->dev, "missing \"ranges\" property\n");
1836 return -EINVAL;
1837 }
1838
1839 for_each_of_pci_range(&parser, &range) {
1840 err = of_pci_range_to_resource(&range, np, &res);
1841 if (err < 0)
1842 return err;
1843
1844 switch (res.flags & IORESOURCE_TYPE_BITS) {
1845 case IORESOURCE_IO:
1846 /* Track the bus -> CPU I/O mapping offset. */
1847 pcie->offset.io = res.start - range.pci_addr;
1848
1849 memcpy(&pcie->pio, &res, sizeof(res));
1850 pcie->pio.name = np->full_name;
1851
1852 /*
1853 * The Tegra PCIe host bridge uses this to program the
1854 * mapping of the I/O space to the physical address,
1855 * so we override the .start and .end fields here that
1856 * of_pci_range_to_resource() converted to I/O space.
1857 * We also set the IORESOURCE_MEM type to clarify that
1858 * the resource is in the physical memory space.
1859 */
1860 pcie->io.start = range.cpu_addr;
1861 pcie->io.end = range.cpu_addr + range.size - 1;
1862 pcie->io.flags = IORESOURCE_MEM;
1863 pcie->io.name = "I/O";
1864
1865 memcpy(&res, &pcie->io, sizeof(res));
1866 break;
1867
1868 case IORESOURCE_MEM:
1869 /*
1870 * Track the bus -> CPU memory mapping offset. This
1871 * assumes that the prefetchable and non-prefetchable
1872 * regions will be the last of type IORESOURCE_MEM in
1873 * the ranges property.
1874 * */
1875 pcie->offset.mem = res.start - range.pci_addr;
1876
1877 if (res.flags & IORESOURCE_PREFETCH) {
1878 memcpy(&pcie->prefetch, &res, sizeof(res));
1879 pcie->prefetch.name = "prefetchable";
1880 } else {
1881 memcpy(&pcie->mem, &res, sizeof(res));
1882 pcie->mem.name = "non-prefetchable";
1883 }
1884 break;
1885 }
1886
1887 if (res.start <= pcie->all.start)
1888 pcie->all.start = res.start;
1889
1890 if (res.end >= pcie->all.end)
1891 pcie->all.end = res.end;
1892 }
1893
1894 err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all);
1895 if (err < 0)
1896 return err;
1897
1898 err = of_pci_parse_bus_range(np, &pcie->busn);
1899 if (err < 0) {
1900 dev_err(pcie->dev, "failed to parse ranges property: %d\n",
1901 err);
1902 pcie->busn.name = np->name;
1903 pcie->busn.start = 0;
1904 pcie->busn.end = 0xff;
1905 pcie->busn.flags = IORESOURCE_BUS;
1906 }
1907
1908 /* parse root ports */
1909 for_each_child_of_node(np, port) {
1910 struct tegra_pcie_port *rp;
1911 unsigned int index;
1912 u32 value;
1913
1914 err = of_pci_get_devfn(port);
1915 if (err < 0) {
1916 dev_err(pcie->dev, "failed to parse address: %d\n",
1917 err);
1918 return err;
1919 }
1920
1921 index = PCI_SLOT(err);
1922
1923 if (index < 1 || index > soc->num_ports) {
1924 dev_err(pcie->dev, "invalid port number: %d\n", index);
1925 return -EINVAL;
1926 }
1927
1928 index--;
1929
1930 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1931 if (err < 0) {
1932 dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
1933 err);
1934 return err;
1935 }
1936
1937 if (value > 16) {
1938 dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
1939 return -EINVAL;
1940 }
1941
1942 lanes |= value << (index << 3);
1943
1944 if (!of_device_is_available(port)) {
1945 lane += value;
1946 continue;
1947 }
1948
1949 mask |= ((1 << value) - 1) << lane;
1950 lane += value;
1951
1952 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
1953 if (!rp)
1954 return -ENOMEM;
1955
1956 err = of_address_to_resource(port, 0, &rp->regs);
1957 if (err < 0) {
1958 dev_err(pcie->dev, "failed to parse address: %d\n",
1959 err);
1960 return err;
1961 }
1962
1963 INIT_LIST_HEAD(&rp->list);
1964 rp->index = index;
1965 rp->lanes = value;
1966 rp->pcie = pcie;
1967 rp->np = port;
1968
1969 rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
1970 if (IS_ERR(rp->base))
1971 return PTR_ERR(rp->base);
1972
1973 list_add_tail(&rp->list, &pcie->ports);
1974 }
1975
1976 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1977 if (err < 0) {
1978 dev_err(pcie->dev, "invalid lane configuration\n");
1979 return err;
1980 }
1981
1982 err = tegra_pcie_get_regulators(pcie, mask);
1983 if (err < 0)
1984 return err;
1985
1986 return 0;
1987 }
1988
1989 /*
1990 * FIXME: If there are no PCIe cards attached, then calling this function
1991 * can result in the increase of the bootup time as there are big timeout
1992 * loops.
1993 */
1994 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1995 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1996 {
1997 unsigned int retries = 3;
1998 unsigned long value;
1999
2000 /* override presence detection */
2001 value = readl(port->base + RP_PRIV_MISC);
2002 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
2003 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
2004 writel(value, port->base + RP_PRIV_MISC);
2005
2006 do {
2007 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2008
2009 do {
2010 value = readl(port->base + RP_VEND_XP);
2011
2012 if (value & RP_VEND_XP_DL_UP)
2013 break;
2014
2015 usleep_range(1000, 2000);
2016 } while (--timeout);
2017
2018 if (!timeout) {
2019 dev_err(port->pcie->dev, "link %u down, retrying\n",
2020 port->index);
2021 goto retry;
2022 }
2023
2024 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2025
2026 do {
2027 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2028
2029 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2030 return true;
2031
2032 usleep_range(1000, 2000);
2033 } while (--timeout);
2034
2035 retry:
2036 tegra_pcie_port_reset(port);
2037 } while (--retries);
2038
2039 return false;
2040 }
2041
2042 static int tegra_pcie_enable(struct tegra_pcie *pcie)
2043 {
2044 struct tegra_pcie_port *port, *tmp;
2045 struct hw_pci hw;
2046
2047 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2048 dev_info(pcie->dev, "probing port %u, using %u lanes\n",
2049 port->index, port->lanes);
2050
2051 tegra_pcie_port_enable(port);
2052
2053 if (tegra_pcie_port_check_link(port))
2054 continue;
2055
2056 dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
2057
2058 tegra_pcie_port_disable(port);
2059 tegra_pcie_port_free(port);
2060 }
2061
2062 memset(&hw, 0, sizeof(hw));
2063
2064 #ifdef CONFIG_PCI_MSI
2065 hw.msi_ctrl = &pcie->msi.chip;
2066 #endif
2067
2068 hw.nr_controllers = 1;
2069 hw.private_data = (void **)&pcie;
2070 hw.setup = tegra_pcie_setup;
2071 hw.map_irq = tegra_pcie_map_irq;
2072 hw.ops = &tegra_pcie_ops;
2073
2074 pci_common_init_dev(pcie->dev, &hw);
2075
2076 return 0;
2077 }
2078
2079 static const struct tegra_pcie_soc_data tegra20_pcie_data = {
2080 .num_ports = 2,
2081 .msi_base_shift = 0,
2082 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
2083 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
2084 .has_pex_clkreq_en = false,
2085 .has_pex_bias_ctrl = false,
2086 .has_intr_prsnt_sense = false,
2087 .has_cml_clk = false,
2088 .has_gen2 = false,
2089 };
2090
2091 static const struct tegra_pcie_soc_data tegra30_pcie_data = {
2092 .num_ports = 3,
2093 .msi_base_shift = 8,
2094 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2095 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2096 .has_pex_clkreq_en = true,
2097 .has_pex_bias_ctrl = true,
2098 .has_intr_prsnt_sense = true,
2099 .has_cml_clk = true,
2100 .has_gen2 = false,
2101 };
2102
2103 static const struct tegra_pcie_soc_data tegra124_pcie_data = {
2104 .num_ports = 2,
2105 .msi_base_shift = 8,
2106 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2107 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2108 .has_pex_clkreq_en = true,
2109 .has_pex_bias_ctrl = true,
2110 .has_intr_prsnt_sense = true,
2111 .has_cml_clk = true,
2112 .has_gen2 = true,
2113 };
2114
2115 static const struct of_device_id tegra_pcie_of_match[] = {
2116 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data },
2117 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
2118 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
2119 { },
2120 };
2121 MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
2122
2123 static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos)
2124 {
2125 struct tegra_pcie *pcie = s->private;
2126
2127 if (list_empty(&pcie->ports))
2128 return NULL;
2129
2130 seq_printf(s, "Index Status\n");
2131
2132 return seq_list_start(&pcie->ports, *pos);
2133 }
2134
2135 static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
2136 {
2137 struct tegra_pcie *pcie = s->private;
2138
2139 return seq_list_next(v, &pcie->ports, pos);
2140 }
2141
2142 static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
2143 {
2144 }
2145
2146 static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
2147 {
2148 bool up = false, active = false;
2149 struct tegra_pcie_port *port;
2150 unsigned int value;
2151
2152 port = list_entry(v, struct tegra_pcie_port, list);
2153
2154 value = readl(port->base + RP_VEND_XP);
2155
2156 if (value & RP_VEND_XP_DL_UP)
2157 up = true;
2158
2159 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2160
2161 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2162 active = true;
2163
2164 seq_printf(s, "%2u ", port->index);
2165
2166 if (up)
2167 seq_printf(s, "up");
2168
2169 if (active) {
2170 if (up)
2171 seq_printf(s, ", ");
2172
2173 seq_printf(s, "active");
2174 }
2175
2176 seq_printf(s, "\n");
2177 return 0;
2178 }
2179
2180 static const struct seq_operations tegra_pcie_ports_seq_ops = {
2181 .start = tegra_pcie_ports_seq_start,
2182 .next = tegra_pcie_ports_seq_next,
2183 .stop = tegra_pcie_ports_seq_stop,
2184 .show = tegra_pcie_ports_seq_show,
2185 };
2186
2187 static int tegra_pcie_ports_open(struct inode *inode, struct file *file)
2188 {
2189 struct tegra_pcie *pcie = inode->i_private;
2190 struct seq_file *s;
2191 int err;
2192
2193 err = seq_open(file, &tegra_pcie_ports_seq_ops);
2194 if (err)
2195 return err;
2196
2197 s = file->private_data;
2198 s->private = pcie;
2199
2200 return 0;
2201 }
2202
2203 static const struct file_operations tegra_pcie_ports_ops = {
2204 .owner = THIS_MODULE,
2205 .open = tegra_pcie_ports_open,
2206 .read = seq_read,
2207 .llseek = seq_lseek,
2208 .release = seq_release,
2209 };
2210
2211 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2212 {
2213 struct dentry *file;
2214
2215 pcie->debugfs = debugfs_create_dir("pcie", NULL);
2216 if (!pcie->debugfs)
2217 return -ENOMEM;
2218
2219 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs,
2220 pcie, &tegra_pcie_ports_ops);
2221 if (!file)
2222 goto remove;
2223
2224 return 0;
2225
2226 remove:
2227 debugfs_remove_recursive(pcie->debugfs);
2228 pcie->debugfs = NULL;
2229 return -ENOMEM;
2230 }
2231
2232 static int tegra_pcie_probe(struct platform_device *pdev)
2233 {
2234 const struct of_device_id *match;
2235 struct tegra_pcie *pcie;
2236 int err;
2237
2238 match = of_match_device(tegra_pcie_of_match, &pdev->dev);
2239 if (!match)
2240 return -ENODEV;
2241
2242 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
2243 if (!pcie)
2244 return -ENOMEM;
2245
2246 INIT_LIST_HEAD(&pcie->buses);
2247 INIT_LIST_HEAD(&pcie->ports);
2248 pcie->soc_data = match->data;
2249 pcie->dev = &pdev->dev;
2250
2251 err = tegra_pcie_parse_dt(pcie);
2252 if (err < 0)
2253 return err;
2254
2255 err = tegra_pcie_get_resources(pcie);
2256 if (err < 0) {
2257 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
2258 return err;
2259 }
2260
2261 err = tegra_pcie_enable_controller(pcie);
2262 if (err)
2263 goto put_resources;
2264
2265 /* setup the AFI address translations */
2266 tegra_pcie_setup_translations(pcie);
2267
2268 if (IS_ENABLED(CONFIG_PCI_MSI)) {
2269 err = tegra_pcie_enable_msi(pcie);
2270 if (err < 0) {
2271 dev_err(&pdev->dev,
2272 "failed to enable MSI support: %d\n",
2273 err);
2274 goto put_resources;
2275 }
2276 }
2277
2278 err = tegra_pcie_enable(pcie);
2279 if (err < 0) {
2280 dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
2281 goto disable_msi;
2282 }
2283
2284 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2285 err = tegra_pcie_debugfs_init(pcie);
2286 if (err < 0)
2287 dev_err(&pdev->dev, "failed to setup debugfs: %d\n",
2288 err);
2289 }
2290
2291 platform_set_drvdata(pdev, pcie);
2292 return 0;
2293
2294 disable_msi:
2295 if (IS_ENABLED(CONFIG_PCI_MSI))
2296 tegra_pcie_disable_msi(pcie);
2297 put_resources:
2298 tegra_pcie_put_resources(pcie);
2299 return err;
2300 }
2301
2302 static struct platform_driver tegra_pcie_driver = {
2303 .driver = {
2304 .name = "tegra-pcie",
2305 .of_match_table = tegra_pcie_of_match,
2306 .suppress_bind_attrs = true,
2307 },
2308 .probe = tegra_pcie_probe,
2309 };
2310 module_platform_driver(tegra_pcie_driver);
2311
2312 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2313 MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
2314 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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