2 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
4 * Author: Ley Foon Tan <lftan@altera.com>
5 * Description: Altera PCIe host controller driver
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/init.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
31 #define RP_TX_REG0 0x2000
32 #define RP_TX_REG1 0x2004
33 #define RP_TX_CNTRL 0x2008
36 #define RP_RXCPL_STATUS 0x2010
37 #define RP_RXCPL_EOP 0x2
38 #define RP_RXCPL_SOP 0x1
39 #define RP_RXCPL_REG0 0x2014
40 #define RP_RXCPL_REG1 0x2018
41 #define P2A_INT_STATUS 0x3060
42 #define P2A_INT_STS_ALL 0xf
43 #define P2A_INT_ENABLE 0x3070
44 #define P2A_INT_ENA_ALL 0xf
45 #define RP_LTSSM 0x3c64
46 #define RP_LTSSM_MASK 0x1f
49 /* TLP configuration type 0 and 1 */
50 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
51 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
52 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
53 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
54 #define TLP_PAYLOAD_SIZE 0x01
55 #define TLP_READ_TAG 0x1d
56 #define TLP_WRITE_TAG 0x10
57 #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
58 #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
59 #define TLP_CFG_DW2(bus, devfn, offset) \
60 (((bus) << 24) | ((devfn) << 16) | (offset))
61 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
62 #define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
63 #define TLP_HDR_SIZE 3
67 #define LINK_UP_TIMEOUT 5000
74 struct platform_device
*pdev
;
75 void __iomem
*cra_base
;
78 struct irq_domain
*irq_domain
;
79 struct resource bus_range
;
80 struct list_head resources
;
83 struct tlp_rp_regpair_t
{
89 static inline void cra_writel(struct altera_pcie
*pcie
, const u32 value
,
92 writel_relaxed(value
, pcie
->cra_base
+ reg
);
95 static inline u32
cra_readl(struct altera_pcie
*pcie
, const u32 reg
)
97 return readl_relaxed(pcie
->cra_base
+ reg
);
100 static bool altera_pcie_link_is_up(struct altera_pcie
*pcie
)
102 return !!((cra_readl(pcie
, RP_LTSSM
) & RP_LTSSM_MASK
) == LTSSM_L0
);
105 static void altera_pcie_retrain(struct pci_dev
*dev
)
107 u16 linkcap
, linkstat
;
108 struct altera_pcie
*pcie
= dev
->bus
->sysdata
;
111 if (!altera_pcie_link_is_up(pcie
))
115 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
116 * current speed is 2.5 GB/s.
118 pcie_capability_read_word(dev
, PCI_EXP_LNKCAP
, &linkcap
);
120 if ((linkcap
& PCI_EXP_LNKCAP_SLS
) <= PCI_EXP_LNKCAP_SLS_2_5GB
)
123 pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &linkstat
);
124 if ((linkstat
& PCI_EXP_LNKSTA_CLS
) == PCI_EXP_LNKSTA_CLS_2_5GB
) {
125 pcie_capability_set_word(dev
, PCI_EXP_LNKCTL
,
127 while (!altera_pcie_link_is_up(pcie
)) {
129 if (timeout
> LINK_UP_TIMEOUT
)
135 DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID
, altera_pcie_retrain
);
138 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
139 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
140 * using these registers, so it can be reached by DMA from EP devices.
141 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
142 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
143 * should be hidden during enumeration to avoid the sizing and resource
144 * allocation by PCIe core.
146 static bool altera_pcie_hide_rc_bar(struct pci_bus
*bus
, unsigned int devfn
,
149 if (pci_is_root_bus(bus
) && (devfn
== 0) &&
150 (offset
== PCI_BASE_ADDRESS_0
))
156 static void tlp_write_tx(struct altera_pcie
*pcie
,
157 struct tlp_rp_regpair_t
*tlp_rp_regdata
)
159 cra_writel(pcie
, tlp_rp_regdata
->reg0
, RP_TX_REG0
);
160 cra_writel(pcie
, tlp_rp_regdata
->reg1
, RP_TX_REG1
);
161 cra_writel(pcie
, tlp_rp_regdata
->ctrl
, RP_TX_CNTRL
);
164 static bool altera_pcie_valid_config(struct altera_pcie
*pcie
,
165 struct pci_bus
*bus
, int dev
)
167 /* If there is no link, then there is no device */
168 if (bus
->number
!= pcie
->root_bus_nr
) {
169 if (!altera_pcie_link_is_up(pcie
))
173 /* access only one slot on each root port */
174 if (bus
->number
== pcie
->root_bus_nr
&& dev
> 0)
178 * Do not read more than one device on the bus directly attached
179 * to root port, root port can only attach to one downstream port.
181 if (bus
->primary
== pcie
->root_bus_nr
&& dev
> 0)
187 static int tlp_read_packet(struct altera_pcie
*pcie
, u32
*value
)
196 * Minimum 2 loops to read TLP headers and 1 loop to read data
199 for (i
= 0; i
< TLP_LOOP
; i
++) {
200 ctrl
= cra_readl(pcie
, RP_RXCPL_STATUS
);
201 if ((ctrl
& RP_RXCPL_SOP
) || (ctrl
& RP_RXCPL_EOP
) || sop
) {
202 reg0
= cra_readl(pcie
, RP_RXCPL_REG0
);
203 reg1
= cra_readl(pcie
, RP_RXCPL_REG1
);
205 if (ctrl
& RP_RXCPL_SOP
) {
207 comp_status
= TLP_COMP_STATUS(reg1
);
210 if (ctrl
& RP_RXCPL_EOP
) {
212 return PCIBIOS_DEVICE_NOT_FOUND
;
217 return PCIBIOS_SUCCESSFUL
;
223 return PCIBIOS_DEVICE_NOT_FOUND
;
226 static void tlp_write_packet(struct altera_pcie
*pcie
, u32
*headers
,
227 u32 data
, bool align
)
229 struct tlp_rp_regpair_t tlp_rp_regdata
;
231 tlp_rp_regdata
.reg0
= headers
[0];
232 tlp_rp_regdata
.reg1
= headers
[1];
233 tlp_rp_regdata
.ctrl
= RP_TX_SOP
;
234 tlp_write_tx(pcie
, &tlp_rp_regdata
);
237 tlp_rp_regdata
.reg0
= headers
[2];
238 tlp_rp_regdata
.reg1
= 0;
239 tlp_rp_regdata
.ctrl
= 0;
240 tlp_write_tx(pcie
, &tlp_rp_regdata
);
242 tlp_rp_regdata
.reg0
= data
;
243 tlp_rp_regdata
.reg1
= 0;
245 tlp_rp_regdata
.reg0
= headers
[2];
246 tlp_rp_regdata
.reg1
= data
;
249 tlp_rp_regdata
.ctrl
= RP_TX_EOP
;
250 tlp_write_tx(pcie
, &tlp_rp_regdata
);
253 static int tlp_cfg_dword_read(struct altera_pcie
*pcie
, u8 bus
, u32 devfn
,
254 int where
, u8 byte_en
, u32
*value
)
256 u32 headers
[TLP_HDR_SIZE
];
258 if (bus
== pcie
->root_bus_nr
)
259 headers
[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0
);
261 headers
[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1
);
263 headers
[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie
->root_bus_nr
, RP_DEVFN
),
264 TLP_READ_TAG
, byte_en
);
265 headers
[2] = TLP_CFG_DW2(bus
, devfn
, where
);
267 tlp_write_packet(pcie
, headers
, 0, false);
269 return tlp_read_packet(pcie
, value
);
272 static int tlp_cfg_dword_write(struct altera_pcie
*pcie
, u8 bus
, u32 devfn
,
273 int where
, u8 byte_en
, u32 value
)
275 u32 headers
[TLP_HDR_SIZE
];
278 if (bus
== pcie
->root_bus_nr
)
279 headers
[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0
);
281 headers
[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1
);
283 headers
[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie
->root_bus_nr
, RP_DEVFN
),
284 TLP_WRITE_TAG
, byte_en
);
285 headers
[2] = TLP_CFG_DW2(bus
, devfn
, where
);
287 /* check alignment to Qword */
288 if ((where
& 0x7) == 0)
289 tlp_write_packet(pcie
, headers
, value
, true);
291 tlp_write_packet(pcie
, headers
, value
, false);
293 ret
= tlp_read_packet(pcie
, NULL
);
294 if (ret
!= PCIBIOS_SUCCESSFUL
)
298 * Monitor changes to PCI_PRIMARY_BUS register on root port
299 * and update local copy of root bus number accordingly.
301 if ((bus
== pcie
->root_bus_nr
) && (where
== PCI_PRIMARY_BUS
))
302 pcie
->root_bus_nr
= (u8
)(value
);
304 return PCIBIOS_SUCCESSFUL
;
307 static int altera_pcie_cfg_read(struct pci_bus
*bus
, unsigned int devfn
,
308 int where
, int size
, u32
*value
)
310 struct altera_pcie
*pcie
= bus
->sysdata
;
315 if (altera_pcie_hide_rc_bar(bus
, devfn
, where
))
316 return PCIBIOS_BAD_REGISTER_NUMBER
;
318 if (!altera_pcie_valid_config(pcie
, bus
, PCI_SLOT(devfn
))) {
320 return PCIBIOS_DEVICE_NOT_FOUND
;
325 byte_en
= 1 << (where
& 3);
328 byte_en
= 3 << (where
& 3);
335 ret
= tlp_cfg_dword_read(pcie
, bus
->number
, devfn
,
336 (where
& ~DWORD_MASK
), byte_en
, &data
);
337 if (ret
!= PCIBIOS_SUCCESSFUL
)
342 *value
= (data
>> (8 * (where
& 0x3))) & 0xff;
345 *value
= (data
>> (8 * (where
& 0x2))) & 0xffff;
352 return PCIBIOS_SUCCESSFUL
;
355 static int altera_pcie_cfg_write(struct pci_bus
*bus
, unsigned int devfn
,
356 int where
, int size
, u32 value
)
358 struct altera_pcie
*pcie
= bus
->sysdata
;
360 u32 shift
= 8 * (where
& 3);
363 if (altera_pcie_hide_rc_bar(bus
, devfn
, where
))
364 return PCIBIOS_BAD_REGISTER_NUMBER
;
366 if (!altera_pcie_valid_config(pcie
, bus
, PCI_SLOT(devfn
)))
367 return PCIBIOS_DEVICE_NOT_FOUND
;
371 data32
= (value
& 0xff) << shift
;
372 byte_en
= 1 << (where
& 3);
375 data32
= (value
& 0xffff) << shift
;
376 byte_en
= 3 << (where
& 3);
384 return tlp_cfg_dword_write(pcie
, bus
->number
, devfn
,
385 (where
& ~DWORD_MASK
), byte_en
, data32
);
388 static struct pci_ops altera_pcie_ops
= {
389 .read
= altera_pcie_cfg_read
,
390 .write
= altera_pcie_cfg_write
,
393 static int altera_pcie_intx_map(struct irq_domain
*domain
, unsigned int irq
,
394 irq_hw_number_t hwirq
)
396 irq_set_chip_and_handler(irq
, &dummy_irq_chip
, handle_simple_irq
);
397 irq_set_chip_data(irq
, domain
->host_data
);
402 static const struct irq_domain_ops intx_domain_ops
= {
403 .map
= altera_pcie_intx_map
,
406 static void altera_pcie_isr(struct irq_desc
*desc
)
408 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
409 struct altera_pcie
*pcie
;
410 unsigned long status
;
414 chained_irq_enter(chip
, desc
);
415 pcie
= irq_desc_get_handler_data(desc
);
417 while ((status
= cra_readl(pcie
, P2A_INT_STATUS
)
418 & P2A_INT_STS_ALL
) != 0) {
419 for_each_set_bit(bit
, &status
, INTX_NUM
) {
420 /* clear interrupts */
421 cra_writel(pcie
, 1 << bit
, P2A_INT_STATUS
);
423 virq
= irq_find_mapping(pcie
->irq_domain
, bit
+ 1);
425 generic_handle_irq(virq
);
427 dev_err(&pcie
->pdev
->dev
,
428 "unexpected IRQ, INT%d\n", bit
);
432 chained_irq_exit(chip
, desc
);
435 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie
*pcie
)
437 int err
, res_valid
= 0;
438 struct device
*dev
= &pcie
->pdev
->dev
;
439 struct device_node
*np
= dev
->of_node
;
440 struct resource_entry
*win
;
442 err
= of_pci_get_host_bridge_resources(np
, 0, 0xff, &pcie
->resources
,
447 err
= devm_request_pci_bus_resources(dev
, &pcie
->resources
);
449 goto out_release_res
;
451 resource_list_for_each_entry(win
, &pcie
->resources
) {
452 struct resource
*res
= win
->res
;
454 if (resource_type(res
) == IORESOURCE_MEM
)
455 res_valid
|= !(res
->flags
& IORESOURCE_PREFETCH
);
461 dev_err(dev
, "non-prefetchable memory resource required\n");
465 pci_free_resource_list(&pcie
->resources
);
469 static int altera_pcie_init_irq_domain(struct altera_pcie
*pcie
)
471 struct device
*dev
= &pcie
->pdev
->dev
;
472 struct device_node
*node
= dev
->of_node
;
475 pcie
->irq_domain
= irq_domain_add_linear(node
, INTX_NUM
+ 1,
476 &intx_domain_ops
, pcie
);
477 if (!pcie
->irq_domain
) {
478 dev_err(dev
, "Failed to get a INTx IRQ domain\n");
485 static int altera_pcie_parse_dt(struct altera_pcie
*pcie
)
487 struct resource
*cra
;
488 struct platform_device
*pdev
= pcie
->pdev
;
490 cra
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "Cra");
492 dev_err(&pdev
->dev
, "no Cra memory resource defined\n");
496 pcie
->cra_base
= devm_ioremap_resource(&pdev
->dev
, cra
);
497 if (IS_ERR(pcie
->cra_base
)) {
498 dev_err(&pdev
->dev
, "failed to map cra memory\n");
499 return PTR_ERR(pcie
->cra_base
);
503 pcie
->irq
= platform_get_irq(pdev
, 0);
504 if (pcie
->irq
<= 0) {
505 dev_err(&pdev
->dev
, "failed to get IRQ: %d\n", pcie
->irq
);
509 irq_set_chained_handler_and_data(pcie
->irq
, altera_pcie_isr
, pcie
);
514 static int altera_pcie_probe(struct platform_device
*pdev
)
516 struct altera_pcie
*pcie
;
518 struct pci_bus
*child
;
521 pcie
= devm_kzalloc(&pdev
->dev
, sizeof(*pcie
), GFP_KERNEL
);
527 ret
= altera_pcie_parse_dt(pcie
);
529 dev_err(&pdev
->dev
, "Parsing DT failed\n");
533 INIT_LIST_HEAD(&pcie
->resources
);
535 ret
= altera_pcie_parse_request_of_pci_ranges(pcie
);
537 dev_err(&pdev
->dev
, "Failed add resources\n");
541 ret
= altera_pcie_init_irq_domain(pcie
);
543 dev_err(&pdev
->dev
, "Failed creating IRQ Domain\n");
547 /* clear all interrupts */
548 cra_writel(pcie
, P2A_INT_STS_ALL
, P2A_INT_STATUS
);
549 /* enable all interrupts */
550 cra_writel(pcie
, P2A_INT_ENA_ALL
, P2A_INT_ENABLE
);
552 bus
= pci_scan_root_bus(&pdev
->dev
, pcie
->root_bus_nr
, &altera_pcie_ops
,
553 pcie
, &pcie
->resources
);
557 pci_fixup_irqs(pci_common_swizzle
, of_irq_parse_and_map_pci
);
558 pci_assign_unassigned_bus_resources(bus
);
560 /* Configure PCI Express setting. */
561 list_for_each_entry(child
, &bus
->children
, node
)
562 pcie_bus_configure_settings(child
);
564 pci_bus_add_devices(bus
);
566 platform_set_drvdata(pdev
, pcie
);
570 static const struct of_device_id altera_pcie_of_match
[] = {
571 { .compatible
= "altr,pcie-root-port-1.0", },
575 static struct platform_driver altera_pcie_driver
= {
576 .probe
= altera_pcie_probe
,
578 .name
= "altera-pcie",
579 .of_match_table
= altera_pcie_of_match
,
580 .suppress_bind_attrs
= true,
584 static int altera_pcie_init(void)
586 return platform_driver_register(&altera_pcie_driver
);
588 device_initcall(altera_pcie_init
);