drivers/pci/host/pcie-armada8k.c

   1 /*
   2  * PCIe host controller driver for Marvell Armada-8K SoCs
   3  *
   4  * Armada-8K PCIe Glue Layer Source Code
   5  *
   6  * Copyright (C) 2016 Marvell Technology Group Ltd.
   7  *
   8  * Author: Yehuda Yitshak <yehuday@marvell.com>
   9  * Author: Shadi Ammouri <shadi@marvell.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/pci.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/resource.h>
  26 #include <linux/of_pci.h>
  27 #include <linux/of_irq.h>
  28
  29 #include "pcie-designware.h"
  30
  31 struct armada8k_pcie {
  32         void __iomem *base;
  33         struct clk *clk;
  34         struct pcie_port pp;
  35 };
  36
  37 #define PCIE_VENDOR_REGS_OFFSET         0x8000
  38
  39 #define PCIE_GLOBAL_CONTROL_REG         0x0
  40 #define PCIE_APP_LTSSM_EN               BIT(2)
  41 #define PCIE_DEVICE_TYPE_SHIFT          4
  42 #define PCIE_DEVICE_TYPE_MASK           0xF
  43 #define PCIE_DEVICE_TYPE_RC             0x4 /* Root complex */
  44
  45 #define PCIE_GLOBAL_STATUS_REG          0x8
  46 #define PCIE_GLB_STS_RDLH_LINK_UP       BIT(1)
  47 #define PCIE_GLB_STS_PHY_LINK_UP        BIT(9)
  48
  49 #define PCIE_GLOBAL_INT_CAUSE1_REG      0x1C
  50 #define PCIE_GLOBAL_INT_MASK1_REG       0x20
  51 #define PCIE_INT_A_ASSERT_MASK          BIT(9)
  52 #define PCIE_INT_B_ASSERT_MASK          BIT(10)
  53 #define PCIE_INT_C_ASSERT_MASK          BIT(11)
  54 #define PCIE_INT_D_ASSERT_MASK          BIT(12)
  55
  56 #define PCIE_ARCACHE_TRC_REG            0x50
  57 #define PCIE_AWCACHE_TRC_REG            0x54
  58 #define PCIE_ARUSER_REG                 0x5C
  59 #define PCIE_AWUSER_REG                 0x60
  60 /*
  61  * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
  62  * allocate
  63  */
  64 #define ARCACHE_DEFAULT_VALUE           0x3511
  65 #define AWCACHE_DEFAULT_VALUE           0x5311
  66
  67 #define DOMAIN_OUTER_SHAREABLE          0x2
  68 #define AX_USER_DOMAIN_MASK             0x3
  69 #define AX_USER_DOMAIN_SHIFT            4
  70
  71 #define to_armada8k_pcie(x)     container_of(x, struct armada8k_pcie, pp)
  72
  73 static int armada8k_pcie_link_up(struct pcie_port *pp)
  74 {
  75         struct armada8k_pcie *pcie = to_armada8k_pcie(pp);
  76         u32 reg;
  77         u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
  78
  79         reg = readl(pcie->base + PCIE_GLOBAL_STATUS_REG);
  80
  81         if ((reg & mask) == mask)
  82                 return 1;
  83
  84         dev_dbg(pp->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
  85         return 0;
  86 }
  87
  88 static void armada8k_pcie_establish_link(struct pcie_port *pp)
  89 {
  90         struct armada8k_pcie *pcie = to_armada8k_pcie(pp);
  91         void __iomem *base = pcie->base;
  92         u32 reg;
  93
  94         if (!dw_pcie_link_up(pp)) {
  95                 /* Disable LTSSM state machine to enable configuration */
  96                 reg = readl(base + PCIE_GLOBAL_CONTROL_REG);
  97                 reg &= ~(PCIE_APP_LTSSM_EN);
  98                 writel(reg, base + PCIE_GLOBAL_CONTROL_REG);
  99         }
 100
 101         /* Set the device to root complex mode */
 102         reg = readl(base + PCIE_GLOBAL_CONTROL_REG);
 103         reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
 104         reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
 105         writel(reg, base + PCIE_GLOBAL_CONTROL_REG);
 106
 107         /* Set the PCIe master AxCache attributes */
 108         writel(ARCACHE_DEFAULT_VALUE, base + PCIE_ARCACHE_TRC_REG);
 109         writel(AWCACHE_DEFAULT_VALUE, base + PCIE_AWCACHE_TRC_REG);
 110
 111         /* Set the PCIe master AxDomain attributes */
 112         reg = readl(base + PCIE_ARUSER_REG);
 113         reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
 114         reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
 115         writel(reg, base + PCIE_ARUSER_REG);
 116
 117         reg = readl(base + PCIE_AWUSER_REG);
 118         reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
 119         reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
 120         writel(reg, base + PCIE_AWUSER_REG);
 121
 122         /* Enable INT A-D interrupts */
 123         reg = readl(base + PCIE_GLOBAL_INT_MASK1_REG);
 124         reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
 125                PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
 126         writel(reg, base + PCIE_GLOBAL_INT_MASK1_REG);
 127
 128         if (!dw_pcie_link_up(pp)) {
 129                 /* Configuration done. Start LTSSM */
 130                 reg = readl(base + PCIE_GLOBAL_CONTROL_REG);
 131                 reg |= PCIE_APP_LTSSM_EN;
 132                 writel(reg, base + PCIE_GLOBAL_CONTROL_REG);
 133         }
 134
 135         /* Wait until the link becomes active again */
 136         if (dw_pcie_wait_for_link(pp))
 137                 dev_err(pp->dev, "Link not up after reconfiguration\n");
 138 }
 139
 140 static void armada8k_pcie_host_init(struct pcie_port *pp)
 141 {
 142         dw_pcie_setup_rc(pp);
 143         armada8k_pcie_establish_link(pp);
 144 }
 145
 146 static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
 147 {
 148         struct pcie_port *pp = arg;
 149         struct armada8k_pcie *pcie = to_armada8k_pcie(pp);
 150         void __iomem *base = pcie->base;
 151         u32 val;
 152
 153         /*
 154          * Interrupts are directly handled by the device driver of the
 155          * PCI device. However, they are also latched into the PCIe
 156          * controller, so we simply discard them.
 157          */
 158         val = readl(base + PCIE_GLOBAL_INT_CAUSE1_REG);
 159         writel(val, base + PCIE_GLOBAL_INT_CAUSE1_REG);
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 static struct pcie_host_ops armada8k_pcie_host_ops = {
 165         .link_up = armada8k_pcie_link_up,
 166         .host_init = armada8k_pcie_host_init,
 167 };
 168
 169 static int armada8k_add_pcie_port(struct pcie_port *pp,
 170                                   struct platform_device *pdev)
 171 {
 172         struct device *dev = &pdev->dev;
 173         int ret;
 174
 175         pp->root_bus_nr = -1;
 176         pp->ops = &armada8k_pcie_host_ops;
 177
 178         pp->irq = platform_get_irq(pdev, 0);
 179         if (!pp->irq) {
 180                 dev_err(dev, "failed to get irq for port\n");
 181                 return -ENODEV;
 182         }
 183
 184         ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
 185                                IRQF_SHARED, "armada8k-pcie", pp);
 186         if (ret) {
 187                 dev_err(dev, "failed to request irq %d\n", pp->irq);
 188                 return ret;
 189         }
 190
 191         ret = dw_pcie_host_init(pp);
 192         if (ret) {
 193                 dev_err(dev, "failed to initialize host: %d\n", ret);
 194                 return ret;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int armada8k_pcie_probe(struct platform_device *pdev)
 201 {
 202         struct armada8k_pcie *pcie;
 203         struct pcie_port *pp;
 204         struct device *dev = &pdev->dev;
 205         struct resource *base;
 206         int ret;
 207
 208         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 209         if (!pcie)
 210                 return -ENOMEM;
 211
 212         pcie->clk = devm_clk_get(dev, NULL);
 213         if (IS_ERR(pcie->clk))
 214                 return PTR_ERR(pcie->clk);
 215
 216         clk_prepare_enable(pcie->clk);
 217
 218         pp = &pcie->pp;
 219         pp->dev = dev;
 220         platform_set_drvdata(pdev, pcie);
 221
 222         /* Get the dw-pcie unit configuration/control registers base. */
 223         base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
 224         pp->dbi_base = devm_ioremap_resource(dev, base);
 225         if (IS_ERR(pp->dbi_base)) {
 226                 dev_err(dev, "couldn't remap regs base %p\n", base);
 227                 ret = PTR_ERR(pp->dbi_base);
 228                 goto fail;
 229         }
 230
 231         pcie->base = pp->dbi_base + PCIE_VENDOR_REGS_OFFSET;
 232
 233         ret = armada8k_add_pcie_port(pp, pdev);
 234         if (ret)
 235                 goto fail;
 236
 237         return 0;
 238
 239 fail:
 240         if (!IS_ERR(pcie->clk))
 241                 clk_disable_unprepare(pcie->clk);
 242
 243         return ret;
 244 }
 245
 246 static const struct of_device_id armada8k_pcie_of_match[] = {
 247         { .compatible = "marvell,armada8k-pcie", },
 248         {},
 249 };
 250
 251 static struct platform_driver armada8k_pcie_driver = {
 252         .probe          = armada8k_pcie_probe,
 253         .driver = {
 254                 .name   = "armada8k-pcie",
 255                 .of_match_table = of_match_ptr(armada8k_pcie_of_match),
 256         },
 257 };
 258 builtin_platform_driver(armada8k_pcie_driver);