2 * PCIe host controller driver for Axis ARTPEC-6 SoC
4 * Author: Niklas Cassel <niklas.cassel@axis.com>
6 * Based on work done by Phil Edworthy <phil@edworthys.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/resource.h>
19 #include <linux/signal.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
25 #include "pcie-designware.h"
27 #define to_artpec6_pcie(x) container_of(x, struct artpec6_pcie, pp)
31 struct regmap
*regmap
;
32 void __iomem
*phy_base
;
35 /* PCIe Port Logic registers (memory-mapped) */
36 #define PL_OFFSET 0x700
37 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
38 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
40 #define MISC_CONTROL_1_OFF (PL_OFFSET + 0x1bc)
41 #define DBI_RO_WR_EN 1
43 /* ARTPEC-6 specific registers */
45 #define PCIECFG_DBG_OEN (1 << 24)
46 #define PCIECFG_CORE_RESET_REQ (1 << 21)
47 #define PCIECFG_LTSSM_ENABLE (1 << 20)
48 #define PCIECFG_CLKREQ_B (1 << 11)
49 #define PCIECFG_REFCLK_ENABLE (1 << 10)
50 #define PCIECFG_PLL_ENABLE (1 << 9)
51 #define PCIECFG_PCLK_ENABLE (1 << 8)
52 #define PCIECFG_RISRCREN (1 << 4)
53 #define PCIECFG_MODE_TX_DRV_EN (1 << 3)
54 #define PCIECFG_CISRREN (1 << 2)
55 #define PCIECFG_MACRO_ENABLE (1 << 0)
58 #define NOCCFG_ENABLE_CLK_PCIE (1 << 4)
59 #define NOCCFG_POWER_PCIE_IDLEACK (1 << 3)
60 #define NOCCFG_POWER_PCIE_IDLE (1 << 2)
61 #define NOCCFG_POWER_PCIE_IDLEREQ (1 << 1)
63 #define PHY_STATUS 0x118
64 #define PHY_COSPLLLOCK (1 << 0)
66 #define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
68 static int artpec6_pcie_establish_link(struct pcie_port
*pp
)
70 struct artpec6_pcie
*artpec6_pcie
= to_artpec6_pcie(pp
);
74 /* Hold DW core in reset */
75 regmap_read(artpec6_pcie
->regmap
, PCIECFG
, &val
);
76 val
|= PCIECFG_CORE_RESET_REQ
;
77 regmap_write(artpec6_pcie
->regmap
, PCIECFG
, val
);
79 regmap_read(artpec6_pcie
->regmap
, PCIECFG
, &val
);
80 val
|= PCIECFG_RISRCREN
| /* Receiver term. 50 Ohm */
81 PCIECFG_MODE_TX_DRV_EN
|
82 PCIECFG_CISRREN
| /* Reference clock term. 100 Ohm */
84 val
|= PCIECFG_REFCLK_ENABLE
;
85 val
&= ~PCIECFG_DBG_OEN
;
86 val
&= ~PCIECFG_CLKREQ_B
;
87 regmap_write(artpec6_pcie
->regmap
, PCIECFG
, val
);
88 usleep_range(5000, 6000);
90 regmap_read(artpec6_pcie
->regmap
, NOCCFG
, &val
);
91 val
|= NOCCFG_ENABLE_CLK_PCIE
;
92 regmap_write(artpec6_pcie
->regmap
, NOCCFG
, val
);
95 regmap_read(artpec6_pcie
->regmap
, PCIECFG
, &val
);
96 val
|= PCIECFG_PCLK_ENABLE
| PCIECFG_PLL_ENABLE
;
97 regmap_write(artpec6_pcie
->regmap
, PCIECFG
, val
);
98 usleep_range(6000, 7000);
100 regmap_read(artpec6_pcie
->regmap
, NOCCFG
, &val
);
101 val
&= ~NOCCFG_POWER_PCIE_IDLEREQ
;
102 regmap_write(artpec6_pcie
->regmap
, NOCCFG
, val
);
106 usleep_range(1000, 2000);
107 regmap_read(artpec6_pcie
->regmap
, NOCCFG
, &val
);
110 (val
& (NOCCFG_POWER_PCIE_IDLEACK
| NOCCFG_POWER_PCIE_IDLE
)));
114 usleep_range(1000, 2000);
115 val
= readl(artpec6_pcie
->phy_base
+ PHY_STATUS
);
117 } while (retries
&& !(val
& PHY_COSPLLLOCK
));
119 /* Take DW core out of reset */
120 regmap_read(artpec6_pcie
->regmap
, PCIECFG
, &val
);
121 val
&= ~PCIECFG_CORE_RESET_REQ
;
122 regmap_write(artpec6_pcie
->regmap
, PCIECFG
, val
);
123 usleep_range(100, 200);
126 * Enable writing to config regs. This is required as the Synopsys
127 * driver changes the class code. That register needs DBI write enable.
129 writel(DBI_RO_WR_EN
, pp
->dbi_base
+ MISC_CONTROL_1_OFF
);
131 pp
->io_base
&= ARTPEC6_CPU_TO_BUS_ADDR
;
132 pp
->mem_base
&= ARTPEC6_CPU_TO_BUS_ADDR
;
133 pp
->cfg0_base
&= ARTPEC6_CPU_TO_BUS_ADDR
;
134 pp
->cfg1_base
&= ARTPEC6_CPU_TO_BUS_ADDR
;
136 /* setup root complex */
137 dw_pcie_setup_rc(pp
);
139 /* assert LTSSM enable */
140 regmap_read(artpec6_pcie
->regmap
, PCIECFG
, &val
);
141 val
|= PCIECFG_LTSSM_ENABLE
;
142 regmap_write(artpec6_pcie
->regmap
, PCIECFG
, val
);
144 /* check if the link is up or not */
145 if (!dw_pcie_wait_for_link(pp
))
148 dev_dbg(pp
->dev
, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
149 readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R0
),
150 readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
));
155 static void artpec6_pcie_enable_interrupts(struct pcie_port
*pp
)
157 if (IS_ENABLED(CONFIG_PCI_MSI
))
158 dw_pcie_msi_init(pp
);
161 static void artpec6_pcie_host_init(struct pcie_port
*pp
)
163 artpec6_pcie_establish_link(pp
);
164 artpec6_pcie_enable_interrupts(pp
);
167 static int artpec6_pcie_link_up(struct pcie_port
*pp
)
172 * Get status from Synopsys IP
173 * link is debug bit 36, debug register 1 starts at bit 32
175 rc
= readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
) & (0x1 << (36 - 32));
182 static struct pcie_host_ops artpec6_pcie_host_ops
= {
183 .link_up
= artpec6_pcie_link_up
,
184 .host_init
= artpec6_pcie_host_init
,
187 static irqreturn_t
artpec6_pcie_msi_handler(int irq
, void *arg
)
189 struct pcie_port
*pp
= arg
;
191 return dw_handle_msi_irq(pp
);
194 static int __init
artpec6_add_pcie_port(struct pcie_port
*pp
,
195 struct platform_device
*pdev
)
199 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
200 pp
->msi_irq
= platform_get_irq_byname(pdev
, "msi");
201 if (pp
->msi_irq
<= 0) {
202 dev_err(&pdev
->dev
, "failed to get MSI irq\n");
206 ret
= devm_request_irq(&pdev
->dev
, pp
->msi_irq
,
207 artpec6_pcie_msi_handler
,
208 IRQF_SHARED
| IRQF_NO_THREAD
,
209 "artpec6-pcie-msi", pp
);
211 dev_err(&pdev
->dev
, "failed to request MSI irq\n");
216 pp
->root_bus_nr
= -1;
217 pp
->ops
= &artpec6_pcie_host_ops
;
219 ret
= dw_pcie_host_init(pp
);
221 dev_err(&pdev
->dev
, "failed to initialize host\n");
228 static int artpec6_pcie_probe(struct platform_device
*pdev
)
230 struct artpec6_pcie
*artpec6_pcie
;
231 struct pcie_port
*pp
;
232 struct resource
*dbi_base
;
233 struct resource
*phy_base
;
236 artpec6_pcie
= devm_kzalloc(&pdev
->dev
, sizeof(*artpec6_pcie
),
241 pp
= &artpec6_pcie
->pp
;
242 pp
->dev
= &pdev
->dev
;
244 dbi_base
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dbi");
245 pp
->dbi_base
= devm_ioremap_resource(&pdev
->dev
, dbi_base
);
246 if (IS_ERR(pp
->dbi_base
))
247 return PTR_ERR(pp
->dbi_base
);
249 phy_base
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "phy");
250 artpec6_pcie
->phy_base
= devm_ioremap_resource(&pdev
->dev
, phy_base
);
251 if (IS_ERR(artpec6_pcie
->phy_base
))
252 return PTR_ERR(artpec6_pcie
->phy_base
);
254 artpec6_pcie
->regmap
=
255 syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
257 if (IS_ERR(artpec6_pcie
->regmap
))
258 return PTR_ERR(artpec6_pcie
->regmap
);
260 ret
= artpec6_add_pcie_port(pp
, pdev
);
264 platform_set_drvdata(pdev
, artpec6_pcie
);
268 static const struct of_device_id artpec6_pcie_of_match
[] = {
269 { .compatible
= "axis,artpec6-pcie", },
273 static struct platform_driver artpec6_pcie_driver
= {
274 .probe
= artpec6_pcie_probe
,
276 .name
= "artpec6-pcie",
277 .of_match_table
= artpec6_pcie_of_match
,
280 builtin_platform_driver(artpec6_pcie_driver
);