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Merge branches 'pci/hotplug', 'pci/iommu', 'pci/irq' and 'pci/virtualization' into...
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
1 /*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
25
26 #include "pcie-designware.h"
27
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34 #define PORT_LINK_MODE_8_LANES (0xf << 16)
35
36 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
37 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
38 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
39 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
41 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
42 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
43
44 #define PCIE_MSI_ADDR_LO 0x820
45 #define PCIE_MSI_ADDR_HI 0x824
46 #define PCIE_MSI_INTR0_ENABLE 0x828
47 #define PCIE_MSI_INTR0_MASK 0x82C
48 #define PCIE_MSI_INTR0_STATUS 0x830
49
50 #define PCIE_ATU_VIEWPORT 0x900
51 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
52 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
53 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
54 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
55 #define PCIE_ATU_CR1 0x904
56 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
57 #define PCIE_ATU_TYPE_IO (0x2 << 0)
58 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
59 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
60 #define PCIE_ATU_CR2 0x908
61 #define PCIE_ATU_ENABLE (0x1 << 31)
62 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
63 #define PCIE_ATU_LOWER_BASE 0x90C
64 #define PCIE_ATU_UPPER_BASE 0x910
65 #define PCIE_ATU_LIMIT 0x914
66 #define PCIE_ATU_LOWER_TARGET 0x918
67 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
68 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
69 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
70 #define PCIE_ATU_UPPER_TARGET 0x91C
71
72 static struct hw_pci dw_pci;
73
74 static unsigned long global_io_offset;
75
76 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
77 {
78 BUG_ON(!sys->private_data);
79
80 return sys->private_data;
81 }
82
83 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
84 {
85 *val = readl(addr);
86
87 if (size == 1)
88 *val = (*val >> (8 * (where & 3))) & 0xff;
89 else if (size == 2)
90 *val = (*val >> (8 * (where & 3))) & 0xffff;
91 else if (size != 4)
92 return PCIBIOS_BAD_REGISTER_NUMBER;
93
94 return PCIBIOS_SUCCESSFUL;
95 }
96
97 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
98 {
99 if (size == 4)
100 writel(val, addr);
101 else if (size == 2)
102 writew(val, addr + (where & 2));
103 else if (size == 1)
104 writeb(val, addr + (where & 3));
105 else
106 return PCIBIOS_BAD_REGISTER_NUMBER;
107
108 return PCIBIOS_SUCCESSFUL;
109 }
110
111 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
112 {
113 if (pp->ops->readl_rc)
114 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
115 else
116 *val = readl(pp->dbi_base + reg);
117 }
118
119 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
120 {
121 if (pp->ops->writel_rc)
122 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
123 else
124 writel(val, pp->dbi_base + reg);
125 }
126
127 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
128 u32 *val)
129 {
130 int ret;
131
132 if (pp->ops->rd_own_conf)
133 ret = pp->ops->rd_own_conf(pp, where, size, val);
134 else
135 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
136 size, val);
137
138 return ret;
139 }
140
141 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
142 u32 val)
143 {
144 int ret;
145
146 if (pp->ops->wr_own_conf)
147 ret = pp->ops->wr_own_conf(pp, where, size, val);
148 else
149 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
150 size, val);
151
152 return ret;
153 }
154
155 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
156 int type, u64 cpu_addr, u64 pci_addr, u32 size)
157 {
158 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
159 PCIE_ATU_VIEWPORT);
160 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
161 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
162 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
163 PCIE_ATU_LIMIT);
164 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
165 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
166 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
167 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
168 }
169
170 static struct irq_chip dw_msi_irq_chip = {
171 .name = "PCI-MSI",
172 .irq_enable = pci_msi_unmask_irq,
173 .irq_disable = pci_msi_mask_irq,
174 .irq_mask = pci_msi_mask_irq,
175 .irq_unmask = pci_msi_unmask_irq,
176 };
177
178 /* MSI int handler */
179 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
180 {
181 unsigned long val;
182 int i, pos, irq;
183 irqreturn_t ret = IRQ_NONE;
184
185 for (i = 0; i < MAX_MSI_CTRLS; i++) {
186 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
187 (u32 *)&val);
188 if (val) {
189 ret = IRQ_HANDLED;
190 pos = 0;
191 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
192 irq = irq_find_mapping(pp->irq_domain,
193 i * 32 + pos);
194 dw_pcie_wr_own_conf(pp,
195 PCIE_MSI_INTR0_STATUS + i * 12,
196 4, 1 << pos);
197 generic_handle_irq(irq);
198 pos++;
199 }
200 }
201 }
202
203 return ret;
204 }
205
206 void dw_pcie_msi_init(struct pcie_port *pp)
207 {
208 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
209
210 /* program the msi_data */
211 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
212 virt_to_phys((void *)pp->msi_data));
213 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
214 }
215
216 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
217 {
218 unsigned int res, bit, val;
219
220 res = (irq / 32) * 12;
221 bit = irq % 32;
222 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
223 val &= ~(1 << bit);
224 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
225 }
226
227 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
228 unsigned int nvec, unsigned int pos)
229 {
230 unsigned int i;
231
232 for (i = 0; i < nvec; i++) {
233 irq_set_msi_desc_off(irq_base, i, NULL);
234 /* Disable corresponding interrupt on MSI controller */
235 if (pp->ops->msi_clear_irq)
236 pp->ops->msi_clear_irq(pp, pos + i);
237 else
238 dw_pcie_msi_clear_irq(pp, pos + i);
239 }
240
241 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
242 }
243
244 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
245 {
246 unsigned int res, bit, val;
247
248 res = (irq / 32) * 12;
249 bit = irq % 32;
250 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
251 val |= 1 << bit;
252 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
253 }
254
255 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
256 {
257 int irq, pos0, i;
258 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
259
260 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
261 order_base_2(no_irqs));
262 if (pos0 < 0)
263 goto no_valid_irq;
264
265 irq = irq_find_mapping(pp->irq_domain, pos0);
266 if (!irq)
267 goto no_valid_irq;
268
269 /*
270 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
271 * descs so there is no need to allocate descs here. We can therefore
272 * assume that if irq_find_mapping above returns non-zero, then the
273 * descs are also successfully allocated.
274 */
275
276 for (i = 0; i < no_irqs; i++) {
277 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
278 clear_irq_range(pp, irq, i, pos0);
279 goto no_valid_irq;
280 }
281 /*Enable corresponding interrupt in MSI interrupt controller */
282 if (pp->ops->msi_set_irq)
283 pp->ops->msi_set_irq(pp, pos0 + i);
284 else
285 dw_pcie_msi_set_irq(pp, pos0 + i);
286 }
287
288 *pos = pos0;
289 return irq;
290
291 no_valid_irq:
292 *pos = pos0;
293 return -ENOSPC;
294 }
295
296 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
297 struct msi_desc *desc)
298 {
299 int irq, pos;
300 struct msi_msg msg;
301 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
302
303 if (desc->msi_attrib.is_msix)
304 return -EINVAL;
305
306 irq = assign_irq(1, desc, &pos);
307 if (irq < 0)
308 return irq;
309
310 if (pp->ops->get_msi_addr)
311 msg.address_lo = pp->ops->get_msi_addr(pp);
312 else
313 msg.address_lo = virt_to_phys((void *)pp->msi_data);
314 msg.address_hi = 0x0;
315
316 if (pp->ops->get_msi_data)
317 msg.data = pp->ops->get_msi_data(pp, pos);
318 else
319 msg.data = pos;
320
321 pci_write_msi_msg(irq, &msg);
322
323 return 0;
324 }
325
326 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
327 {
328 struct irq_data *data = irq_get_irq_data(irq);
329 struct msi_desc *msi = irq_data_get_msi(data);
330 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
331
332 clear_irq_range(pp, irq, 1, data->hwirq);
333 }
334
335 static struct msi_controller dw_pcie_msi_chip = {
336 .setup_irq = dw_msi_setup_irq,
337 .teardown_irq = dw_msi_teardown_irq,
338 };
339
340 int dw_pcie_link_up(struct pcie_port *pp)
341 {
342 if (pp->ops->link_up)
343 return pp->ops->link_up(pp);
344 else
345 return 0;
346 }
347
348 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
349 irq_hw_number_t hwirq)
350 {
351 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
352 irq_set_chip_data(irq, domain->host_data);
353
354 return 0;
355 }
356
357 static const struct irq_domain_ops msi_domain_ops = {
358 .map = dw_pcie_msi_map,
359 };
360
361 int dw_pcie_host_init(struct pcie_port *pp)
362 {
363 struct device_node *np = pp->dev->of_node;
364 struct platform_device *pdev = to_platform_device(pp->dev);
365 struct of_pci_range range;
366 struct of_pci_range_parser parser;
367 struct resource *cfg_res;
368 u32 val, na, ns;
369 const __be32 *addrp;
370 int i, index, ret;
371
372 /* Find the address cell size and the number of cells in order to get
373 * the untranslated address.
374 */
375 of_property_read_u32(np, "#address-cells", &na);
376 ns = of_n_size_cells(np);
377
378 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
379 if (cfg_res) {
380 pp->cfg0_size = resource_size(cfg_res)/2;
381 pp->cfg1_size = resource_size(cfg_res)/2;
382 pp->cfg0_base = cfg_res->start;
383 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
384
385 /* Find the untranslated configuration space address */
386 index = of_property_match_string(np, "reg-names", "config");
387 addrp = of_get_address(np, index, NULL, NULL);
388 pp->cfg0_mod_base = of_read_number(addrp, ns);
389 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
390 } else if (!pp->va_cfg0_base) {
391 dev_err(pp->dev, "missing *config* reg space\n");
392 }
393
394 if (of_pci_range_parser_init(&parser, np)) {
395 dev_err(pp->dev, "missing ranges property\n");
396 return -EINVAL;
397 }
398
399 /* Get the I/O and memory ranges from DT */
400 for_each_of_pci_range(&parser, &range) {
401 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
402
403 if (restype == IORESOURCE_IO) {
404 of_pci_range_to_resource(&range, np, &pp->io);
405 pp->io.name = "I/O";
406 pp->io.start = max_t(resource_size_t,
407 PCIBIOS_MIN_IO,
408 range.pci_addr + global_io_offset);
409 pp->io.end = min_t(resource_size_t,
410 IO_SPACE_LIMIT,
411 range.pci_addr + range.size
412 + global_io_offset - 1);
413 pp->io_size = resource_size(&pp->io);
414 pp->io_bus_addr = range.pci_addr;
415 pp->io_base = range.cpu_addr;
416
417 /* Find the untranslated IO space address */
418 pp->io_mod_base = of_read_number(parser.range -
419 parser.np + na, ns);
420 }
421 if (restype == IORESOURCE_MEM) {
422 of_pci_range_to_resource(&range, np, &pp->mem);
423 pp->mem.name = "MEM";
424 pp->mem_size = resource_size(&pp->mem);
425 pp->mem_bus_addr = range.pci_addr;
426
427 /* Find the untranslated MEM space address */
428 pp->mem_mod_base = of_read_number(parser.range -
429 parser.np + na, ns);
430 }
431 if (restype == 0) {
432 of_pci_range_to_resource(&range, np, &pp->cfg);
433 pp->cfg0_size = resource_size(&pp->cfg)/2;
434 pp->cfg1_size = resource_size(&pp->cfg)/2;
435 pp->cfg0_base = pp->cfg.start;
436 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
437
438 /* Find the untranslated configuration space address */
439 pp->cfg0_mod_base = of_read_number(parser.range -
440 parser.np + na, ns);
441 pp->cfg1_mod_base = pp->cfg0_mod_base +
442 pp->cfg0_size;
443 }
444 }
445
446 ret = of_pci_parse_bus_range(np, &pp->busn);
447 if (ret < 0) {
448 pp->busn.name = np->name;
449 pp->busn.start = 0;
450 pp->busn.end = 0xff;
451 pp->busn.flags = IORESOURCE_BUS;
452 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
453 ret, &pp->busn);
454 }
455
456 if (!pp->dbi_base) {
457 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
458 resource_size(&pp->cfg));
459 if (!pp->dbi_base) {
460 dev_err(pp->dev, "error with ioremap\n");
461 return -ENOMEM;
462 }
463 }
464
465 pp->mem_base = pp->mem.start;
466
467 if (!pp->va_cfg0_base) {
468 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
469 pp->cfg0_size);
470 if (!pp->va_cfg0_base) {
471 dev_err(pp->dev, "error with ioremap in function\n");
472 return -ENOMEM;
473 }
474 }
475
476 if (!pp->va_cfg1_base) {
477 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
478 pp->cfg1_size);
479 if (!pp->va_cfg1_base) {
480 dev_err(pp->dev, "error with ioremap\n");
481 return -ENOMEM;
482 }
483 }
484
485 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
486 dev_err(pp->dev, "Failed to parse the number of lanes\n");
487 return -EINVAL;
488 }
489
490 if (IS_ENABLED(CONFIG_PCI_MSI)) {
491 if (!pp->ops->msi_host_init) {
492 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
493 MAX_MSI_IRQS, &msi_domain_ops,
494 &dw_pcie_msi_chip);
495 if (!pp->irq_domain) {
496 dev_err(pp->dev, "irq domain init failed\n");
497 return -ENXIO;
498 }
499
500 for (i = 0; i < MAX_MSI_IRQS; i++)
501 irq_create_mapping(pp->irq_domain, i);
502 } else {
503 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
504 if (ret < 0)
505 return ret;
506 }
507 }
508
509 if (pp->ops->host_init)
510 pp->ops->host_init(pp);
511
512 if (!pp->ops->rd_other_conf)
513 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
514 PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
515 pp->mem_bus_addr, pp->mem_size);
516
517 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
518
519 /* program correct class for RC */
520 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
521
522 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
523 val |= PORT_LOGIC_SPEED_CHANGE;
524 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
525
526 #ifdef CONFIG_PCI_MSI
527 dw_pcie_msi_chip.dev = pp->dev;
528 dw_pci.msi_ctrl = &dw_pcie_msi_chip;
529 #endif
530
531 dw_pci.nr_controllers = 1;
532 dw_pci.private_data = (void **)&pp;
533
534 pci_common_init_dev(pp->dev, &dw_pci);
535
536 return 0;
537 }
538
539 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
540 u32 devfn, int where, int size, u32 *val)
541 {
542 int ret, type;
543 u32 address, busdev, cfg_size;
544 u64 cpu_addr;
545 void __iomem *va_cfg_base;
546
547 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
548 PCIE_ATU_FUNC(PCI_FUNC(devfn));
549 address = where & ~0x3;
550
551 if (bus->parent->number == pp->root_bus_nr) {
552 type = PCIE_ATU_TYPE_CFG0;
553 cpu_addr = pp->cfg0_mod_base;
554 cfg_size = pp->cfg0_size;
555 va_cfg_base = pp->va_cfg0_base;
556 } else {
557 type = PCIE_ATU_TYPE_CFG1;
558 cpu_addr = pp->cfg1_mod_base;
559 cfg_size = pp->cfg1_size;
560 va_cfg_base = pp->va_cfg1_base;
561 }
562
563 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
564 type, cpu_addr,
565 busdev, cfg_size);
566 ret = dw_pcie_cfg_read(va_cfg_base + address, where, size, val);
567 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
568 PCIE_ATU_TYPE_IO, pp->io_mod_base,
569 pp->io_bus_addr, pp->io_size);
570
571 return ret;
572 }
573
574 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
575 u32 devfn, int where, int size, u32 val)
576 {
577 int ret, type;
578 u32 address, busdev, cfg_size;
579 u64 cpu_addr;
580 void __iomem *va_cfg_base;
581
582 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
583 PCIE_ATU_FUNC(PCI_FUNC(devfn));
584 address = where & ~0x3;
585
586 if (bus->parent->number == pp->root_bus_nr) {
587 type = PCIE_ATU_TYPE_CFG0;
588 cpu_addr = pp->cfg0_mod_base;
589 cfg_size = pp->cfg0_size;
590 va_cfg_base = pp->va_cfg0_base;
591 } else {
592 type = PCIE_ATU_TYPE_CFG1;
593 cpu_addr = pp->cfg1_mod_base;
594 cfg_size = pp->cfg1_size;
595 va_cfg_base = pp->va_cfg1_base;
596 }
597
598 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
599 type, cpu_addr,
600 busdev, cfg_size);
601 ret = dw_pcie_cfg_write(va_cfg_base + address, where, size, val);
602 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
603 PCIE_ATU_TYPE_IO, pp->io_mod_base,
604 pp->io_bus_addr, pp->io_size);
605
606 return ret;
607 }
608
609 static int dw_pcie_valid_config(struct pcie_port *pp,
610 struct pci_bus *bus, int dev)
611 {
612 /* If there is no link, then there is no device */
613 if (bus->number != pp->root_bus_nr) {
614 if (!dw_pcie_link_up(pp))
615 return 0;
616 }
617
618 /* access only one slot on each root port */
619 if (bus->number == pp->root_bus_nr && dev > 0)
620 return 0;
621
622 /*
623 * do not read more than one device on the bus directly attached
624 * to RC's (Virtual Bridge's) DS side.
625 */
626 if (bus->primary == pp->root_bus_nr && dev > 0)
627 return 0;
628
629 return 1;
630 }
631
632 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
633 int size, u32 *val)
634 {
635 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
636 int ret;
637
638 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
639 *val = 0xffffffff;
640 return PCIBIOS_DEVICE_NOT_FOUND;
641 }
642
643 if (bus->number != pp->root_bus_nr)
644 if (pp->ops->rd_other_conf)
645 ret = pp->ops->rd_other_conf(pp, bus, devfn,
646 where, size, val);
647 else
648 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
649 where, size, val);
650 else
651 ret = dw_pcie_rd_own_conf(pp, where, size, val);
652
653 return ret;
654 }
655
656 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
657 int where, int size, u32 val)
658 {
659 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
660 int ret;
661
662 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
663 return PCIBIOS_DEVICE_NOT_FOUND;
664
665 if (bus->number != pp->root_bus_nr)
666 if (pp->ops->wr_other_conf)
667 ret = pp->ops->wr_other_conf(pp, bus, devfn,
668 where, size, val);
669 else
670 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
671 where, size, val);
672 else
673 ret = dw_pcie_wr_own_conf(pp, where, size, val);
674
675 return ret;
676 }
677
678 static struct pci_ops dw_pcie_ops = {
679 .read = dw_pcie_rd_conf,
680 .write = dw_pcie_wr_conf,
681 };
682
683 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
684 {
685 struct pcie_port *pp;
686
687 pp = sys_to_pcie(sys);
688
689 if (global_io_offset < SZ_1M && pp->io_size > 0) {
690 sys->io_offset = global_io_offset - pp->io_bus_addr;
691 pci_ioremap_io(global_io_offset, pp->io_base);
692 global_io_offset += SZ_64K;
693 pci_add_resource_offset(&sys->resources, &pp->io,
694 sys->io_offset);
695 }
696
697 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
698 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
699 pci_add_resource(&sys->resources, &pp->busn);
700
701 return 1;
702 }
703
704 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
705 {
706 struct pci_bus *bus;
707 struct pcie_port *pp = sys_to_pcie(sys);
708
709 pp->root_bus_nr = sys->busnr;
710 bus = pci_scan_root_bus(pp->dev, sys->busnr,
711 &dw_pcie_ops, sys, &sys->resources);
712 if (!bus)
713 return NULL;
714
715 if (bus && pp->ops->scan_bus)
716 pp->ops->scan_bus(pp);
717
718 return bus;
719 }
720
721 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
722 {
723 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
724 int irq;
725
726 irq = of_irq_parse_and_map_pci(dev, slot, pin);
727 if (!irq)
728 irq = pp->irq;
729
730 return irq;
731 }
732
733 static struct hw_pci dw_pci = {
734 .setup = dw_pcie_setup,
735 .scan = dw_pcie_scan_bus,
736 .map_irq = dw_pcie_map_irq,
737 };
738
739 void dw_pcie_setup_rc(struct pcie_port *pp)
740 {
741 u32 val;
742 u32 membase;
743 u32 memlimit;
744
745 /* set the number of lanes */
746 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
747 val &= ~PORT_LINK_MODE_MASK;
748 switch (pp->lanes) {
749 case 1:
750 val |= PORT_LINK_MODE_1_LANES;
751 break;
752 case 2:
753 val |= PORT_LINK_MODE_2_LANES;
754 break;
755 case 4:
756 val |= PORT_LINK_MODE_4_LANES;
757 break;
758 case 8:
759 val |= PORT_LINK_MODE_8_LANES;
760 break;
761 }
762 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
763
764 /* set link width speed control register */
765 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
766 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
767 switch (pp->lanes) {
768 case 1:
769 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
770 break;
771 case 2:
772 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
773 break;
774 case 4:
775 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
776 break;
777 case 8:
778 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
779 break;
780 }
781 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
782
783 /* setup RC BARs */
784 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
785 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
786
787 /* setup interrupt pins */
788 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
789 val &= 0xffff00ff;
790 val |= 0x00000100;
791 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
792
793 /* setup bus numbers */
794 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
795 val &= 0xff000000;
796 val |= 0x00010100;
797 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
798
799 /* setup memory base, memory limit */
800 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
801 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
802 val = memlimit | membase;
803 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
804
805 /* setup command register */
806 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
807 val &= 0xffff0000;
808 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
809 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
810 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
811 }
812
813 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
814 MODULE_DESCRIPTION("Designware PCIe host controller driver");
815 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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