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PCI: designware: Parse bus-range property from devicetree
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
1 /*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
25
26 #include "pcie-designware.h"
27
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34
35 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
38 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
41
42 #define PCIE_MSI_ADDR_LO 0x820
43 #define PCIE_MSI_ADDR_HI 0x824
44 #define PCIE_MSI_INTR0_ENABLE 0x828
45 #define PCIE_MSI_INTR0_MASK 0x82C
46 #define PCIE_MSI_INTR0_STATUS 0x830
47
48 #define PCIE_ATU_VIEWPORT 0x900
49 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53 #define PCIE_ATU_CR1 0x904
54 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
55 #define PCIE_ATU_TYPE_IO (0x2 << 0)
56 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58 #define PCIE_ATU_CR2 0x908
59 #define PCIE_ATU_ENABLE (0x1 << 31)
60 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61 #define PCIE_ATU_LOWER_BASE 0x90C
62 #define PCIE_ATU_UPPER_BASE 0x910
63 #define PCIE_ATU_LIMIT 0x914
64 #define PCIE_ATU_LOWER_TARGET 0x918
65 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68 #define PCIE_ATU_UPPER_TARGET 0x91C
69
70 static struct hw_pci dw_pci;
71
72 static unsigned long global_io_offset;
73
74 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75 {
76 return sys->private_data;
77 }
78
79 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
80 {
81 *val = readl(addr);
82
83 if (size == 1)
84 *val = (*val >> (8 * (where & 3))) & 0xff;
85 else if (size == 2)
86 *val = (*val >> (8 * (where & 3))) & 0xffff;
87 else if (size != 4)
88 return PCIBIOS_BAD_REGISTER_NUMBER;
89
90 return PCIBIOS_SUCCESSFUL;
91 }
92
93 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
94 {
95 if (size == 4)
96 writel(val, addr);
97 else if (size == 2)
98 writew(val, addr + (where & 2));
99 else if (size == 1)
100 writeb(val, addr + (where & 3));
101 else
102 return PCIBIOS_BAD_REGISTER_NUMBER;
103
104 return PCIBIOS_SUCCESSFUL;
105 }
106
107 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
108 {
109 if (pp->ops->readl_rc)
110 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
111 else
112 *val = readl(pp->dbi_base + reg);
113 }
114
115 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
116 {
117 if (pp->ops->writel_rc)
118 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
119 else
120 writel(val, pp->dbi_base + reg);
121 }
122
123 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
124 u32 *val)
125 {
126 int ret;
127
128 if (pp->ops->rd_own_conf)
129 ret = pp->ops->rd_own_conf(pp, where, size, val);
130 else
131 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
132 size, val);
133
134 return ret;
135 }
136
137 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
138 u32 val)
139 {
140 int ret;
141
142 if (pp->ops->wr_own_conf)
143 ret = pp->ops->wr_own_conf(pp, where, size, val);
144 else
145 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
146 size, val);
147
148 return ret;
149 }
150
151 static struct irq_chip dw_msi_irq_chip = {
152 .name = "PCI-MSI",
153 .irq_enable = unmask_msi_irq,
154 .irq_disable = mask_msi_irq,
155 .irq_mask = mask_msi_irq,
156 .irq_unmask = unmask_msi_irq,
157 };
158
159 /* MSI int handler */
160 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
161 {
162 unsigned long val;
163 int i, pos, irq;
164 irqreturn_t ret = IRQ_NONE;
165
166 for (i = 0; i < MAX_MSI_CTRLS; i++) {
167 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
168 (u32 *)&val);
169 if (val) {
170 ret = IRQ_HANDLED;
171 pos = 0;
172 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
173 irq = irq_find_mapping(pp->irq_domain,
174 i * 32 + pos);
175 dw_pcie_wr_own_conf(pp,
176 PCIE_MSI_INTR0_STATUS + i * 12,
177 4, 1 << pos);
178 generic_handle_irq(irq);
179 pos++;
180 }
181 }
182 }
183
184 return ret;
185 }
186
187 void dw_pcie_msi_init(struct pcie_port *pp)
188 {
189 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
190
191 /* program the msi_data */
192 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
193 virt_to_phys((void *)pp->msi_data));
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
195 }
196
197 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
198 {
199 int flag = 1;
200
201 do {
202 pos = find_next_zero_bit(pp->msi_irq_in_use,
203 MAX_MSI_IRQS, pos);
204 /*if you have reached to the end then get out from here.*/
205 if (pos == MAX_MSI_IRQS)
206 return -ENOSPC;
207 /*
208 * Check if this position is at correct offset.nvec is always a
209 * power of two. pos0 must be nvec bit aligned.
210 */
211 if (pos % msgvec)
212 pos += msgvec - (pos % msgvec);
213 else
214 flag = 0;
215 } while (flag);
216
217 *pos0 = pos;
218 return 0;
219 }
220
221 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
222 {
223 unsigned int res, bit, val;
224
225 res = (irq / 32) * 12;
226 bit = irq % 32;
227 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
228 val &= ~(1 << bit);
229 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
230 }
231
232 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
233 unsigned int nvec, unsigned int pos)
234 {
235 unsigned int i;
236
237 for (i = 0; i < nvec; i++) {
238 irq_set_msi_desc_off(irq_base, i, NULL);
239 clear_bit(pos + i, pp->msi_irq_in_use);
240 /* Disable corresponding interrupt on MSI controller */
241 if (pp->ops->msi_clear_irq)
242 pp->ops->msi_clear_irq(pp, pos + i);
243 else
244 dw_pcie_msi_clear_irq(pp, pos + i);
245 }
246 }
247
248 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
249 {
250 unsigned int res, bit, val;
251
252 res = (irq / 32) * 12;
253 bit = irq % 32;
254 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
255 val |= 1 << bit;
256 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
257 }
258
259 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
260 {
261 int irq, pos0, pos1, i;
262 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
263
264 if (!pp) {
265 BUG();
266 return -EINVAL;
267 }
268
269 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
270 MAX_MSI_IRQS);
271 if (pos0 % no_irqs) {
272 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
273 goto no_valid_irq;
274 }
275 if (no_irqs > 1) {
276 pos1 = find_next_bit(pp->msi_irq_in_use,
277 MAX_MSI_IRQS, pos0);
278 /* there must be nvec number of consecutive free bits */
279 while ((pos1 - pos0) < no_irqs) {
280 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
281 goto no_valid_irq;
282 pos1 = find_next_bit(pp->msi_irq_in_use,
283 MAX_MSI_IRQS, pos0);
284 }
285 }
286
287 irq = irq_find_mapping(pp->irq_domain, pos0);
288 if (!irq)
289 goto no_valid_irq;
290
291 /*
292 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
293 * descs so there is no need to allocate descs here. We can therefore
294 * assume that if irq_find_mapping above returns non-zero, then the
295 * descs are also successfully allocated.
296 */
297
298 for (i = 0; i < no_irqs; i++) {
299 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
300 clear_irq_range(pp, irq, i, pos0);
301 goto no_valid_irq;
302 }
303 set_bit(pos0 + i, pp->msi_irq_in_use);
304 /*Enable corresponding interrupt in MSI interrupt controller */
305 if (pp->ops->msi_set_irq)
306 pp->ops->msi_set_irq(pp, pos0 + i);
307 else
308 dw_pcie_msi_set_irq(pp, pos0 + i);
309 }
310
311 *pos = pos0;
312 return irq;
313
314 no_valid_irq:
315 *pos = pos0;
316 return -ENOSPC;
317 }
318
319 static void clear_irq(unsigned int irq)
320 {
321 unsigned int pos, nvec;
322 struct msi_desc *msi;
323 struct pcie_port *pp;
324 struct irq_data *data = irq_get_irq_data(irq);
325
326 /* get the port structure */
327 msi = irq_data_get_msi(data);
328 pp = sys_to_pcie(msi->dev->bus->sysdata);
329 if (!pp) {
330 BUG();
331 return;
332 }
333
334 /* undo what was done in assign_irq */
335 pos = data->hwirq;
336 nvec = 1 << msi->msi_attrib.multiple;
337
338 clear_irq_range(pp, irq, nvec, pos);
339
340 /* all irqs cleared; reset attributes */
341 msi->irq = 0;
342 msi->msi_attrib.multiple = 0;
343 }
344
345 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
346 struct msi_desc *desc)
347 {
348 int irq, pos, msgvec;
349 u16 msg_ctr;
350 struct msi_msg msg;
351 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
352
353 if (!pp) {
354 BUG();
355 return -EINVAL;
356 }
357
358 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
359 &msg_ctr);
360 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
361 if (msgvec == 0)
362 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
363 if (msgvec > 5)
364 msgvec = 0;
365
366 irq = assign_irq((1 << msgvec), desc, &pos);
367 if (irq < 0)
368 return irq;
369
370 /*
371 * write_msi_msg() will update PCI_MSI_FLAGS so there is
372 * no need to explicitly call pci_write_config_word().
373 */
374 desc->msi_attrib.multiple = msgvec;
375
376 if (pp->ops->get_msi_data)
377 msg.address_lo = pp->ops->get_msi_data(pp);
378 else
379 msg.address_lo = virt_to_phys((void *)pp->msi_data);
380 msg.address_hi = 0x0;
381 msg.data = pos;
382 write_msi_msg(irq, &msg);
383
384 return 0;
385 }
386
387 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
388 {
389 clear_irq(irq);
390 }
391
392 static struct msi_chip dw_pcie_msi_chip = {
393 .setup_irq = dw_msi_setup_irq,
394 .teardown_irq = dw_msi_teardown_irq,
395 };
396
397 int dw_pcie_link_up(struct pcie_port *pp)
398 {
399 if (pp->ops->link_up)
400 return pp->ops->link_up(pp);
401 else
402 return 0;
403 }
404
405 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
406 irq_hw_number_t hwirq)
407 {
408 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
409 irq_set_chip_data(irq, domain->host_data);
410 set_irq_flags(irq, IRQF_VALID);
411
412 return 0;
413 }
414
415 static const struct irq_domain_ops msi_domain_ops = {
416 .map = dw_pcie_msi_map,
417 };
418
419 int __init dw_pcie_host_init(struct pcie_port *pp)
420 {
421 struct device_node *np = pp->dev->of_node;
422 struct platform_device *pdev = to_platform_device(pp->dev);
423 struct of_pci_range range;
424 struct of_pci_range_parser parser;
425 struct resource *cfg_res;
426 u32 val, na, ns;
427 const __be32 *addrp;
428 int i, index, ret;
429
430 /* Find the address cell size and the number of cells in order to get
431 * the untranslated address.
432 */
433 of_property_read_u32(np, "#address-cells", &na);
434 ns = of_n_size_cells(np);
435
436 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
437 if (cfg_res) {
438 pp->config.cfg0_size = resource_size(cfg_res)/2;
439 pp->config.cfg1_size = resource_size(cfg_res)/2;
440 pp->cfg0_base = cfg_res->start;
441 pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
442
443 /* Find the untranslated configuration space address */
444 index = of_property_match_string(np, "reg-names", "config");
445 addrp = of_get_address(np, index, false, false);
446 pp->cfg0_mod_base = of_read_number(addrp, ns);
447 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->config.cfg0_size;
448 } else {
449 dev_err(pp->dev, "missing *config* reg space\n");
450 }
451
452 if (of_pci_range_parser_init(&parser, np)) {
453 dev_err(pp->dev, "missing ranges property\n");
454 return -EINVAL;
455 }
456
457 /* Get the I/O and memory ranges from DT */
458 for_each_of_pci_range(&parser, &range) {
459 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
460 if (restype == IORESOURCE_IO) {
461 of_pci_range_to_resource(&range, np, &pp->io);
462 pp->io.name = "I/O";
463 pp->io.start = max_t(resource_size_t,
464 PCIBIOS_MIN_IO,
465 range.pci_addr + global_io_offset);
466 pp->io.end = min_t(resource_size_t,
467 IO_SPACE_LIMIT,
468 range.pci_addr + range.size
469 + global_io_offset);
470 pp->config.io_size = resource_size(&pp->io);
471 pp->config.io_bus_addr = range.pci_addr;
472 pp->io_base = range.cpu_addr;
473
474 /* Find the untranslated IO space address */
475 pp->io_mod_base = of_read_number(parser.range -
476 parser.np + na, ns);
477 }
478 if (restype == IORESOURCE_MEM) {
479 of_pci_range_to_resource(&range, np, &pp->mem);
480 pp->mem.name = "MEM";
481 pp->config.mem_size = resource_size(&pp->mem);
482 pp->config.mem_bus_addr = range.pci_addr;
483
484 /* Find the untranslated MEM space address */
485 pp->mem_mod_base = of_read_number(parser.range -
486 parser.np + na, ns);
487 }
488 if (restype == 0) {
489 of_pci_range_to_resource(&range, np, &pp->cfg);
490 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
491 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
492 pp->cfg0_base = pp->cfg.start;
493 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
494
495 /* Find the untranslated configuration space address */
496 pp->cfg0_mod_base = of_read_number(parser.range -
497 parser.np + na, ns);
498 pp->cfg1_mod_base = pp->cfg0_mod_base +
499 pp->config.cfg0_size;
500 }
501 }
502
503 ret = of_pci_parse_bus_range(np, &pp->busn);
504 if (ret < 0) {
505 pp->busn.name = np->name;
506 pp->busn.start = 0;
507 pp->busn.end = 0xff;
508 pp->busn.flags = IORESOURCE_BUS;
509 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
510 ret, &pp->busn);
511 }
512
513 if (!pp->dbi_base) {
514 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
515 resource_size(&pp->cfg));
516 if (!pp->dbi_base) {
517 dev_err(pp->dev, "error with ioremap\n");
518 return -ENOMEM;
519 }
520 }
521
522 pp->mem_base = pp->mem.start;
523
524 if (!pp->va_cfg0_base) {
525 pp->cfg0_base = pp->cfg.start;
526 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
527 pp->config.cfg0_size);
528 if (!pp->va_cfg0_base) {
529 dev_err(pp->dev, "error with ioremap in function\n");
530 return -ENOMEM;
531 }
532 }
533
534 if (!pp->va_cfg1_base) {
535 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
536 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
537 pp->config.cfg1_size);
538 if (!pp->va_cfg1_base) {
539 dev_err(pp->dev, "error with ioremap\n");
540 return -ENOMEM;
541 }
542 }
543
544 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
545 dev_err(pp->dev, "Failed to parse the number of lanes\n");
546 return -EINVAL;
547 }
548
549 if (IS_ENABLED(CONFIG_PCI_MSI)) {
550 if (!pp->ops->msi_host_init) {
551 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
552 MAX_MSI_IRQS, &msi_domain_ops,
553 &dw_pcie_msi_chip);
554 if (!pp->irq_domain) {
555 dev_err(pp->dev, "irq domain init failed\n");
556 return -ENXIO;
557 }
558
559 for (i = 0; i < MAX_MSI_IRQS; i++)
560 irq_create_mapping(pp->irq_domain, i);
561 } else {
562 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
563 if (ret < 0)
564 return ret;
565 }
566 }
567
568 if (pp->ops->host_init)
569 pp->ops->host_init(pp);
570
571 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
572
573 /* program correct class for RC */
574 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
575
576 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
577 val |= PORT_LOGIC_SPEED_CHANGE;
578 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
579
580 dw_pci.nr_controllers = 1;
581 dw_pci.private_data = (void **)&pp;
582
583 pci_common_init_dev(pp->dev, &dw_pci);
584 pci_assign_unassigned_resources();
585 #ifdef CONFIG_PCI_DOMAINS
586 dw_pci.domain++;
587 #endif
588
589 return 0;
590 }
591
592 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
593 {
594 /* Program viewport 0 : OUTBOUND : CFG0 */
595 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
596 PCIE_ATU_VIEWPORT);
597 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
598 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
599 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->config.cfg0_size - 1,
600 PCIE_ATU_LIMIT);
601 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
602 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
603 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
604 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
605 }
606
607 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
608 {
609 /* Program viewport 1 : OUTBOUND : CFG1 */
610 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
611 PCIE_ATU_VIEWPORT);
612 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
613 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
614 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
615 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->config.cfg1_size - 1,
616 PCIE_ATU_LIMIT);
617 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
618 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
619 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
620 }
621
622 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
623 {
624 /* Program viewport 0 : OUTBOUND : MEM */
625 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
626 PCIE_ATU_VIEWPORT);
627 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
628 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
629 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
630 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->config.mem_size - 1,
631 PCIE_ATU_LIMIT);
632 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
633 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
634 PCIE_ATU_UPPER_TARGET);
635 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
636 }
637
638 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
639 {
640 /* Program viewport 1 : OUTBOUND : IO */
641 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
642 PCIE_ATU_VIEWPORT);
643 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
644 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
645 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
646 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->config.io_size - 1,
647 PCIE_ATU_LIMIT);
648 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
649 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
650 PCIE_ATU_UPPER_TARGET);
651 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
652 }
653
654 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
655 u32 devfn, int where, int size, u32 *val)
656 {
657 int ret = PCIBIOS_SUCCESSFUL;
658 u32 address, busdev;
659
660 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
661 PCIE_ATU_FUNC(PCI_FUNC(devfn));
662 address = where & ~0x3;
663
664 if (bus->parent->number == pp->root_bus_nr) {
665 dw_pcie_prog_viewport_cfg0(pp, busdev);
666 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
667 val);
668 dw_pcie_prog_viewport_mem_outbound(pp);
669 } else {
670 dw_pcie_prog_viewport_cfg1(pp, busdev);
671 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
672 val);
673 dw_pcie_prog_viewport_io_outbound(pp);
674 }
675
676 return ret;
677 }
678
679 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
680 u32 devfn, int where, int size, u32 val)
681 {
682 int ret = PCIBIOS_SUCCESSFUL;
683 u32 address, busdev;
684
685 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
686 PCIE_ATU_FUNC(PCI_FUNC(devfn));
687 address = where & ~0x3;
688
689 if (bus->parent->number == pp->root_bus_nr) {
690 dw_pcie_prog_viewport_cfg0(pp, busdev);
691 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
692 val);
693 dw_pcie_prog_viewport_mem_outbound(pp);
694 } else {
695 dw_pcie_prog_viewport_cfg1(pp, busdev);
696 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
697 val);
698 dw_pcie_prog_viewport_io_outbound(pp);
699 }
700
701 return ret;
702 }
703
704 static int dw_pcie_valid_config(struct pcie_port *pp,
705 struct pci_bus *bus, int dev)
706 {
707 /* If there is no link, then there is no device */
708 if (bus->number != pp->root_bus_nr) {
709 if (!dw_pcie_link_up(pp))
710 return 0;
711 }
712
713 /* access only one slot on each root port */
714 if (bus->number == pp->root_bus_nr && dev > 0)
715 return 0;
716
717 /*
718 * do not read more than one device on the bus directly attached
719 * to RC's (Virtual Bridge's) DS side.
720 */
721 if (bus->primary == pp->root_bus_nr && dev > 0)
722 return 0;
723
724 return 1;
725 }
726
727 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
728 int size, u32 *val)
729 {
730 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
731 int ret;
732
733 if (!pp) {
734 BUG();
735 return -EINVAL;
736 }
737
738 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
739 *val = 0xffffffff;
740 return PCIBIOS_DEVICE_NOT_FOUND;
741 }
742
743 if (bus->number != pp->root_bus_nr)
744 if (pp->ops->rd_other_conf)
745 ret = pp->ops->rd_other_conf(pp, bus, devfn,
746 where, size, val);
747 else
748 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
749 where, size, val);
750 else
751 ret = dw_pcie_rd_own_conf(pp, where, size, val);
752
753 return ret;
754 }
755
756 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
757 int where, int size, u32 val)
758 {
759 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
760 int ret;
761
762 if (!pp) {
763 BUG();
764 return -EINVAL;
765 }
766
767 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
768 return PCIBIOS_DEVICE_NOT_FOUND;
769
770 if (bus->number != pp->root_bus_nr)
771 if (pp->ops->wr_other_conf)
772 ret = pp->ops->wr_other_conf(pp, bus, devfn,
773 where, size, val);
774 else
775 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
776 where, size, val);
777 else
778 ret = dw_pcie_wr_own_conf(pp, where, size, val);
779
780 return ret;
781 }
782
783 static struct pci_ops dw_pcie_ops = {
784 .read = dw_pcie_rd_conf,
785 .write = dw_pcie_wr_conf,
786 };
787
788 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
789 {
790 struct pcie_port *pp;
791
792 pp = sys_to_pcie(sys);
793
794 if (!pp)
795 return 0;
796
797 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
798 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
799 pci_ioremap_io(global_io_offset, pp->io_base);
800 global_io_offset += SZ_64K;
801 pci_add_resource_offset(&sys->resources, &pp->io,
802 sys->io_offset);
803 }
804
805 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
806 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
807 pci_add_resource(&sys->resources, &pp->busn);
808
809 return 1;
810 }
811
812 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
813 {
814 struct pci_bus *bus;
815 struct pcie_port *pp = sys_to_pcie(sys);
816
817 if (pp) {
818 pp->root_bus_nr = sys->busnr;
819 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
820 sys, &sys->resources);
821 } else {
822 bus = NULL;
823 BUG();
824 }
825
826 if (bus && pp->ops->scan_bus)
827 pp->ops->scan_bus(pp);
828
829 return bus;
830 }
831
832 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
833 {
834 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
835 int irq;
836
837 irq = of_irq_parse_and_map_pci(dev, slot, pin);
838 if (!irq)
839 irq = pp->irq;
840
841 return irq;
842 }
843
844 static void dw_pcie_add_bus(struct pci_bus *bus)
845 {
846 if (IS_ENABLED(CONFIG_PCI_MSI)) {
847 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
848
849 dw_pcie_msi_chip.dev = pp->dev;
850 bus->msi = &dw_pcie_msi_chip;
851 }
852 }
853
854 static struct hw_pci dw_pci = {
855 .setup = dw_pcie_setup,
856 .scan = dw_pcie_scan_bus,
857 .map_irq = dw_pcie_map_irq,
858 .add_bus = dw_pcie_add_bus,
859 };
860
861 void dw_pcie_setup_rc(struct pcie_port *pp)
862 {
863 struct pcie_port_info *config = &pp->config;
864 u32 val;
865 u32 membase;
866 u32 memlimit;
867
868 /* set the number of lanes */
869 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
870 val &= ~PORT_LINK_MODE_MASK;
871 switch (pp->lanes) {
872 case 1:
873 val |= PORT_LINK_MODE_1_LANES;
874 break;
875 case 2:
876 val |= PORT_LINK_MODE_2_LANES;
877 break;
878 case 4:
879 val |= PORT_LINK_MODE_4_LANES;
880 break;
881 }
882 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
883
884 /* set link width speed control register */
885 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
886 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
887 switch (pp->lanes) {
888 case 1:
889 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
890 break;
891 case 2:
892 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
893 break;
894 case 4:
895 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
896 break;
897 }
898 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
899
900 /* setup RC BARs */
901 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
902 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
903
904 /* setup interrupt pins */
905 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
906 val &= 0xffff00ff;
907 val |= 0x00000100;
908 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
909
910 /* setup bus numbers */
911 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
912 val &= 0xff000000;
913 val |= 0x00010100;
914 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
915
916 /* setup memory base, memory limit */
917 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
918 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
919 val = memlimit | membase;
920 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
921
922 /* setup command register */
923 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
924 val &= 0xffff0000;
925 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
926 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
927 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
928 }
929
930 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
931 MODULE_DESCRIPTION("Designware PCIe host controller driver");
932 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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