2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
26 #include "pcie-designware.h"
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
35 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
38 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
42 #define PCIE_MSI_ADDR_LO 0x820
43 #define PCIE_MSI_ADDR_HI 0x824
44 #define PCIE_MSI_INTR0_ENABLE 0x828
45 #define PCIE_MSI_INTR0_MASK 0x82C
46 #define PCIE_MSI_INTR0_STATUS 0x830
48 #define PCIE_ATU_VIEWPORT 0x900
49 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53 #define PCIE_ATU_CR1 0x904
54 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
55 #define PCIE_ATU_TYPE_IO (0x2 << 0)
56 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58 #define PCIE_ATU_CR2 0x908
59 #define PCIE_ATU_ENABLE (0x1 << 31)
60 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61 #define PCIE_ATU_LOWER_BASE 0x90C
62 #define PCIE_ATU_UPPER_BASE 0x910
63 #define PCIE_ATU_LIMIT 0x914
64 #define PCIE_ATU_LOWER_TARGET 0x918
65 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68 #define PCIE_ATU_UPPER_TARGET 0x91C
70 static struct hw_pci dw_pci
;
72 static unsigned long global_io_offset
;
74 static inline struct pcie_port
*sys_to_pcie(struct pci_sys_data
*sys
)
76 return sys
->private_data
;
79 int dw_pcie_cfg_read(void __iomem
*addr
, int where
, int size
, u32
*val
)
84 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
86 *val
= (*val
>> (8 * (where
& 3))) & 0xffff;
88 return PCIBIOS_BAD_REGISTER_NUMBER
;
90 return PCIBIOS_SUCCESSFUL
;
93 int dw_pcie_cfg_write(void __iomem
*addr
, int where
, int size
, u32 val
)
98 writew(val
, addr
+ (where
& 2));
100 writeb(val
, addr
+ (where
& 3));
102 return PCIBIOS_BAD_REGISTER_NUMBER
;
104 return PCIBIOS_SUCCESSFUL
;
107 static inline void dw_pcie_readl_rc(struct pcie_port
*pp
, u32 reg
, u32
*val
)
109 if (pp
->ops
->readl_rc
)
110 pp
->ops
->readl_rc(pp
, pp
->dbi_base
+ reg
, val
);
112 *val
= readl(pp
->dbi_base
+ reg
);
115 static inline void dw_pcie_writel_rc(struct pcie_port
*pp
, u32 val
, u32 reg
)
117 if (pp
->ops
->writel_rc
)
118 pp
->ops
->writel_rc(pp
, val
, pp
->dbi_base
+ reg
);
120 writel(val
, pp
->dbi_base
+ reg
);
123 static int dw_pcie_rd_own_conf(struct pcie_port
*pp
, int where
, int size
,
128 if (pp
->ops
->rd_own_conf
)
129 ret
= pp
->ops
->rd_own_conf(pp
, where
, size
, val
);
131 ret
= dw_pcie_cfg_read(pp
->dbi_base
+ (where
& ~0x3), where
,
137 static int dw_pcie_wr_own_conf(struct pcie_port
*pp
, int where
, int size
,
142 if (pp
->ops
->wr_own_conf
)
143 ret
= pp
->ops
->wr_own_conf(pp
, where
, size
, val
);
145 ret
= dw_pcie_cfg_write(pp
->dbi_base
+ (where
& ~0x3), where
,
151 static struct irq_chip dw_msi_irq_chip
= {
153 .irq_enable
= unmask_msi_irq
,
154 .irq_disable
= mask_msi_irq
,
155 .irq_mask
= mask_msi_irq
,
156 .irq_unmask
= unmask_msi_irq
,
159 /* MSI int handler */
160 irqreturn_t
dw_handle_msi_irq(struct pcie_port
*pp
)
164 irqreturn_t ret
= IRQ_NONE
;
166 for (i
= 0; i
< MAX_MSI_CTRLS
; i
++) {
167 dw_pcie_rd_own_conf(pp
, PCIE_MSI_INTR0_STATUS
+ i
* 12, 4,
172 while ((pos
= find_next_bit(&val
, 32, pos
)) != 32) {
173 irq
= irq_find_mapping(pp
->irq_domain
,
175 dw_pcie_wr_own_conf(pp
,
176 PCIE_MSI_INTR0_STATUS
+ i
* 12,
178 generic_handle_irq(irq
);
187 void dw_pcie_msi_init(struct pcie_port
*pp
)
189 pp
->msi_data
= __get_free_pages(GFP_KERNEL
, 0);
191 /* program the msi_data */
192 dw_pcie_wr_own_conf(pp
, PCIE_MSI_ADDR_LO
, 4,
193 virt_to_phys((void *)pp
->msi_data
));
194 dw_pcie_wr_own_conf(pp
, PCIE_MSI_ADDR_HI
, 4, 0);
197 static int find_valid_pos0(struct pcie_port
*pp
, int msgvec
, int pos
, int *pos0
)
202 pos
= find_next_zero_bit(pp
->msi_irq_in_use
,
204 /*if you have reached to the end then get out from here.*/
205 if (pos
== MAX_MSI_IRQS
)
208 * Check if this position is at correct offset.nvec is always a
209 * power of two. pos0 must be nvec bit aligned.
212 pos
+= msgvec
- (pos
% msgvec
);
221 static void dw_pcie_msi_clear_irq(struct pcie_port
*pp
, int irq
)
223 unsigned int res
, bit
, val
;
225 res
= (irq
/ 32) * 12;
227 dw_pcie_rd_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, &val
);
229 dw_pcie_wr_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, val
);
232 static void clear_irq_range(struct pcie_port
*pp
, unsigned int irq_base
,
233 unsigned int nvec
, unsigned int pos
)
237 for (i
= 0; i
< nvec
; i
++) {
238 irq_set_msi_desc_off(irq_base
, i
, NULL
);
239 clear_bit(pos
+ i
, pp
->msi_irq_in_use
);
240 /* Disable corresponding interrupt on MSI controller */
241 if (pp
->ops
->msi_clear_irq
)
242 pp
->ops
->msi_clear_irq(pp
, pos
+ i
);
244 dw_pcie_msi_clear_irq(pp
, pos
+ i
);
248 static void dw_pcie_msi_set_irq(struct pcie_port
*pp
, int irq
)
250 unsigned int res
, bit
, val
;
252 res
= (irq
/ 32) * 12;
254 dw_pcie_rd_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, &val
);
256 dw_pcie_wr_own_conf(pp
, PCIE_MSI_INTR0_ENABLE
+ res
, 4, val
);
259 static int assign_irq(int no_irqs
, struct msi_desc
*desc
, int *pos
)
261 int irq
, pos0
, pos1
, i
;
262 struct pcie_port
*pp
= sys_to_pcie(desc
->dev
->bus
->sysdata
);
269 pos0
= find_first_zero_bit(pp
->msi_irq_in_use
,
271 if (pos0
% no_irqs
) {
272 if (find_valid_pos0(pp
, no_irqs
, pos0
, &pos0
))
276 pos1
= find_next_bit(pp
->msi_irq_in_use
,
278 /* there must be nvec number of consecutive free bits */
279 while ((pos1
- pos0
) < no_irqs
) {
280 if (find_valid_pos0(pp
, no_irqs
, pos1
, &pos0
))
282 pos1
= find_next_bit(pp
->msi_irq_in_use
,
287 irq
= irq_find_mapping(pp
->irq_domain
, pos0
);
292 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
293 * descs so there is no need to allocate descs here. We can therefore
294 * assume that if irq_find_mapping above returns non-zero, then the
295 * descs are also successfully allocated.
298 for (i
= 0; i
< no_irqs
; i
++) {
299 if (irq_set_msi_desc_off(irq
, i
, desc
) != 0) {
300 clear_irq_range(pp
, irq
, i
, pos0
);
303 set_bit(pos0
+ i
, pp
->msi_irq_in_use
);
304 /*Enable corresponding interrupt in MSI interrupt controller */
305 if (pp
->ops
->msi_set_irq
)
306 pp
->ops
->msi_set_irq(pp
, pos0
+ i
);
308 dw_pcie_msi_set_irq(pp
, pos0
+ i
);
319 static void clear_irq(unsigned int irq
)
321 unsigned int pos
, nvec
;
322 struct msi_desc
*msi
;
323 struct pcie_port
*pp
;
324 struct irq_data
*data
= irq_get_irq_data(irq
);
326 /* get the port structure */
327 msi
= irq_data_get_msi(data
);
328 pp
= sys_to_pcie(msi
->dev
->bus
->sysdata
);
334 /* undo what was done in assign_irq */
336 nvec
= 1 << msi
->msi_attrib
.multiple
;
338 clear_irq_range(pp
, irq
, nvec
, pos
);
340 /* all irqs cleared; reset attributes */
342 msi
->msi_attrib
.multiple
= 0;
345 static int dw_msi_setup_irq(struct msi_chip
*chip
, struct pci_dev
*pdev
,
346 struct msi_desc
*desc
)
348 int irq
, pos
, msgvec
;
351 struct pcie_port
*pp
= sys_to_pcie(pdev
->bus
->sysdata
);
358 pci_read_config_word(pdev
, desc
->msi_attrib
.pos
+PCI_MSI_FLAGS
,
360 msgvec
= (msg_ctr
&PCI_MSI_FLAGS_QSIZE
) >> 4;
362 msgvec
= (msg_ctr
& PCI_MSI_FLAGS_QMASK
) >> 1;
366 irq
= assign_irq((1 << msgvec
), desc
, &pos
);
371 * write_msi_msg() will update PCI_MSI_FLAGS so there is
372 * no need to explicitly call pci_write_config_word().
374 desc
->msi_attrib
.multiple
= msgvec
;
376 if (pp
->ops
->get_msi_data
)
377 msg
.address_lo
= pp
->ops
->get_msi_data(pp
);
379 msg
.address_lo
= virt_to_phys((void *)pp
->msi_data
);
380 msg
.address_hi
= 0x0;
382 write_msi_msg(irq
, &msg
);
387 static void dw_msi_teardown_irq(struct msi_chip
*chip
, unsigned int irq
)
392 static struct msi_chip dw_pcie_msi_chip
= {
393 .setup_irq
= dw_msi_setup_irq
,
394 .teardown_irq
= dw_msi_teardown_irq
,
397 int dw_pcie_link_up(struct pcie_port
*pp
)
399 if (pp
->ops
->link_up
)
400 return pp
->ops
->link_up(pp
);
405 static int dw_pcie_msi_map(struct irq_domain
*domain
, unsigned int irq
,
406 irq_hw_number_t hwirq
)
408 irq_set_chip_and_handler(irq
, &dw_msi_irq_chip
, handle_simple_irq
);
409 irq_set_chip_data(irq
, domain
->host_data
);
410 set_irq_flags(irq
, IRQF_VALID
);
415 static const struct irq_domain_ops msi_domain_ops
= {
416 .map
= dw_pcie_msi_map
,
419 int __init
dw_pcie_host_init(struct pcie_port
*pp
)
421 struct device_node
*np
= pp
->dev
->of_node
;
422 struct platform_device
*pdev
= to_platform_device(pp
->dev
);
423 struct of_pci_range range
;
424 struct of_pci_range_parser parser
;
425 struct resource
*cfg_res
;
430 /* Find the address cell size and the number of cells in order to get
431 * the untranslated address.
433 of_property_read_u32(np
, "#address-cells", &na
);
434 ns
= of_n_size_cells(np
);
436 cfg_res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "config");
438 pp
->config
.cfg0_size
= resource_size(cfg_res
)/2;
439 pp
->config
.cfg1_size
= resource_size(cfg_res
)/2;
440 pp
->cfg0_base
= cfg_res
->start
;
441 pp
->cfg1_base
= cfg_res
->start
+ pp
->config
.cfg0_size
;
443 /* Find the untranslated configuration space address */
444 index
= of_property_match_string(np
, "reg-names", "config");
445 addrp
= of_get_address(np
, index
, false, false);
446 pp
->cfg0_mod_base
= of_read_number(addrp
, ns
);
447 pp
->cfg1_mod_base
= pp
->cfg0_mod_base
+ pp
->config
.cfg0_size
;
449 dev_err(pp
->dev
, "missing *config* reg space\n");
452 if (of_pci_range_parser_init(&parser
, np
)) {
453 dev_err(pp
->dev
, "missing ranges property\n");
457 /* Get the I/O and memory ranges from DT */
458 for_each_of_pci_range(&parser
, &range
) {
459 unsigned long restype
= range
.flags
& IORESOURCE_TYPE_BITS
;
460 if (restype
== IORESOURCE_IO
) {
461 of_pci_range_to_resource(&range
, np
, &pp
->io
);
463 pp
->io
.start
= max_t(resource_size_t
,
465 range
.pci_addr
+ global_io_offset
);
466 pp
->io
.end
= min_t(resource_size_t
,
468 range
.pci_addr
+ range
.size
470 pp
->config
.io_size
= resource_size(&pp
->io
);
471 pp
->config
.io_bus_addr
= range
.pci_addr
;
472 pp
->io_base
= range
.cpu_addr
;
474 /* Find the untranslated IO space address */
475 pp
->io_mod_base
= of_read_number(parser
.range
-
478 if (restype
== IORESOURCE_MEM
) {
479 of_pci_range_to_resource(&range
, np
, &pp
->mem
);
480 pp
->mem
.name
= "MEM";
481 pp
->config
.mem_size
= resource_size(&pp
->mem
);
482 pp
->config
.mem_bus_addr
= range
.pci_addr
;
484 /* Find the untranslated MEM space address */
485 pp
->mem_mod_base
= of_read_number(parser
.range
-
489 of_pci_range_to_resource(&range
, np
, &pp
->cfg
);
490 pp
->config
.cfg0_size
= resource_size(&pp
->cfg
)/2;
491 pp
->config
.cfg1_size
= resource_size(&pp
->cfg
)/2;
492 pp
->cfg0_base
= pp
->cfg
.start
;
493 pp
->cfg1_base
= pp
->cfg
.start
+ pp
->config
.cfg0_size
;
495 /* Find the untranslated configuration space address */
496 pp
->cfg0_mod_base
= of_read_number(parser
.range
-
498 pp
->cfg1_mod_base
= pp
->cfg0_mod_base
+
499 pp
->config
.cfg0_size
;
504 pp
->dbi_base
= devm_ioremap(pp
->dev
, pp
->cfg
.start
,
505 resource_size(&pp
->cfg
));
507 dev_err(pp
->dev
, "error with ioremap\n");
512 pp
->mem_base
= pp
->mem
.start
;
514 pp
->va_cfg0_base
= devm_ioremap(pp
->dev
, pp
->cfg0_base
,
515 pp
->config
.cfg0_size
);
516 if (!pp
->va_cfg0_base
) {
517 dev_err(pp
->dev
, "error with ioremap in function\n");
520 pp
->va_cfg1_base
= devm_ioremap(pp
->dev
, pp
->cfg1_base
,
521 pp
->config
.cfg1_size
);
522 if (!pp
->va_cfg1_base
) {
523 dev_err(pp
->dev
, "error with ioremap\n");
527 if (of_property_read_u32(np
, "num-lanes", &pp
->lanes
)) {
528 dev_err(pp
->dev
, "Failed to parse the number of lanes\n");
532 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
533 pp
->irq_domain
= irq_domain_add_linear(pp
->dev
->of_node
,
534 MAX_MSI_IRQS
, &msi_domain_ops
,
536 if (!pp
->irq_domain
) {
537 dev_err(pp
->dev
, "irq domain init failed\n");
541 for (i
= 0; i
< MAX_MSI_IRQS
; i
++)
542 irq_create_mapping(pp
->irq_domain
, i
);
545 if (pp
->ops
->host_init
)
546 pp
->ops
->host_init(pp
);
548 dw_pcie_wr_own_conf(pp
, PCI_BASE_ADDRESS_0
, 4, 0);
550 /* program correct class for RC */
551 dw_pcie_wr_own_conf(pp
, PCI_CLASS_DEVICE
, 2, PCI_CLASS_BRIDGE_PCI
);
553 dw_pcie_rd_own_conf(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, 4, &val
);
554 val
|= PORT_LOGIC_SPEED_CHANGE
;
555 dw_pcie_wr_own_conf(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, 4, val
);
557 dw_pci
.nr_controllers
= 1;
558 dw_pci
.private_data
= (void **)&pp
;
560 pci_common_init_dev(pp
->dev
, &dw_pci
);
561 pci_assign_unassigned_resources();
562 #ifdef CONFIG_PCI_DOMAINS
569 static void dw_pcie_prog_viewport_cfg0(struct pcie_port
*pp
, u32 busdev
)
571 /* Program viewport 0 : OUTBOUND : CFG0 */
572 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX0
,
574 dw_pcie_writel_rc(pp
, pp
->cfg0_mod_base
, PCIE_ATU_LOWER_BASE
);
575 dw_pcie_writel_rc(pp
, (pp
->cfg0_mod_base
>> 32), PCIE_ATU_UPPER_BASE
);
576 dw_pcie_writel_rc(pp
, pp
->cfg0_mod_base
+ pp
->config
.cfg0_size
- 1,
578 dw_pcie_writel_rc(pp
, busdev
, PCIE_ATU_LOWER_TARGET
);
579 dw_pcie_writel_rc(pp
, 0, PCIE_ATU_UPPER_TARGET
);
580 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_CFG0
, PCIE_ATU_CR1
);
581 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
584 static void dw_pcie_prog_viewport_cfg1(struct pcie_port
*pp
, u32 busdev
)
586 /* Program viewport 1 : OUTBOUND : CFG1 */
587 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX1
,
589 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_CFG1
, PCIE_ATU_CR1
);
590 dw_pcie_writel_rc(pp
, pp
->cfg1_mod_base
, PCIE_ATU_LOWER_BASE
);
591 dw_pcie_writel_rc(pp
, (pp
->cfg1_mod_base
>> 32), PCIE_ATU_UPPER_BASE
);
592 dw_pcie_writel_rc(pp
, pp
->cfg1_mod_base
+ pp
->config
.cfg1_size
- 1,
594 dw_pcie_writel_rc(pp
, busdev
, PCIE_ATU_LOWER_TARGET
);
595 dw_pcie_writel_rc(pp
, 0, PCIE_ATU_UPPER_TARGET
);
596 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
599 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port
*pp
)
601 /* Program viewport 0 : OUTBOUND : MEM */
602 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX0
,
604 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_MEM
, PCIE_ATU_CR1
);
605 dw_pcie_writel_rc(pp
, pp
->mem_mod_base
, PCIE_ATU_LOWER_BASE
);
606 dw_pcie_writel_rc(pp
, (pp
->mem_mod_base
>> 32), PCIE_ATU_UPPER_BASE
);
607 dw_pcie_writel_rc(pp
, pp
->mem_mod_base
+ pp
->config
.mem_size
- 1,
609 dw_pcie_writel_rc(pp
, pp
->config
.mem_bus_addr
, PCIE_ATU_LOWER_TARGET
);
610 dw_pcie_writel_rc(pp
, upper_32_bits(pp
->config
.mem_bus_addr
),
611 PCIE_ATU_UPPER_TARGET
);
612 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
615 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port
*pp
)
617 /* Program viewport 1 : OUTBOUND : IO */
618 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX1
,
620 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_IO
, PCIE_ATU_CR1
);
621 dw_pcie_writel_rc(pp
, pp
->io_mod_base
, PCIE_ATU_LOWER_BASE
);
622 dw_pcie_writel_rc(pp
, (pp
->io_mod_base
>> 32), PCIE_ATU_UPPER_BASE
);
623 dw_pcie_writel_rc(pp
, pp
->io_mod_base
+ pp
->config
.io_size
- 1,
625 dw_pcie_writel_rc(pp
, pp
->config
.io_bus_addr
, PCIE_ATU_LOWER_TARGET
);
626 dw_pcie_writel_rc(pp
, upper_32_bits(pp
->config
.io_bus_addr
),
627 PCIE_ATU_UPPER_TARGET
);
628 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
631 static int dw_pcie_rd_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
632 u32 devfn
, int where
, int size
, u32
*val
)
634 int ret
= PCIBIOS_SUCCESSFUL
;
637 busdev
= PCIE_ATU_BUS(bus
->number
) | PCIE_ATU_DEV(PCI_SLOT(devfn
)) |
638 PCIE_ATU_FUNC(PCI_FUNC(devfn
));
639 address
= where
& ~0x3;
641 if (bus
->parent
->number
== pp
->root_bus_nr
) {
642 dw_pcie_prog_viewport_cfg0(pp
, busdev
);
643 ret
= dw_pcie_cfg_read(pp
->va_cfg0_base
+ address
, where
, size
,
645 dw_pcie_prog_viewport_mem_outbound(pp
);
647 dw_pcie_prog_viewport_cfg1(pp
, busdev
);
648 ret
= dw_pcie_cfg_read(pp
->va_cfg1_base
+ address
, where
, size
,
650 dw_pcie_prog_viewport_io_outbound(pp
);
656 static int dw_pcie_wr_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
657 u32 devfn
, int where
, int size
, u32 val
)
659 int ret
= PCIBIOS_SUCCESSFUL
;
662 busdev
= PCIE_ATU_BUS(bus
->number
) | PCIE_ATU_DEV(PCI_SLOT(devfn
)) |
663 PCIE_ATU_FUNC(PCI_FUNC(devfn
));
664 address
= where
& ~0x3;
666 if (bus
->parent
->number
== pp
->root_bus_nr
) {
667 dw_pcie_prog_viewport_cfg0(pp
, busdev
);
668 ret
= dw_pcie_cfg_write(pp
->va_cfg0_base
+ address
, where
, size
,
670 dw_pcie_prog_viewport_mem_outbound(pp
);
672 dw_pcie_prog_viewport_cfg1(pp
, busdev
);
673 ret
= dw_pcie_cfg_write(pp
->va_cfg1_base
+ address
, where
, size
,
675 dw_pcie_prog_viewport_io_outbound(pp
);
681 static int dw_pcie_valid_config(struct pcie_port
*pp
,
682 struct pci_bus
*bus
, int dev
)
684 /* If there is no link, then there is no device */
685 if (bus
->number
!= pp
->root_bus_nr
) {
686 if (!dw_pcie_link_up(pp
))
690 /* access only one slot on each root port */
691 if (bus
->number
== pp
->root_bus_nr
&& dev
> 0)
695 * do not read more than one device on the bus directly attached
696 * to RC's (Virtual Bridge's) DS side.
698 if (bus
->primary
== pp
->root_bus_nr
&& dev
> 0)
704 static int dw_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
707 struct pcie_port
*pp
= sys_to_pcie(bus
->sysdata
);
715 if (dw_pcie_valid_config(pp
, bus
, PCI_SLOT(devfn
)) == 0) {
717 return PCIBIOS_DEVICE_NOT_FOUND
;
720 if (bus
->number
!= pp
->root_bus_nr
)
721 if (pp
->ops
->rd_other_conf
)
722 ret
= pp
->ops
->rd_other_conf(pp
, bus
, devfn
,
725 ret
= dw_pcie_rd_other_conf(pp
, bus
, devfn
,
728 ret
= dw_pcie_rd_own_conf(pp
, where
, size
, val
);
733 static int dw_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
734 int where
, int size
, u32 val
)
736 struct pcie_port
*pp
= sys_to_pcie(bus
->sysdata
);
744 if (dw_pcie_valid_config(pp
, bus
, PCI_SLOT(devfn
)) == 0)
745 return PCIBIOS_DEVICE_NOT_FOUND
;
747 if (bus
->number
!= pp
->root_bus_nr
)
748 if (pp
->ops
->wr_other_conf
)
749 ret
= pp
->ops
->wr_other_conf(pp
, bus
, devfn
,
752 ret
= dw_pcie_wr_other_conf(pp
, bus
, devfn
,
755 ret
= dw_pcie_wr_own_conf(pp
, where
, size
, val
);
760 static struct pci_ops dw_pcie_ops
= {
761 .read
= dw_pcie_rd_conf
,
762 .write
= dw_pcie_wr_conf
,
765 static int dw_pcie_setup(int nr
, struct pci_sys_data
*sys
)
767 struct pcie_port
*pp
;
769 pp
= sys_to_pcie(sys
);
774 if (global_io_offset
< SZ_1M
&& pp
->config
.io_size
> 0) {
775 sys
->io_offset
= global_io_offset
- pp
->config
.io_bus_addr
;
776 pci_ioremap_io(global_io_offset
, pp
->io_base
);
777 global_io_offset
+= SZ_64K
;
778 pci_add_resource_offset(&sys
->resources
, &pp
->io
,
782 sys
->mem_offset
= pp
->mem
.start
- pp
->config
.mem_bus_addr
;
783 pci_add_resource_offset(&sys
->resources
, &pp
->mem
, sys
->mem_offset
);
788 static struct pci_bus
*dw_pcie_scan_bus(int nr
, struct pci_sys_data
*sys
)
791 struct pcie_port
*pp
= sys_to_pcie(sys
);
794 pp
->root_bus_nr
= sys
->busnr
;
795 bus
= pci_scan_root_bus(pp
->dev
, sys
->busnr
, &dw_pcie_ops
,
796 sys
, &sys
->resources
);
805 static int dw_pcie_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
807 struct pcie_port
*pp
= sys_to_pcie(dev
->bus
->sysdata
);
810 irq
= of_irq_parse_and_map_pci(dev
, slot
, pin
);
817 static void dw_pcie_add_bus(struct pci_bus
*bus
)
819 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
820 struct pcie_port
*pp
= sys_to_pcie(bus
->sysdata
);
822 dw_pcie_msi_chip
.dev
= pp
->dev
;
823 bus
->msi
= &dw_pcie_msi_chip
;
827 static struct hw_pci dw_pci
= {
828 .setup
= dw_pcie_setup
,
829 .scan
= dw_pcie_scan_bus
,
830 .map_irq
= dw_pcie_map_irq
,
831 .add_bus
= dw_pcie_add_bus
,
834 void dw_pcie_setup_rc(struct pcie_port
*pp
)
836 struct pcie_port_info
*config
= &pp
->config
;
841 /* set the number of lanes */
842 dw_pcie_readl_rc(pp
, PCIE_PORT_LINK_CONTROL
, &val
);
843 val
&= ~PORT_LINK_MODE_MASK
;
846 val
|= PORT_LINK_MODE_1_LANES
;
849 val
|= PORT_LINK_MODE_2_LANES
;
852 val
|= PORT_LINK_MODE_4_LANES
;
855 dw_pcie_writel_rc(pp
, val
, PCIE_PORT_LINK_CONTROL
);
857 /* set link width speed control register */
858 dw_pcie_readl_rc(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, &val
);
859 val
&= ~PORT_LOGIC_LINK_WIDTH_MASK
;
862 val
|= PORT_LOGIC_LINK_WIDTH_1_LANES
;
865 val
|= PORT_LOGIC_LINK_WIDTH_2_LANES
;
868 val
|= PORT_LOGIC_LINK_WIDTH_4_LANES
;
871 dw_pcie_writel_rc(pp
, val
, PCIE_LINK_WIDTH_SPEED_CONTROL
);
874 dw_pcie_writel_rc(pp
, 0x00000004, PCI_BASE_ADDRESS_0
);
875 dw_pcie_writel_rc(pp
, 0x00000000, PCI_BASE_ADDRESS_1
);
877 /* setup interrupt pins */
878 dw_pcie_readl_rc(pp
, PCI_INTERRUPT_LINE
, &val
);
881 dw_pcie_writel_rc(pp
, val
, PCI_INTERRUPT_LINE
);
883 /* setup bus numbers */
884 dw_pcie_readl_rc(pp
, PCI_PRIMARY_BUS
, &val
);
887 dw_pcie_writel_rc(pp
, val
, PCI_PRIMARY_BUS
);
889 /* setup memory base, memory limit */
890 membase
= ((u32
)pp
->mem_base
& 0xfff00000) >> 16;
891 memlimit
= (config
->mem_size
+ (u32
)pp
->mem_base
) & 0xfff00000;
892 val
= memlimit
| membase
;
893 dw_pcie_writel_rc(pp
, val
, PCI_MEMORY_BASE
);
895 /* setup command register */
896 dw_pcie_readl_rc(pp
, PCI_COMMAND
, &val
);
898 val
|= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
899 PCI_COMMAND_MASTER
| PCI_COMMAND_SERR
;
900 dw_pcie_writel_rc(pp
, val
, PCI_COMMAND
);
903 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
904 MODULE_DESCRIPTION("Designware PCIe host controller driver");
905 MODULE_LICENSE("GPL v2");