2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #ifndef _PCIE_DESIGNWARE_H
15 #define _PCIE_DESIGNWARE_H
17 struct pcie_port_info
{
22 phys_addr_t io_bus_addr
;
23 phys_addr_t mem_bus_addr
;
27 * Maximum number of MSI IRQs can be 256 per controller. But keep
28 * it 32 as of now. Probably we will never need more than 32. If needed,
29 * then increment it in multiple of 32.
31 #define MAX_MSI_IRQS 32
32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
37 void __iomem
*dbi_base
;
40 void __iomem
*va_cfg0_base
;
43 void __iomem
*va_cfg1_base
;
52 struct pcie_port_info config
;
55 struct pcie_host_ops
*ops
;
57 struct irq_domain
*irq_domain
;
58 unsigned long msi_data
;
59 DECLARE_BITMAP(msi_irq_in_use
, MAX_MSI_IRQS
);
62 struct pcie_host_ops
{
63 void (*readl_rc
)(struct pcie_port
*pp
,
64 void __iomem
*dbi_base
, u32
*val
);
65 void (*writel_rc
)(struct pcie_port
*pp
,
66 u32 val
, void __iomem
*dbi_base
);
67 int (*rd_own_conf
)(struct pcie_port
*pp
, int where
, int size
, u32
*val
);
68 int (*wr_own_conf
)(struct pcie_port
*pp
, int where
, int size
, u32 val
);
69 int (*rd_other_conf
)(struct pcie_port
*pp
, struct pci_bus
*bus
,
70 unsigned int devfn
, int where
, int size
, u32
*val
);
71 int (*wr_other_conf
)(struct pcie_port
*pp
, struct pci_bus
*bus
,
72 unsigned int devfn
, int where
, int size
, u32 val
);
73 int (*link_up
)(struct pcie_port
*pp
);
74 void (*host_init
)(struct pcie_port
*pp
);
75 void (*msi_set_irq
)(struct pcie_port
*pp
, int irq
);
76 void (*msi_clear_irq
)(struct pcie_port
*pp
, int irq
);
77 u32 (*get_msi_data
)(struct pcie_port
*pp
);
78 void (*scan_bus
)(struct pcie_port
*pp
);
79 int (*msi_host_init
)(struct pcie_port
*pp
, struct msi_chip
*chip
);
82 int dw_pcie_cfg_read(void __iomem
*addr
, int where
, int size
, u32
*val
);
83 int dw_pcie_cfg_write(void __iomem
*addr
, int where
, int size
, u32 val
);
84 irqreturn_t
dw_handle_msi_irq(struct pcie_port
*pp
);
85 void dw_pcie_msi_init(struct pcie_port
*pp
);
86 int dw_pcie_link_up(struct pcie_port
*pp
);
87 void dw_pcie_setup_rc(struct pcie_port
*pp
);
88 int dw_pcie_host_init(struct pcie_port
*pp
);
90 #endif /* _PCIE_DESIGNWARE_H */
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