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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31
32 #define DRV_NAME "rcar-pcie"
33
34 #define PCIECAR 0x000010
35 #define PCIECCTLR 0x000018
36 #define CONFIG_SEND_ENABLE (1 << 31)
37 #define TYPE0 (0 << 8)
38 #define TYPE1 (1 << 8)
39 #define PCIECDR 0x000020
40 #define PCIEMSR 0x000028
41 #define PCIEINTXR 0x000400
42 #define PCIEMSITXR 0x000840
43
44 /* Transfer control */
45 #define PCIETCTLR 0x02000
46 #define CFINIT 1
47 #define PCIETSTR 0x02004
48 #define DATA_LINK_ACTIVE 1
49 #define PCIEERRFR 0x02020
50 #define UNSUPPORTED_REQUEST (1 << 4)
51 #define PCIEMSIFR 0x02044
52 #define PCIEMSIALR 0x02048
53 #define MSIFE 1
54 #define PCIEMSIAUR 0x0204c
55 #define PCIEMSIIER 0x02050
56
57 /* root port address */
58 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
59
60 /* local address reg & mask */
61 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
62 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
63 #define LAM_PREFETCH (1 << 3)
64 #define LAM_64BIT (1 << 2)
65 #define LAR_ENABLE (1 << 1)
66
67 /* PCIe address reg & mask */
68 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
69 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
70 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
71 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
72 #define PAR_ENABLE (1 << 31)
73 #define IO_SPACE (1 << 8)
74
75 /* Configuration */
76 #define PCICONF(x) (0x010000 + ((x) * 0x4))
77 #define PMCAP(x) (0x010040 + ((x) * 0x4))
78 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
79 #define VCCAP(x) (0x010100 + ((x) * 0x4))
80
81 /* link layer */
82 #define IDSETR1 0x011004
83 #define TLCTLR 0x011048
84 #define MACSR 0x011054
85 #define MACCTLR 0x011058
86 #define SCRAMBLE_DISABLE (1 << 27)
87
88 /* R-Car H1 PHY */
89 #define H1_PCIEPHYADRR 0x04000c
90 #define WRITE_CMD (1 << 16)
91 #define PHY_ACK (1 << 24)
92 #define RATE_POS 12
93 #define LANE_POS 8
94 #define ADR_POS 0
95 #define H1_PCIEPHYDOUTR 0x040014
96 #define H1_PCIEPHYSR 0x040018
97
98 /* R-Car Gen2 PHY */
99 #define GEN2_PCIEPHYADDR 0x780
100 #define GEN2_PCIEPHYDATA 0x784
101 #define GEN2_PCIEPHYCTRL 0x78c
102
103 #define INT_PCI_MSI_NR 32
104
105 #define RCONF(x) (PCICONF(0)+(x))
106 #define RPMCAP(x) (PMCAP(0)+(x))
107 #define REXPCAP(x) (EXPCAP(0)+(x))
108 #define RVCCAP(x) (VCCAP(0)+(x))
109
110 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
111 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
112 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
113
114 #define RCAR_PCI_MAX_RESOURCES 4
115 #define MAX_NR_INBOUND_MAPS 6
116
117 struct rcar_msi {
118 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
119 struct irq_domain *domain;
120 struct msi_controller chip;
121 unsigned long pages;
122 struct mutex lock;
123 int irq1;
124 int irq2;
125 };
126
127 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
128 {
129 return container_of(chip, struct rcar_msi, chip);
130 }
131
132 /* Structure representing the PCIe interface */
133 struct rcar_pcie {
134 struct device *dev;
135 void __iomem *base;
136 struct list_head resources;
137 int root_bus_nr;
138 struct clk *clk;
139 struct clk *bus_clk;
140 struct rcar_msi msi;
141 };
142
143 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
149 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
150 unsigned long reg)
151 {
152 return readl(pcie->base + reg);
153 }
154
155 enum {
156 RCAR_PCI_ACCESS_READ,
157 RCAR_PCI_ACCESS_WRITE,
158 };
159
160 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
161 {
162 int shift = 8 * (where & 3);
163 u32 val = rcar_pci_read_reg(pcie, where & ~3);
164
165 val &= ~(mask << shift);
166 val |= data << shift;
167 rcar_pci_write_reg(pcie, val, where & ~3);
168 }
169
170 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
171 {
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
174
175 return val >> shift;
176 }
177
178 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
179 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
180 unsigned char access_type, struct pci_bus *bus,
181 unsigned int devfn, int where, u32 *data)
182 {
183 int dev, func, reg, index;
184
185 dev = PCI_SLOT(devfn);
186 func = PCI_FUNC(devfn);
187 reg = where & ~3;
188 index = reg / 4;
189
190 /*
191 * While each channel has its own memory-mapped extended config
192 * space, it's generally only accessible when in endpoint mode.
193 * When in root complex mode, the controller is unable to target
194 * itself with either type 0 or type 1 accesses, and indeed, any
195 * controller initiated target transfer to its own config space
196 * result in a completer abort.
197 *
198 * Each channel effectively only supports a single device, but as
199 * the same channel <-> device access works for any PCI_SLOT()
200 * value, we cheat a bit here and bind the controller's config
201 * space to devfn 0 in order to enable self-enumeration. In this
202 * case the regular ECAR/ECDR path is sidelined and the mangled
203 * config access itself is initiated as an internal bus transaction.
204 */
205 if (pci_is_root_bus(bus)) {
206 if (dev != 0)
207 return PCIBIOS_DEVICE_NOT_FOUND;
208
209 if (access_type == RCAR_PCI_ACCESS_READ) {
210 *data = rcar_pci_read_reg(pcie, PCICONF(index));
211 } else {
212 /* Keep an eye out for changes to the root bus number */
213 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
214 pcie->root_bus_nr = *data & 0xff;
215
216 rcar_pci_write_reg(pcie, *data, PCICONF(index));
217 }
218
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 if (pcie->root_bus_nr < 0)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 /* Clear errors */
226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
227
228 /* Set the PIO address */
229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
230 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
231
232 /* Enable the configuration access */
233 if (bus->parent->number == pcie->root_bus_nr)
234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
235 else
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
237
238 /* Check for errors */
239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 /* Check for master and target aborts */
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
244 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 if (access_type == RCAR_PCI_ACCESS_READ)
248 *data = rcar_pci_read_reg(pcie, PCIECDR);
249 else
250 rcar_pci_write_reg(pcie, *data, PCIECDR);
251
252 /* Disable the configuration access */
253 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
254
255 return PCIBIOS_SUCCESSFUL;
256 }
257
258 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260 {
261 struct rcar_pcie *pcie = bus->sysdata;
262 int ret;
263
264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
265 bus, devfn, where, val);
266 if (ret != PCIBIOS_SUCCESSFUL) {
267 *val = 0xffffffff;
268 return ret;
269 }
270
271 if (size == 1)
272 *val = (*val >> (8 * (where & 3))) & 0xff;
273 else if (size == 2)
274 *val = (*val >> (8 * (where & 2))) & 0xffff;
275
276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
277 bus->number, devfn, where, size, (unsigned long)*val);
278
279 return ret;
280 }
281
282 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
283 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
285 {
286 struct rcar_pcie *pcie = bus->sysdata;
287 int shift, ret;
288 u32 data;
289
290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
291 bus, devfn, where, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
293 return ret;
294
295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
296 bus->number, devfn, where, size, (unsigned long)val);
297
298 if (size == 1) {
299 shift = 8 * (where & 3);
300 data &= ~(0xff << shift);
301 data |= ((val & 0xff) << shift);
302 } else if (size == 2) {
303 shift = 8 * (where & 2);
304 data &= ~(0xffff << shift);
305 data |= ((val & 0xffff) << shift);
306 } else
307 data = val;
308
309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
310 bus, devfn, where, &data);
311
312 return ret;
313 }
314
315 static struct pci_ops rcar_pcie_ops = {
316 .read = rcar_pcie_read_conf,
317 .write = rcar_pcie_write_conf,
318 };
319
320 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
321 struct resource *res)
322 {
323 /* Setup PCIe address space mappings for each resource */
324 resource_size_t size;
325 resource_size_t res_start;
326 u32 mask;
327
328 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
329
330 /*
331 * The PAMR mask is calculated in units of 128Bytes, which
332 * keeps things pretty simple.
333 */
334 size = resource_size(res);
335 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
336 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
337
338 if (res->flags & IORESOURCE_IO)
339 res_start = pci_pio_to_address(res->start);
340 else
341 res_start = res->start;
342
343 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
344 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
345 PCIEPALR(win));
346
347 /* First resource is for IO */
348 mask = PAR_ENABLE;
349 if (res->flags & IORESOURCE_IO)
350 mask |= IO_SPACE;
351
352 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
353 }
354
355 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
356 {
357 struct resource_entry *win;
358 int i = 0;
359
360 /* Setup PCI resources */
361 resource_list_for_each_entry(win, &pci->resources) {
362 struct resource *res = win->res;
363
364 if (!res->flags)
365 continue;
366
367 switch (resource_type(res)) {
368 case IORESOURCE_IO:
369 case IORESOURCE_MEM:
370 rcar_pcie_setup_window(i, pci, res);
371 i++;
372 break;
373 case IORESOURCE_BUS:
374 pci->root_bus_nr = res->start;
375 break;
376 default:
377 continue;
378 }
379
380 pci_add_resource(resource, res);
381 }
382
383 return 1;
384 }
385
386 static int rcar_pcie_enable(struct rcar_pcie *pcie)
387 {
388 struct pci_bus *bus, *child;
389 LIST_HEAD(res);
390
391 rcar_pcie_setup(&res, pcie);
392
393 /* Do not reassign resources if probe only */
394 if (!pci_has_flag(PCI_PROBE_ONLY))
395 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
396
397 if (IS_ENABLED(CONFIG_PCI_MSI))
398 bus = pci_scan_root_bus_msi(pcie->dev, pcie->root_bus_nr,
399 &rcar_pcie_ops, pcie, &res, &pcie->msi.chip);
400 else
401 bus = pci_scan_root_bus(pcie->dev, pcie->root_bus_nr,
402 &rcar_pcie_ops, pcie, &res);
403
404 if (!bus) {
405 dev_err(pcie->dev, "Scanning rootbus failed");
406 return -ENODEV;
407 }
408
409 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
410
411 if (!pci_has_flag(PCI_PROBE_ONLY)) {
412 pci_bus_size_bridges(bus);
413 pci_bus_assign_resources(bus);
414
415 list_for_each_entry(child, &bus->children, node)
416 pcie_bus_configure_settings(child);
417 }
418
419 pci_bus_add_devices(bus);
420
421 return 0;
422 }
423
424 static int phy_wait_for_ack(struct rcar_pcie *pcie)
425 {
426 unsigned int timeout = 100;
427
428 while (timeout--) {
429 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
430 return 0;
431
432 udelay(100);
433 }
434
435 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
436
437 return -ETIMEDOUT;
438 }
439
440 static void phy_write_reg(struct rcar_pcie *pcie,
441 unsigned int rate, unsigned int addr,
442 unsigned int lane, unsigned int data)
443 {
444 unsigned long phyaddr;
445
446 phyaddr = WRITE_CMD |
447 ((rate & 1) << RATE_POS) |
448 ((lane & 0xf) << LANE_POS) |
449 ((addr & 0xff) << ADR_POS);
450
451 /* Set write data */
452 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
453 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
454
455 /* Ignore errors as they will be dealt with if the data link is down */
456 phy_wait_for_ack(pcie);
457
458 /* Clear command */
459 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
460 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
461
462 /* Ignore errors as they will be dealt with if the data link is down */
463 phy_wait_for_ack(pcie);
464 }
465
466 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
467 {
468 unsigned int timeout = 10;
469
470 while (timeout--) {
471 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
472 return 0;
473
474 msleep(5);
475 }
476
477 return -ETIMEDOUT;
478 }
479
480 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
481 {
482 int err;
483
484 /* Begin initialization */
485 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
486
487 /* Set mode */
488 rcar_pci_write_reg(pcie, 1, PCIEMSR);
489
490 /*
491 * Initial header for port config space is type 1, set the device
492 * class to match. Hardware takes care of propagating the IDSETR
493 * settings, so there is no need to bother with a quirk.
494 */
495 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
496
497 /*
498 * Setup Secondary Bus Number & Subordinate Bus Number, even though
499 * they aren't used, to avoid bridge being detected as broken.
500 */
501 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
502 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
503
504 /* Initialize default capabilities. */
505 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
506 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
507 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
508 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
509 PCI_HEADER_TYPE_BRIDGE);
510
511 /* Enable data link layer active state reporting */
512 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
513 PCI_EXP_LNKCAP_DLLLARC);
514
515 /* Write out the physical slot number = 0 */
516 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
517
518 /* Set the completion timer timeout to the maximum 50ms. */
519 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
520
521 /* Terminate list of capabilities (Next Capability Offset=0) */
522 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
523
524 /* Enable MSI */
525 if (IS_ENABLED(CONFIG_PCI_MSI))
526 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
527
528 /* Finish initialization - establish a PCI Express link */
529 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
530
531 /* This will timeout if we don't have a link. */
532 err = rcar_pcie_wait_for_dl(pcie);
533 if (err)
534 return err;
535
536 /* Enable INTx interrupts */
537 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
538
539 wmb();
540
541 return 0;
542 }
543
544 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
545 {
546 unsigned int timeout = 10;
547
548 /* Initialize the phy */
549 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
550 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
551 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
552 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
553 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
554 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
555 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
556 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
557 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
558 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
559 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
560 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
561
562 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
563 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
564 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
565
566 while (timeout--) {
567 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
568 return rcar_pcie_hw_init(pcie);
569
570 msleep(5);
571 }
572
573 return -ETIMEDOUT;
574 }
575
576 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
577 {
578 /*
579 * These settings come from the R-Car Series, 2nd Generation User's
580 * Manual, section 50.3.1 (2) Initialization of the physical layer.
581 */
582 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
583 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
584 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
585 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
586
587 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
588 /* The following value is for DC connection, no termination resistor */
589 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
590 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
591 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
592
593 return rcar_pcie_hw_init(pcie);
594 }
595
596 static int rcar_msi_alloc(struct rcar_msi *chip)
597 {
598 int msi;
599
600 mutex_lock(&chip->lock);
601
602 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
603 if (msi < INT_PCI_MSI_NR)
604 set_bit(msi, chip->used);
605 else
606 msi = -ENOSPC;
607
608 mutex_unlock(&chip->lock);
609
610 return msi;
611 }
612
613 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
614 {
615 mutex_lock(&chip->lock);
616 clear_bit(irq, chip->used);
617 mutex_unlock(&chip->lock);
618 }
619
620 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
621 {
622 struct rcar_pcie *pcie = data;
623 struct rcar_msi *msi = &pcie->msi;
624 unsigned long reg;
625
626 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
627
628 /* MSI & INTx share an interrupt - we only handle MSI here */
629 if (!reg)
630 return IRQ_NONE;
631
632 while (reg) {
633 unsigned int index = find_first_bit(&reg, 32);
634 unsigned int irq;
635
636 /* clear the interrupt */
637 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
638
639 irq = irq_find_mapping(msi->domain, index);
640 if (irq) {
641 if (test_bit(index, msi->used))
642 generic_handle_irq(irq);
643 else
644 dev_info(pcie->dev, "unhandled MSI\n");
645 } else {
646 /* Unknown MSI, just clear it */
647 dev_dbg(pcie->dev, "unexpected MSI\n");
648 }
649
650 /* see if there's any more pending in this vector */
651 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
652 }
653
654 return IRQ_HANDLED;
655 }
656
657 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
658 struct msi_desc *desc)
659 {
660 struct rcar_msi *msi = to_rcar_msi(chip);
661 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
662 struct msi_msg msg;
663 unsigned int irq;
664 int hwirq;
665
666 hwirq = rcar_msi_alloc(msi);
667 if (hwirq < 0)
668 return hwirq;
669
670 irq = irq_create_mapping(msi->domain, hwirq);
671 if (!irq) {
672 rcar_msi_free(msi, hwirq);
673 return -EINVAL;
674 }
675
676 irq_set_msi_desc(irq, desc);
677
678 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
679 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
680 msg.data = hwirq;
681
682 pci_write_msi_msg(irq, &msg);
683
684 return 0;
685 }
686
687 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
688 {
689 struct rcar_msi *msi = to_rcar_msi(chip);
690 struct irq_data *d = irq_get_irq_data(irq);
691
692 rcar_msi_free(msi, d->hwirq);
693 }
694
695 static struct irq_chip rcar_msi_irq_chip = {
696 .name = "R-Car PCIe MSI",
697 .irq_enable = pci_msi_unmask_irq,
698 .irq_disable = pci_msi_mask_irq,
699 .irq_mask = pci_msi_mask_irq,
700 .irq_unmask = pci_msi_unmask_irq,
701 };
702
703 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
704 irq_hw_number_t hwirq)
705 {
706 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
707 irq_set_chip_data(irq, domain->host_data);
708
709 return 0;
710 }
711
712 static const struct irq_domain_ops msi_domain_ops = {
713 .map = rcar_msi_map,
714 };
715
716 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
717 {
718 struct platform_device *pdev = to_platform_device(pcie->dev);
719 struct rcar_msi *msi = &pcie->msi;
720 unsigned long base;
721 int err;
722
723 mutex_init(&msi->lock);
724
725 msi->chip.dev = pcie->dev;
726 msi->chip.setup_irq = rcar_msi_setup_irq;
727 msi->chip.teardown_irq = rcar_msi_teardown_irq;
728
729 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
730 &msi_domain_ops, &msi->chip);
731 if (!msi->domain) {
732 dev_err(&pdev->dev, "failed to create IRQ domain\n");
733 return -ENOMEM;
734 }
735
736 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
737 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
738 IRQF_SHARED | IRQF_NO_THREAD,
739 rcar_msi_irq_chip.name, pcie);
740 if (err < 0) {
741 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
742 goto err;
743 }
744
745 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
746 IRQF_SHARED | IRQF_NO_THREAD,
747 rcar_msi_irq_chip.name, pcie);
748 if (err < 0) {
749 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
750 goto err;
751 }
752
753 /* setup MSI data target */
754 msi->pages = __get_free_pages(GFP_KERNEL, 0);
755 base = virt_to_phys((void *)msi->pages);
756
757 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
758 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
759
760 /* enable all MSI interrupts */
761 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
762
763 return 0;
764
765 err:
766 irq_domain_remove(msi->domain);
767 return err;
768 }
769
770 static int rcar_pcie_get_resources(struct platform_device *pdev,
771 struct rcar_pcie *pcie)
772 {
773 struct resource res;
774 int err, i;
775
776 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
777 if (err)
778 return err;
779
780 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
781 if (IS_ERR(pcie->clk)) {
782 dev_err(pcie->dev, "cannot get platform clock\n");
783 return PTR_ERR(pcie->clk);
784 }
785 err = clk_prepare_enable(pcie->clk);
786 if (err)
787 goto fail_clk;
788
789 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
790 if (IS_ERR(pcie->bus_clk)) {
791 dev_err(pcie->dev, "cannot get pcie bus clock\n");
792 err = PTR_ERR(pcie->bus_clk);
793 goto fail_clk;
794 }
795 err = clk_prepare_enable(pcie->bus_clk);
796 if (err)
797 goto err_map_reg;
798
799 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
800 if (!i) {
801 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
802 err = -ENOENT;
803 goto err_map_reg;
804 }
805 pcie->msi.irq1 = i;
806
807 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
808 if (!i) {
809 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
810 err = -ENOENT;
811 goto err_map_reg;
812 }
813 pcie->msi.irq2 = i;
814
815 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
816 if (IS_ERR(pcie->base)) {
817 err = PTR_ERR(pcie->base);
818 goto err_map_reg;
819 }
820
821 return 0;
822
823 err_map_reg:
824 clk_disable_unprepare(pcie->bus_clk);
825 fail_clk:
826 clk_disable_unprepare(pcie->clk);
827
828 return err;
829 }
830
831 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
832 struct of_pci_range *range,
833 int *index)
834 {
835 u64 restype = range->flags;
836 u64 cpu_addr = range->cpu_addr;
837 u64 cpu_end = range->cpu_addr + range->size;
838 u64 pci_addr = range->pci_addr;
839 u32 flags = LAM_64BIT | LAR_ENABLE;
840 u64 mask;
841 u64 size;
842 int idx = *index;
843
844 if (restype & IORESOURCE_PREFETCH)
845 flags |= LAM_PREFETCH;
846
847 /*
848 * If the size of the range is larger than the alignment of the start
849 * address, we have to use multiple entries to perform the mapping.
850 */
851 if (cpu_addr > 0) {
852 unsigned long nr_zeros = __ffs64(cpu_addr);
853 u64 alignment = 1ULL << nr_zeros;
854
855 size = min(range->size, alignment);
856 } else {
857 size = range->size;
858 }
859 /* Hardware supports max 4GiB inbound region */
860 size = min(size, 1ULL << 32);
861
862 mask = roundup_pow_of_two(size) - 1;
863 mask &= ~0xf;
864
865 while (cpu_addr < cpu_end) {
866 /*
867 * Set up 64-bit inbound regions as the range parser doesn't
868 * distinguish between 32 and 64-bit types.
869 */
870 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
871 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
872 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
873
874 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
875 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
876 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
877
878 pci_addr += size;
879 cpu_addr += size;
880 idx += 2;
881
882 if (idx > MAX_NR_INBOUND_MAPS) {
883 dev_err(pcie->dev, "Failed to map inbound regions!\n");
884 return -EINVAL;
885 }
886 }
887 *index = idx;
888
889 return 0;
890 }
891
892 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
893 struct device_node *node)
894 {
895 const int na = 3, ns = 2;
896 int rlen;
897
898 parser->node = node;
899 parser->pna = of_n_addr_cells(node);
900 parser->np = parser->pna + na + ns;
901
902 parser->range = of_get_property(node, "dma-ranges", &rlen);
903 if (!parser->range)
904 return -ENOENT;
905
906 parser->end = parser->range + rlen / sizeof(__be32);
907 return 0;
908 }
909
910 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
911 struct device_node *np)
912 {
913 struct of_pci_range range;
914 struct of_pci_range_parser parser;
915 int index = 0;
916 int err;
917
918 if (pci_dma_range_parser_init(&parser, np))
919 return -EINVAL;
920
921 /* Get the dma-ranges from DT */
922 for_each_of_pci_range(&parser, &range) {
923 u64 end = range.cpu_addr + range.size - 1;
924 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
925 range.flags, range.cpu_addr, end, range.pci_addr);
926
927 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
928 if (err)
929 return err;
930 }
931
932 return 0;
933 }
934
935 static const struct of_device_id rcar_pcie_of_match[] = {
936 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
937 { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 },
938 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init_gen2 },
939 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init_gen2 },
940 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
941 {},
942 };
943 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
944
945 static void rcar_pcie_release_of_pci_ranges(struct rcar_pcie *pci)
946 {
947 pci_free_resource_list(&pci->resources);
948 }
949
950 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
951 {
952 int err;
953 struct device *dev = pci->dev;
954 struct device_node *np = dev->of_node;
955 resource_size_t iobase;
956 struct resource_entry *win;
957
958 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, &iobase);
959 if (err)
960 return err;
961
962 resource_list_for_each_entry(win, &pci->resources) {
963 struct resource *parent, *res = win->res;
964
965 switch (resource_type(res)) {
966 case IORESOURCE_IO:
967 parent = &ioport_resource;
968 err = pci_remap_iospace(res, iobase);
969 if (err) {
970 dev_warn(dev, "error %d: failed to map resource %pR\n",
971 err, res);
972 continue;
973 }
974 break;
975 case IORESOURCE_MEM:
976 parent = &iomem_resource;
977 break;
978
979 case IORESOURCE_BUS:
980 default:
981 continue;
982 }
983
984 err = devm_request_resource(dev, parent, res);
985 if (err)
986 goto out_release_res;
987 }
988
989 return 0;
990
991 out_release_res:
992 rcar_pcie_release_of_pci_ranges(pci);
993 return err;
994 }
995
996 static int rcar_pcie_probe(struct platform_device *pdev)
997 {
998 struct rcar_pcie *pcie;
999 unsigned int data;
1000 const struct of_device_id *of_id;
1001 int err;
1002 int (*hw_init_fn)(struct rcar_pcie *);
1003
1004 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1005 if (!pcie)
1006 return -ENOMEM;
1007
1008 pcie->dev = &pdev->dev;
1009 platform_set_drvdata(pdev, pcie);
1010
1011 INIT_LIST_HEAD(&pcie->resources);
1012
1013 rcar_pcie_parse_request_of_pci_ranges(pcie);
1014
1015 err = rcar_pcie_get_resources(pdev, pcie);
1016 if (err < 0) {
1017 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
1018 return err;
1019 }
1020
1021 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
1022 if (err)
1023 return err;
1024
1025 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
1026 if (!of_id || !of_id->data)
1027 return -EINVAL;
1028 hw_init_fn = of_id->data;
1029
1030 pm_runtime_enable(pcie->dev);
1031 err = pm_runtime_get_sync(pcie->dev);
1032 if (err < 0) {
1033 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1034 goto err_pm_disable;
1035 }
1036
1037 /* Failure to get a link might just be that no cards are inserted */
1038 err = hw_init_fn(pcie);
1039 if (err) {
1040 dev_info(&pdev->dev, "PCIe link down\n");
1041 err = 0;
1042 goto err_pm_put;
1043 }
1044
1045 data = rcar_pci_read_reg(pcie, MACSR);
1046 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1047
1048 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1049 err = rcar_pcie_enable_msi(pcie);
1050 if (err < 0) {
1051 dev_err(&pdev->dev,
1052 "failed to enable MSI support: %d\n",
1053 err);
1054 goto err_pm_put;
1055 }
1056 }
1057
1058 err = rcar_pcie_enable(pcie);
1059 if (err)
1060 goto err_pm_put;
1061
1062 return 0;
1063
1064 err_pm_put:
1065 pm_runtime_put(pcie->dev);
1066
1067 err_pm_disable:
1068 pm_runtime_disable(pcie->dev);
1069 return err;
1070 }
1071
1072 static struct platform_driver rcar_pcie_driver = {
1073 .driver = {
1074 .name = DRV_NAME,
1075 .of_match_table = rcar_pcie_of_match,
1076 .suppress_bind_attrs = true,
1077 },
1078 .probe = rcar_pcie_probe,
1079 };
1080 module_platform_driver(rcar_pcie_driver);
1081
1082 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1083 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1084 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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