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PCI: rcar: Remove dependency on ARM-specific struct hw_pci
[deliverable/linux.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define RCAR_PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_controller chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119 };
120
121 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
122 {
123 return container_of(chip, struct rcar_msi, chip);
124 }
125
126 /* Structure representing the PCIe interface */
127 /*
128 * ARM pcibios functions expect the ARM struct pci_sys_data as the PCI
129 * sysdata. Add pci_sys_data as the first element in struct gen_pci so
130 * that when we use a gen_pci pointer as sysdata, it is also a pointer to
131 * a struct pci_sys_data.
132 */
133 struct rcar_pcie {
134 #ifdef CONFIG_ARM
135 struct pci_sys_data sys;
136 #endif
137 struct device *dev;
138 void __iomem *base;
139 struct resource res[RCAR_PCI_MAX_RESOURCES];
140 struct resource busn;
141 int root_bus_nr;
142 struct clk *clk;
143 struct clk *bus_clk;
144 struct rcar_msi msi;
145 };
146
147 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
148 unsigned long reg)
149 {
150 writel(val, pcie->base + reg);
151 }
152
153 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
154 unsigned long reg)
155 {
156 return readl(pcie->base + reg);
157 }
158
159 enum {
160 RCAR_PCI_ACCESS_READ,
161 RCAR_PCI_ACCESS_WRITE,
162 };
163
164 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
165 {
166 int shift = 8 * (where & 3);
167 u32 val = rcar_pci_read_reg(pcie, where & ~3);
168
169 val &= ~(mask << shift);
170 val |= data << shift;
171 rcar_pci_write_reg(pcie, val, where & ~3);
172 }
173
174 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
175 {
176 int shift = 8 * (where & 3);
177 u32 val = rcar_pci_read_reg(pcie, where & ~3);
178
179 return val >> shift;
180 }
181
182 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
183 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
184 unsigned char access_type, struct pci_bus *bus,
185 unsigned int devfn, int where, u32 *data)
186 {
187 int dev, func, reg, index;
188
189 dev = PCI_SLOT(devfn);
190 func = PCI_FUNC(devfn);
191 reg = where & ~3;
192 index = reg / 4;
193
194 /*
195 * While each channel has its own memory-mapped extended config
196 * space, it's generally only accessible when in endpoint mode.
197 * When in root complex mode, the controller is unable to target
198 * itself with either type 0 or type 1 accesses, and indeed, any
199 * controller initiated target transfer to its own config space
200 * result in a completer abort.
201 *
202 * Each channel effectively only supports a single device, but as
203 * the same channel <-> device access works for any PCI_SLOT()
204 * value, we cheat a bit here and bind the controller's config
205 * space to devfn 0 in order to enable self-enumeration. In this
206 * case the regular ECAR/ECDR path is sidelined and the mangled
207 * config access itself is initiated as an internal bus transaction.
208 */
209 if (pci_is_root_bus(bus)) {
210 if (dev != 0)
211 return PCIBIOS_DEVICE_NOT_FOUND;
212
213 if (access_type == RCAR_PCI_ACCESS_READ) {
214 *data = rcar_pci_read_reg(pcie, PCICONF(index));
215 } else {
216 /* Keep an eye out for changes to the root bus number */
217 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
218 pcie->root_bus_nr = *data & 0xff;
219
220 rcar_pci_write_reg(pcie, *data, PCICONF(index));
221 }
222
223 return PCIBIOS_SUCCESSFUL;
224 }
225
226 if (pcie->root_bus_nr < 0)
227 return PCIBIOS_DEVICE_NOT_FOUND;
228
229 /* Clear errors */
230 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
231
232 /* Set the PIO address */
233 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
234 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
235
236 /* Enable the configuration access */
237 if (bus->parent->number == pcie->root_bus_nr)
238 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
239 else
240 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
241
242 /* Check for errors */
243 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
244 return PCIBIOS_DEVICE_NOT_FOUND;
245
246 /* Check for master and target aborts */
247 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
248 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
249 return PCIBIOS_DEVICE_NOT_FOUND;
250
251 if (access_type == RCAR_PCI_ACCESS_READ)
252 *data = rcar_pci_read_reg(pcie, PCIECDR);
253 else
254 rcar_pci_write_reg(pcie, *data, PCIECDR);
255
256 /* Disable the configuration access */
257 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
258
259 return PCIBIOS_SUCCESSFUL;
260 }
261
262 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
263 int where, int size, u32 *val)
264 {
265 struct rcar_pcie *pcie = bus->sysdata;
266 int ret;
267
268 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
269 bus, devfn, where, val);
270 if (ret != PCIBIOS_SUCCESSFUL) {
271 *val = 0xffffffff;
272 return ret;
273 }
274
275 if (size == 1)
276 *val = (*val >> (8 * (where & 3))) & 0xff;
277 else if (size == 2)
278 *val = (*val >> (8 * (where & 2))) & 0xffff;
279
280 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
281 bus->number, devfn, where, size, (unsigned long)*val);
282
283 return ret;
284 }
285
286 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
287 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
288 int where, int size, u32 val)
289 {
290 struct rcar_pcie *pcie = bus->sysdata;
291 int shift, ret;
292 u32 data;
293
294 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
295 bus, devfn, where, &data);
296 if (ret != PCIBIOS_SUCCESSFUL)
297 return ret;
298
299 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
300 bus->number, devfn, where, size, (unsigned long)val);
301
302 if (size == 1) {
303 shift = 8 * (where & 3);
304 data &= ~(0xff << shift);
305 data |= ((val & 0xff) << shift);
306 } else if (size == 2) {
307 shift = 8 * (where & 2);
308 data &= ~(0xffff << shift);
309 data |= ((val & 0xffff) << shift);
310 } else
311 data = val;
312
313 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
314 bus, devfn, where, &data);
315
316 return ret;
317 }
318
319 static struct pci_ops rcar_pcie_ops = {
320 .read = rcar_pcie_read_conf,
321 .write = rcar_pcie_write_conf,
322 };
323
324 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
325 {
326 struct resource *res = &pcie->res[win];
327
328 /* Setup PCIe address space mappings for each resource */
329 resource_size_t size;
330 resource_size_t res_start;
331 u32 mask;
332
333 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
334
335 /*
336 * The PAMR mask is calculated in units of 128Bytes, which
337 * keeps things pretty simple.
338 */
339 size = resource_size(res);
340 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
341 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
342
343 if (res->flags & IORESOURCE_IO)
344 res_start = pci_pio_to_address(res->start);
345 else
346 res_start = res->start;
347
348 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
349 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
350 PCIEPALR(win));
351
352 /* First resource is for IO */
353 mask = PAR_ENABLE;
354 if (res->flags & IORESOURCE_IO)
355 mask |= IO_SPACE;
356
357 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
358 }
359
360 static int rcar_pcie_setup(int nr, struct list_head *resource, struct rcar_pcie *pcie)
361 {
362 struct resource *res;
363 int i;
364
365 pcie->root_bus_nr = -1;
366
367 /* Setup PCI resources */
368 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
369
370 res = &pcie->res[i];
371 if (!res->flags)
372 continue;
373
374 rcar_pcie_setup_window(i, pcie);
375
376 if (res->flags & IORESOURCE_IO) {
377 phys_addr_t io_start = pci_pio_to_address(res->start);
378 pci_ioremap_io(nr * SZ_64K, io_start);
379 }
380
381 pci_add_resource(resource, res);
382 }
383 pci_add_resource(resource, &pcie->busn);
384
385 return 1;
386 }
387
388 static int rcar_pcie_enable(struct rcar_pcie *pcie)
389 {
390 struct pci_bus *bus, *child;
391 LIST_HEAD(res);
392
393 rcar_pcie_setup(1, &res, pcie);
394
395 /* Do not reassign resources if probe only */
396 if (!pci_has_flag(PCI_PROBE_ONLY))
397 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
398
399 if (IS_ENABLED(CONFIG_PCI_MSI))
400 bus = pci_scan_root_bus_msi(pcie->dev, pcie->root_bus_nr,
401 &rcar_pcie_ops, pcie, &res, &pcie->msi.chip);
402 else
403 bus = pci_scan_root_bus(pcie->dev, pcie->root_bus_nr,
404 &rcar_pcie_ops, pcie, &res);
405
406 if (!bus) {
407 dev_err(pcie->dev, "Scanning rootbus failed");
408 return -ENODEV;
409 }
410
411 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
412
413 if (!pci_has_flag(PCI_PROBE_ONLY)) {
414 pci_bus_size_bridges(bus);
415 pci_bus_assign_resources(bus);
416
417 list_for_each_entry(child, &bus->children, node)
418 pcie_bus_configure_settings(child);
419 }
420
421 pci_bus_add_devices(bus);
422
423 return 0;
424 }
425
426 static int phy_wait_for_ack(struct rcar_pcie *pcie)
427 {
428 unsigned int timeout = 100;
429
430 while (timeout--) {
431 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
432 return 0;
433
434 udelay(100);
435 }
436
437 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
438
439 return -ETIMEDOUT;
440 }
441
442 static void phy_write_reg(struct rcar_pcie *pcie,
443 unsigned int rate, unsigned int addr,
444 unsigned int lane, unsigned int data)
445 {
446 unsigned long phyaddr;
447
448 phyaddr = WRITE_CMD |
449 ((rate & 1) << RATE_POS) |
450 ((lane & 0xf) << LANE_POS) |
451 ((addr & 0xff) << ADR_POS);
452
453 /* Set write data */
454 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
455 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
456
457 /* Ignore errors as they will be dealt with if the data link is down */
458 phy_wait_for_ack(pcie);
459
460 /* Clear command */
461 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
462 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
463
464 /* Ignore errors as they will be dealt with if the data link is down */
465 phy_wait_for_ack(pcie);
466 }
467
468 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
469 {
470 unsigned int timeout = 10;
471
472 while (timeout--) {
473 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
474 return 0;
475
476 msleep(5);
477 }
478
479 return -ETIMEDOUT;
480 }
481
482 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
483 {
484 int err;
485
486 /* Begin initialization */
487 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
488
489 /* Set mode */
490 rcar_pci_write_reg(pcie, 1, PCIEMSR);
491
492 /*
493 * Initial header for port config space is type 1, set the device
494 * class to match. Hardware takes care of propagating the IDSETR
495 * settings, so there is no need to bother with a quirk.
496 */
497 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
498
499 /*
500 * Setup Secondary Bus Number & Subordinate Bus Number, even though
501 * they aren't used, to avoid bridge being detected as broken.
502 */
503 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
504 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
505
506 /* Initialize default capabilities. */
507 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
508 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
509 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
510 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
511 PCI_HEADER_TYPE_BRIDGE);
512
513 /* Enable data link layer active state reporting */
514 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
515 PCI_EXP_LNKCAP_DLLLARC);
516
517 /* Write out the physical slot number = 0 */
518 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
519
520 /* Set the completion timer timeout to the maximum 50ms. */
521 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
522
523 /* Terminate list of capabilities (Next Capability Offset=0) */
524 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
525
526 /* Enable MSI */
527 if (IS_ENABLED(CONFIG_PCI_MSI))
528 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
529
530 /* Finish initialization - establish a PCI Express link */
531 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
532
533 /* This will timeout if we don't have a link. */
534 err = rcar_pcie_wait_for_dl(pcie);
535 if (err)
536 return err;
537
538 /* Enable INTx interrupts */
539 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
540
541 wmb();
542
543 return 0;
544 }
545
546 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
547 {
548 unsigned int timeout = 10;
549
550 /* Initialize the phy */
551 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
552 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
553 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
554 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
555 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
556 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
557 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
558 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
559 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
560 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
561 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
562 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
563
564 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
565 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
566 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
567
568 while (timeout--) {
569 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
570 return rcar_pcie_hw_init(pcie);
571
572 msleep(5);
573 }
574
575 return -ETIMEDOUT;
576 }
577
578 static int rcar_msi_alloc(struct rcar_msi *chip)
579 {
580 int msi;
581
582 mutex_lock(&chip->lock);
583
584 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
585 if (msi < INT_PCI_MSI_NR)
586 set_bit(msi, chip->used);
587 else
588 msi = -ENOSPC;
589
590 mutex_unlock(&chip->lock);
591
592 return msi;
593 }
594
595 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
596 {
597 mutex_lock(&chip->lock);
598 clear_bit(irq, chip->used);
599 mutex_unlock(&chip->lock);
600 }
601
602 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
603 {
604 struct rcar_pcie *pcie = data;
605 struct rcar_msi *msi = &pcie->msi;
606 unsigned long reg;
607
608 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
609
610 /* MSI & INTx share an interrupt - we only handle MSI here */
611 if (!reg)
612 return IRQ_NONE;
613
614 while (reg) {
615 unsigned int index = find_first_bit(&reg, 32);
616 unsigned int irq;
617
618 /* clear the interrupt */
619 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
620
621 irq = irq_find_mapping(msi->domain, index);
622 if (irq) {
623 if (test_bit(index, msi->used))
624 generic_handle_irq(irq);
625 else
626 dev_info(pcie->dev, "unhandled MSI\n");
627 } else {
628 /* Unknown MSI, just clear it */
629 dev_dbg(pcie->dev, "unexpected MSI\n");
630 }
631
632 /* see if there's any more pending in this vector */
633 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
634 }
635
636 return IRQ_HANDLED;
637 }
638
639 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
640 struct msi_desc *desc)
641 {
642 struct rcar_msi *msi = to_rcar_msi(chip);
643 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
644 struct msi_msg msg;
645 unsigned int irq;
646 int hwirq;
647
648 hwirq = rcar_msi_alloc(msi);
649 if (hwirq < 0)
650 return hwirq;
651
652 irq = irq_create_mapping(msi->domain, hwirq);
653 if (!irq) {
654 rcar_msi_free(msi, hwirq);
655 return -EINVAL;
656 }
657
658 irq_set_msi_desc(irq, desc);
659
660 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
661 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
662 msg.data = hwirq;
663
664 pci_write_msi_msg(irq, &msg);
665
666 return 0;
667 }
668
669 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
670 {
671 struct rcar_msi *msi = to_rcar_msi(chip);
672 struct irq_data *d = irq_get_irq_data(irq);
673
674 rcar_msi_free(msi, d->hwirq);
675 }
676
677 static struct irq_chip rcar_msi_irq_chip = {
678 .name = "R-Car PCIe MSI",
679 .irq_enable = pci_msi_unmask_irq,
680 .irq_disable = pci_msi_mask_irq,
681 .irq_mask = pci_msi_mask_irq,
682 .irq_unmask = pci_msi_unmask_irq,
683 };
684
685 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
686 irq_hw_number_t hwirq)
687 {
688 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
689 irq_set_chip_data(irq, domain->host_data);
690
691 return 0;
692 }
693
694 static const struct irq_domain_ops msi_domain_ops = {
695 .map = rcar_msi_map,
696 };
697
698 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
699 {
700 struct platform_device *pdev = to_platform_device(pcie->dev);
701 struct rcar_msi *msi = &pcie->msi;
702 unsigned long base;
703 int err;
704
705 mutex_init(&msi->lock);
706
707 msi->chip.dev = pcie->dev;
708 msi->chip.setup_irq = rcar_msi_setup_irq;
709 msi->chip.teardown_irq = rcar_msi_teardown_irq;
710
711 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
712 &msi_domain_ops, &msi->chip);
713 if (!msi->domain) {
714 dev_err(&pdev->dev, "failed to create IRQ domain\n");
715 return -ENOMEM;
716 }
717
718 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
719 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
720 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
721 if (err < 0) {
722 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
723 goto err;
724 }
725
726 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
727 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
728 if (err < 0) {
729 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
730 goto err;
731 }
732
733 /* setup MSI data target */
734 msi->pages = __get_free_pages(GFP_KERNEL, 0);
735 base = virt_to_phys((void *)msi->pages);
736
737 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
738 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
739
740 /* enable all MSI interrupts */
741 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
742
743 return 0;
744
745 err:
746 irq_domain_remove(msi->domain);
747 return err;
748 }
749
750 static int rcar_pcie_get_resources(struct platform_device *pdev,
751 struct rcar_pcie *pcie)
752 {
753 struct resource res;
754 int err, i;
755
756 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
757 if (err)
758 return err;
759
760 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
761 if (IS_ERR(pcie->clk)) {
762 dev_err(pcie->dev, "cannot get platform clock\n");
763 return PTR_ERR(pcie->clk);
764 }
765 err = clk_prepare_enable(pcie->clk);
766 if (err)
767 goto fail_clk;
768
769 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
770 if (IS_ERR(pcie->bus_clk)) {
771 dev_err(pcie->dev, "cannot get pcie bus clock\n");
772 err = PTR_ERR(pcie->bus_clk);
773 goto fail_clk;
774 }
775 err = clk_prepare_enable(pcie->bus_clk);
776 if (err)
777 goto err_map_reg;
778
779 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
780 if (!i) {
781 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
782 err = -ENOENT;
783 goto err_map_reg;
784 }
785 pcie->msi.irq1 = i;
786
787 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
788 if (!i) {
789 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
790 err = -ENOENT;
791 goto err_map_reg;
792 }
793 pcie->msi.irq2 = i;
794
795 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
796 if (IS_ERR(pcie->base)) {
797 err = PTR_ERR(pcie->base);
798 goto err_map_reg;
799 }
800
801 return 0;
802
803 err_map_reg:
804 clk_disable_unprepare(pcie->bus_clk);
805 fail_clk:
806 clk_disable_unprepare(pcie->clk);
807
808 return err;
809 }
810
811 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
812 struct of_pci_range *range,
813 int *index)
814 {
815 u64 restype = range->flags;
816 u64 cpu_addr = range->cpu_addr;
817 u64 cpu_end = range->cpu_addr + range->size;
818 u64 pci_addr = range->pci_addr;
819 u32 flags = LAM_64BIT | LAR_ENABLE;
820 u64 mask;
821 u64 size;
822 int idx = *index;
823
824 if (restype & IORESOURCE_PREFETCH)
825 flags |= LAM_PREFETCH;
826
827 /*
828 * If the size of the range is larger than the alignment of the start
829 * address, we have to use multiple entries to perform the mapping.
830 */
831 if (cpu_addr > 0) {
832 unsigned long nr_zeros = __ffs64(cpu_addr);
833 u64 alignment = 1ULL << nr_zeros;
834
835 size = min(range->size, alignment);
836 } else {
837 size = range->size;
838 }
839 /* Hardware supports max 4GiB inbound region */
840 size = min(size, 1ULL << 32);
841
842 mask = roundup_pow_of_two(size) - 1;
843 mask &= ~0xf;
844
845 while (cpu_addr < cpu_end) {
846 /*
847 * Set up 64-bit inbound regions as the range parser doesn't
848 * distinguish between 32 and 64-bit types.
849 */
850 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
851 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
852 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
853
854 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
855 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
856 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
857
858 pci_addr += size;
859 cpu_addr += size;
860 idx += 2;
861
862 if (idx > MAX_NR_INBOUND_MAPS) {
863 dev_err(pcie->dev, "Failed to map inbound regions!\n");
864 return -EINVAL;
865 }
866 }
867 *index = idx;
868
869 return 0;
870 }
871
872 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
873 struct device_node *node)
874 {
875 const int na = 3, ns = 2;
876 int rlen;
877
878 parser->node = node;
879 parser->pna = of_n_addr_cells(node);
880 parser->np = parser->pna + na + ns;
881
882 parser->range = of_get_property(node, "dma-ranges", &rlen);
883 if (!parser->range)
884 return -ENOENT;
885
886 parser->end = parser->range + rlen / sizeof(__be32);
887 return 0;
888 }
889
890 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
891 struct device_node *np)
892 {
893 struct of_pci_range range;
894 struct of_pci_range_parser parser;
895 int index = 0;
896 int err;
897
898 if (pci_dma_range_parser_init(&parser, np))
899 return -EINVAL;
900
901 /* Get the dma-ranges from DT */
902 for_each_of_pci_range(&parser, &range) {
903 u64 end = range.cpu_addr + range.size - 1;
904 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
905 range.flags, range.cpu_addr, end, range.pci_addr);
906
907 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
908 if (err)
909 return err;
910 }
911
912 return 0;
913 }
914
915 static const struct of_device_id rcar_pcie_of_match[] = {
916 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
917 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
918 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
919 {},
920 };
921 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
922
923 static int rcar_pcie_probe(struct platform_device *pdev)
924 {
925 struct rcar_pcie *pcie;
926 unsigned int data;
927 struct of_pci_range range;
928 struct of_pci_range_parser parser;
929 const struct of_device_id *of_id;
930 int err, win = 0;
931 int (*hw_init_fn)(struct rcar_pcie *);
932
933 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
934 if (!pcie)
935 return -ENOMEM;
936
937 pcie->dev = &pdev->dev;
938 platform_set_drvdata(pdev, pcie);
939
940 /* Get the bus range */
941 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
942 dev_err(&pdev->dev, "failed to parse bus-range property\n");
943 return -EINVAL;
944 }
945
946 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
947 dev_err(&pdev->dev, "missing ranges property\n");
948 return -EINVAL;
949 }
950
951 err = rcar_pcie_get_resources(pdev, pcie);
952 if (err < 0) {
953 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
954 return err;
955 }
956
957 for_each_of_pci_range(&parser, &range) {
958 err = of_pci_range_to_resource(&range, pdev->dev.of_node,
959 &pcie->res[win++]);
960 if (err < 0)
961 return err;
962
963 if (win > RCAR_PCI_MAX_RESOURCES)
964 break;
965 }
966
967 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
968 if (err)
969 return err;
970
971 if (IS_ENABLED(CONFIG_PCI_MSI)) {
972 err = rcar_pcie_enable_msi(pcie);
973 if (err < 0) {
974 dev_err(&pdev->dev,
975 "failed to enable MSI support: %d\n",
976 err);
977 return err;
978 }
979 }
980
981 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
982 if (!of_id || !of_id->data)
983 return -EINVAL;
984 hw_init_fn = of_id->data;
985
986 /* Failure to get a link might just be that no cards are inserted */
987 err = hw_init_fn(pcie);
988 if (err) {
989 dev_info(&pdev->dev, "PCIe link down\n");
990 return 0;
991 }
992
993 data = rcar_pci_read_reg(pcie, MACSR);
994 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
995
996 return rcar_pcie_enable(pcie);
997 }
998
999 static struct platform_driver rcar_pcie_driver = {
1000 .driver = {
1001 .name = DRV_NAME,
1002 .of_match_table = rcar_pcie_of_match,
1003 .suppress_bind_attrs = true,
1004 },
1005 .probe = rcar_pcie_probe,
1006 };
1007 module_platform_driver(rcar_pcie_driver);
1008
1009 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1010 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1011 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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