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PCI/MSI: Rename write_msi_msg() to pci_write_msi_msg()
[deliverable/linux.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPARL(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPARH(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define RCAR_PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_controller chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119 };
120
121 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
122 {
123 return container_of(chip, struct rcar_msi, chip);
124 }
125
126 /* Structure representing the PCIe interface */
127 struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
130 struct resource res[RCAR_PCI_MAX_RESOURCES];
131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
135 struct rcar_msi msi;
136 };
137
138 static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139 {
140 return sys->private_data;
141 }
142
143 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
149 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
150 unsigned long reg)
151 {
152 return readl(pcie->base + reg);
153 }
154
155 enum {
156 RCAR_PCI_ACCESS_READ,
157 RCAR_PCI_ACCESS_WRITE,
158 };
159
160 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
161 {
162 int shift = 8 * (where & 3);
163 u32 val = rcar_pci_read_reg(pcie, where & ~3);
164
165 val &= ~(mask << shift);
166 val |= data << shift;
167 rcar_pci_write_reg(pcie, val, where & ~3);
168 }
169
170 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
171 {
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
174
175 return val >> shift;
176 }
177
178 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
179 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
180 unsigned char access_type, struct pci_bus *bus,
181 unsigned int devfn, int where, u32 *data)
182 {
183 int dev, func, reg, index;
184
185 dev = PCI_SLOT(devfn);
186 func = PCI_FUNC(devfn);
187 reg = where & ~3;
188 index = reg / 4;
189
190 /*
191 * While each channel has its own memory-mapped extended config
192 * space, it's generally only accessible when in endpoint mode.
193 * When in root complex mode, the controller is unable to target
194 * itself with either type 0 or type 1 accesses, and indeed, any
195 * controller initiated target transfer to its own config space
196 * result in a completer abort.
197 *
198 * Each channel effectively only supports a single device, but as
199 * the same channel <-> device access works for any PCI_SLOT()
200 * value, we cheat a bit here and bind the controller's config
201 * space to devfn 0 in order to enable self-enumeration. In this
202 * case the regular ECAR/ECDR path is sidelined and the mangled
203 * config access itself is initiated as an internal bus transaction.
204 */
205 if (pci_is_root_bus(bus)) {
206 if (dev != 0)
207 return PCIBIOS_DEVICE_NOT_FOUND;
208
209 if (access_type == RCAR_PCI_ACCESS_READ) {
210 *data = rcar_pci_read_reg(pcie, PCICONF(index));
211 } else {
212 /* Keep an eye out for changes to the root bus number */
213 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
214 pcie->root_bus_nr = *data & 0xff;
215
216 rcar_pci_write_reg(pcie, *data, PCICONF(index));
217 }
218
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 if (pcie->root_bus_nr < 0)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 /* Clear errors */
226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
227
228 /* Set the PIO address */
229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
230 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
231
232 /* Enable the configuration access */
233 if (bus->parent->number == pcie->root_bus_nr)
234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
235 else
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
237
238 /* Check for errors */
239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 /* Check for master and target aborts */
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
244 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 if (access_type == RCAR_PCI_ACCESS_READ)
248 *data = rcar_pci_read_reg(pcie, PCIECDR);
249 else
250 rcar_pci_write_reg(pcie, *data, PCIECDR);
251
252 /* Disable the configuration access */
253 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
254
255 return PCIBIOS_SUCCESSFUL;
256 }
257
258 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260 {
261 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
262 int ret;
263
264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
265 bus, devfn, where, val);
266 if (ret != PCIBIOS_SUCCESSFUL) {
267 *val = 0xffffffff;
268 return ret;
269 }
270
271 if (size == 1)
272 *val = (*val >> (8 * (where & 3))) & 0xff;
273 else if (size == 2)
274 *val = (*val >> (8 * (where & 2))) & 0xffff;
275
276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
277 bus->number, devfn, where, size, (unsigned long)*val);
278
279 return ret;
280 }
281
282 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
283 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
285 {
286 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
287 int shift, ret;
288 u32 data;
289
290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
291 bus, devfn, where, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
293 return ret;
294
295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
296 bus->number, devfn, where, size, (unsigned long)val);
297
298 if (size == 1) {
299 shift = 8 * (where & 3);
300 data &= ~(0xff << shift);
301 data |= ((val & 0xff) << shift);
302 } else if (size == 2) {
303 shift = 8 * (where & 2);
304 data &= ~(0xffff << shift);
305 data |= ((val & 0xffff) << shift);
306 } else
307 data = val;
308
309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
310 bus, devfn, where, &data);
311
312 return ret;
313 }
314
315 static struct pci_ops rcar_pcie_ops = {
316 .read = rcar_pcie_read_conf,
317 .write = rcar_pcie_write_conf,
318 };
319
320 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
321 {
322 struct resource *res = &pcie->res[win];
323
324 /* Setup PCIe address space mappings for each resource */
325 resource_size_t size;
326 resource_size_t res_start;
327 u32 mask;
328
329 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
330
331 /*
332 * The PAMR mask is calculated in units of 128Bytes, which
333 * keeps things pretty simple.
334 */
335 size = resource_size(res);
336 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
337 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
338
339 if (res->flags & IORESOURCE_IO)
340 res_start = pci_pio_to_address(res->start);
341 else
342 res_start = res->start;
343
344 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
345 rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));
346
347 /* First resource is for IO */
348 mask = PAR_ENABLE;
349 if (res->flags & IORESOURCE_IO)
350 mask |= IO_SPACE;
351
352 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
353 }
354
355 static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
356 {
357 struct rcar_pcie *pcie = sys_to_pcie(sys);
358 struct resource *res;
359 int i;
360
361 pcie->root_bus_nr = -1;
362
363 /* Setup PCI resources */
364 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
365
366 res = &pcie->res[i];
367 if (!res->flags)
368 continue;
369
370 rcar_pcie_setup_window(i, pcie);
371
372 if (res->flags & IORESOURCE_IO) {
373 phys_addr_t io_start = pci_pio_to_address(res->start);
374 pci_ioremap_io(nr * SZ_64K, io_start);
375 } else
376 pci_add_resource(&sys->resources, res);
377 }
378 pci_add_resource(&sys->resources, &pcie->busn);
379
380 return 1;
381 }
382
383 struct hw_pci rcar_pci = {
384 .setup = rcar_pcie_setup,
385 .map_irq = of_irq_parse_and_map_pci,
386 .ops = &rcar_pcie_ops,
387 };
388
389 static void rcar_pcie_enable(struct rcar_pcie *pcie)
390 {
391 struct platform_device *pdev = to_platform_device(pcie->dev);
392
393 rcar_pci.nr_controllers = 1;
394 rcar_pci.private_data = (void **)&pcie;
395 #ifdef CONFIG_PCI_MSI
396 rcar_pci.msi_ctrl = &pcie->msi.chip;
397 #endif
398
399 pci_common_init_dev(&pdev->dev, &rcar_pci);
400 #ifdef CONFIG_PCI_DOMAINS
401 rcar_pci.domain++;
402 #endif
403 }
404
405 static int phy_wait_for_ack(struct rcar_pcie *pcie)
406 {
407 unsigned int timeout = 100;
408
409 while (timeout--) {
410 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
411 return 0;
412
413 udelay(100);
414 }
415
416 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
417
418 return -ETIMEDOUT;
419 }
420
421 static void phy_write_reg(struct rcar_pcie *pcie,
422 unsigned int rate, unsigned int addr,
423 unsigned int lane, unsigned int data)
424 {
425 unsigned long phyaddr;
426
427 phyaddr = WRITE_CMD |
428 ((rate & 1) << RATE_POS) |
429 ((lane & 0xf) << LANE_POS) |
430 ((addr & 0xff) << ADR_POS);
431
432 /* Set write data */
433 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
434 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
435
436 /* Ignore errors as they will be dealt with if the data link is down */
437 phy_wait_for_ack(pcie);
438
439 /* Clear command */
440 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
441 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
442
443 /* Ignore errors as they will be dealt with if the data link is down */
444 phy_wait_for_ack(pcie);
445 }
446
447 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
448 {
449 unsigned int timeout = 10;
450
451 while (timeout--) {
452 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
453 return 0;
454
455 msleep(5);
456 }
457
458 return -ETIMEDOUT;
459 }
460
461 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
462 {
463 int err;
464
465 /* Begin initialization */
466 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
467
468 /* Set mode */
469 rcar_pci_write_reg(pcie, 1, PCIEMSR);
470
471 /*
472 * Initial header for port config space is type 1, set the device
473 * class to match. Hardware takes care of propagating the IDSETR
474 * settings, so there is no need to bother with a quirk.
475 */
476 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
477
478 /*
479 * Setup Secondary Bus Number & Subordinate Bus Number, even though
480 * they aren't used, to avoid bridge being detected as broken.
481 */
482 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
483 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
484
485 /* Initialize default capabilities. */
486 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
487 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
488 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
489 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
490 PCI_HEADER_TYPE_BRIDGE);
491
492 /* Enable data link layer active state reporting */
493 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
494 PCI_EXP_LNKCAP_DLLLARC);
495
496 /* Write out the physical slot number = 0 */
497 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
498
499 /* Set the completion timer timeout to the maximum 50ms. */
500 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
501
502 /* Terminate list of capabilities (Next Capability Offset=0) */
503 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
504
505 /* Enable MSI */
506 if (IS_ENABLED(CONFIG_PCI_MSI))
507 rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
508
509 /* Finish initialization - establish a PCI Express link */
510 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
511
512 /* This will timeout if we don't have a link. */
513 err = rcar_pcie_wait_for_dl(pcie);
514 if (err)
515 return err;
516
517 /* Enable INTx interrupts */
518 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
519
520 wmb();
521
522 return 0;
523 }
524
525 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
526 {
527 unsigned int timeout = 10;
528
529 /* Initialize the phy */
530 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
531 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
532 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
533 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
534 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
535 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
536 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
537 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
538 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
539 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
540 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
541 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
542
543 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
544 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
545 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
546
547 while (timeout--) {
548 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
549 return rcar_pcie_hw_init(pcie);
550
551 msleep(5);
552 }
553
554 return -ETIMEDOUT;
555 }
556
557 static int rcar_msi_alloc(struct rcar_msi *chip)
558 {
559 int msi;
560
561 mutex_lock(&chip->lock);
562
563 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
564 if (msi < INT_PCI_MSI_NR)
565 set_bit(msi, chip->used);
566 else
567 msi = -ENOSPC;
568
569 mutex_unlock(&chip->lock);
570
571 return msi;
572 }
573
574 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
575 {
576 mutex_lock(&chip->lock);
577 clear_bit(irq, chip->used);
578 mutex_unlock(&chip->lock);
579 }
580
581 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
582 {
583 struct rcar_pcie *pcie = data;
584 struct rcar_msi *msi = &pcie->msi;
585 unsigned long reg;
586
587 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
588
589 /* MSI & INTx share an interrupt - we only handle MSI here */
590 if (!reg)
591 return IRQ_NONE;
592
593 while (reg) {
594 unsigned int index = find_first_bit(&reg, 32);
595 unsigned int irq;
596
597 /* clear the interrupt */
598 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
599
600 irq = irq_find_mapping(msi->domain, index);
601 if (irq) {
602 if (test_bit(index, msi->used))
603 generic_handle_irq(irq);
604 else
605 dev_info(pcie->dev, "unhandled MSI\n");
606 } else {
607 /* Unknown MSI, just clear it */
608 dev_dbg(pcie->dev, "unexpected MSI\n");
609 }
610
611 /* see if there's any more pending in this vector */
612 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
613 }
614
615 return IRQ_HANDLED;
616 }
617
618 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
619 struct msi_desc *desc)
620 {
621 struct rcar_msi *msi = to_rcar_msi(chip);
622 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
623 struct msi_msg msg;
624 unsigned int irq;
625 int hwirq;
626
627 hwirq = rcar_msi_alloc(msi);
628 if (hwirq < 0)
629 return hwirq;
630
631 irq = irq_create_mapping(msi->domain, hwirq);
632 if (!irq) {
633 rcar_msi_free(msi, hwirq);
634 return -EINVAL;
635 }
636
637 irq_set_msi_desc(irq, desc);
638
639 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
640 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
641 msg.data = hwirq;
642
643 pci_write_msi_msg(irq, &msg);
644
645 return 0;
646 }
647
648 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
649 {
650 struct rcar_msi *msi = to_rcar_msi(chip);
651 struct irq_data *d = irq_get_irq_data(irq);
652
653 rcar_msi_free(msi, d->hwirq);
654 }
655
656 static struct irq_chip rcar_msi_irq_chip = {
657 .name = "R-Car PCIe MSI",
658 .irq_enable = unmask_msi_irq,
659 .irq_disable = mask_msi_irq,
660 .irq_mask = mask_msi_irq,
661 .irq_unmask = unmask_msi_irq,
662 };
663
664 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
665 irq_hw_number_t hwirq)
666 {
667 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
668 irq_set_chip_data(irq, domain->host_data);
669 set_irq_flags(irq, IRQF_VALID);
670
671 return 0;
672 }
673
674 static const struct irq_domain_ops msi_domain_ops = {
675 .map = rcar_msi_map,
676 };
677
678 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
679 {
680 struct platform_device *pdev = to_platform_device(pcie->dev);
681 struct rcar_msi *msi = &pcie->msi;
682 unsigned long base;
683 int err;
684
685 mutex_init(&msi->lock);
686
687 msi->chip.dev = pcie->dev;
688 msi->chip.setup_irq = rcar_msi_setup_irq;
689 msi->chip.teardown_irq = rcar_msi_teardown_irq;
690
691 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
692 &msi_domain_ops, &msi->chip);
693 if (!msi->domain) {
694 dev_err(&pdev->dev, "failed to create IRQ domain\n");
695 return -ENOMEM;
696 }
697
698 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
699 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
700 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
701 if (err < 0) {
702 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
703 goto err;
704 }
705
706 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
707 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
708 if (err < 0) {
709 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
710 goto err;
711 }
712
713 /* setup MSI data target */
714 msi->pages = __get_free_pages(GFP_KERNEL, 0);
715 base = virt_to_phys((void *)msi->pages);
716
717 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
718 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
719
720 /* enable all MSI interrupts */
721 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
722
723 return 0;
724
725 err:
726 irq_domain_remove(msi->domain);
727 return err;
728 }
729
730 static int rcar_pcie_get_resources(struct platform_device *pdev,
731 struct rcar_pcie *pcie)
732 {
733 struct resource res;
734 int err, i;
735
736 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
737 if (err)
738 return err;
739
740 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
741 if (IS_ERR(pcie->clk)) {
742 dev_err(pcie->dev, "cannot get platform clock\n");
743 return PTR_ERR(pcie->clk);
744 }
745 err = clk_prepare_enable(pcie->clk);
746 if (err)
747 goto fail_clk;
748
749 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
750 if (IS_ERR(pcie->bus_clk)) {
751 dev_err(pcie->dev, "cannot get pcie bus clock\n");
752 err = PTR_ERR(pcie->bus_clk);
753 goto fail_clk;
754 }
755 err = clk_prepare_enable(pcie->bus_clk);
756 if (err)
757 goto err_map_reg;
758
759 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
760 if (i < 0) {
761 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
762 err = -ENOENT;
763 goto err_map_reg;
764 }
765 pcie->msi.irq1 = i;
766
767 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
768 if (i < 0) {
769 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
770 err = -ENOENT;
771 goto err_map_reg;
772 }
773 pcie->msi.irq2 = i;
774
775 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
776 if (IS_ERR(pcie->base)) {
777 err = PTR_ERR(pcie->base);
778 goto err_map_reg;
779 }
780
781 return 0;
782
783 err_map_reg:
784 clk_disable_unprepare(pcie->bus_clk);
785 fail_clk:
786 clk_disable_unprepare(pcie->clk);
787
788 return err;
789 }
790
791 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
792 struct of_pci_range *range,
793 int *index)
794 {
795 u64 restype = range->flags;
796 u64 cpu_addr = range->cpu_addr;
797 u64 cpu_end = range->cpu_addr + range->size;
798 u64 pci_addr = range->pci_addr;
799 u32 flags = LAM_64BIT | LAR_ENABLE;
800 u64 mask;
801 u64 size;
802 int idx = *index;
803
804 if (restype & IORESOURCE_PREFETCH)
805 flags |= LAM_PREFETCH;
806
807 /*
808 * If the size of the range is larger than the alignment of the start
809 * address, we have to use multiple entries to perform the mapping.
810 */
811 if (cpu_addr > 0) {
812 unsigned long nr_zeros = __ffs64(cpu_addr);
813 u64 alignment = 1ULL << nr_zeros;
814
815 size = min(range->size, alignment);
816 } else {
817 size = range->size;
818 }
819 /* Hardware supports max 4GiB inbound region */
820 size = min(size, 1ULL << 32);
821
822 mask = roundup_pow_of_two(size) - 1;
823 mask &= ~0xf;
824
825 while (cpu_addr < cpu_end) {
826 /*
827 * Set up 64-bit inbound regions as the range parser doesn't
828 * distinguish between 32 and 64-bit types.
829 */
830 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
831 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
832 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
833
834 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
835 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
836 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
837
838 pci_addr += size;
839 cpu_addr += size;
840 idx += 2;
841
842 if (idx > MAX_NR_INBOUND_MAPS) {
843 dev_err(pcie->dev, "Failed to map inbound regions!\n");
844 return -EINVAL;
845 }
846 }
847 *index = idx;
848
849 return 0;
850 }
851
852 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
853 struct device_node *node)
854 {
855 const int na = 3, ns = 2;
856 int rlen;
857
858 parser->node = node;
859 parser->pna = of_n_addr_cells(node);
860 parser->np = parser->pna + na + ns;
861
862 parser->range = of_get_property(node, "dma-ranges", &rlen);
863 if (!parser->range)
864 return -ENOENT;
865
866 parser->end = parser->range + rlen / sizeof(__be32);
867 return 0;
868 }
869
870 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
871 struct device_node *np)
872 {
873 struct of_pci_range range;
874 struct of_pci_range_parser parser;
875 int index = 0;
876 int err;
877
878 if (pci_dma_range_parser_init(&parser, np))
879 return -EINVAL;
880
881 /* Get the dma-ranges from DT */
882 for_each_of_pci_range(&parser, &range) {
883 u64 end = range.cpu_addr + range.size - 1;
884 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
885 range.flags, range.cpu_addr, end, range.pci_addr);
886
887 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
888 if (err)
889 return err;
890 }
891
892 return 0;
893 }
894
895 static const struct of_device_id rcar_pcie_of_match[] = {
896 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
897 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
898 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
899 {},
900 };
901 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
902
903 static int rcar_pcie_probe(struct platform_device *pdev)
904 {
905 struct rcar_pcie *pcie;
906 unsigned int data;
907 struct of_pci_range range;
908 struct of_pci_range_parser parser;
909 const struct of_device_id *of_id;
910 int err, win = 0;
911 int (*hw_init_fn)(struct rcar_pcie *);
912
913 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
914 if (!pcie)
915 return -ENOMEM;
916
917 pcie->dev = &pdev->dev;
918 platform_set_drvdata(pdev, pcie);
919
920 /* Get the bus range */
921 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
922 dev_err(&pdev->dev, "failed to parse bus-range property\n");
923 return -EINVAL;
924 }
925
926 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
927 dev_err(&pdev->dev, "missing ranges property\n");
928 return -EINVAL;
929 }
930
931 err = rcar_pcie_get_resources(pdev, pcie);
932 if (err < 0) {
933 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
934 return err;
935 }
936
937 for_each_of_pci_range(&parser, &range) {
938 err = of_pci_range_to_resource(&range, pdev->dev.of_node,
939 &pcie->res[win++]);
940 if (err < 0)
941 return err;
942
943 if (win > RCAR_PCI_MAX_RESOURCES)
944 break;
945 }
946
947 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
948 if (err)
949 return err;
950
951 if (IS_ENABLED(CONFIG_PCI_MSI)) {
952 err = rcar_pcie_enable_msi(pcie);
953 if (err < 0) {
954 dev_err(&pdev->dev,
955 "failed to enable MSI support: %d\n",
956 err);
957 return err;
958 }
959 }
960
961 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
962 if (!of_id || !of_id->data)
963 return -EINVAL;
964 hw_init_fn = of_id->data;
965
966 /* Failure to get a link might just be that no cards are inserted */
967 err = hw_init_fn(pcie);
968 if (err) {
969 dev_info(&pdev->dev, "PCIe link down\n");
970 return 0;
971 }
972
973 data = rcar_pci_read_reg(pcie, MACSR);
974 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
975
976 rcar_pcie_enable(pcie);
977
978 return 0;
979 }
980
981 static struct platform_driver rcar_pcie_driver = {
982 .driver = {
983 .name = DRV_NAME,
984 .owner = THIS_MODULE,
985 .of_match_table = rcar_pcie_of_match,
986 .suppress_bind_attrs = true,
987 },
988 .probe = rcar_pcie_probe,
989 };
990 module_platform_driver(rcar_pcie_driver);
991
992 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
993 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
994 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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