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Merge tag 'microblaze-3.16-rc1' of git://git.monstr.eu/linux-2.6-microblaze into...
[deliverable/linux.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPARL(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPARH(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_chip chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119 };
120
121 static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
122 {
123 return container_of(chip, struct rcar_msi, chip);
124 }
125
126 /* Structure representing the PCIe interface */
127 struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
130 struct resource res[PCI_MAX_RESOURCES];
131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
135 struct rcar_msi msi;
136 };
137
138 static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139 {
140 return sys->private_data;
141 }
142
143 static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
149 static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
150 {
151 return readl(pcie->base + reg);
152 }
153
154 enum {
155 PCI_ACCESS_READ,
156 PCI_ACCESS_WRITE,
157 };
158
159 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
160 {
161 int shift = 8 * (where & 3);
162 u32 val = pci_read_reg(pcie, where & ~3);
163
164 val &= ~(mask << shift);
165 val |= data << shift;
166 pci_write_reg(pcie, val, where & ~3);
167 }
168
169 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
170 {
171 int shift = 8 * (where & 3);
172 u32 val = pci_read_reg(pcie, where & ~3);
173
174 return val >> shift;
175 }
176
177 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
178 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
179 unsigned char access_type, struct pci_bus *bus,
180 unsigned int devfn, int where, u32 *data)
181 {
182 int dev, func, reg, index;
183
184 dev = PCI_SLOT(devfn);
185 func = PCI_FUNC(devfn);
186 reg = where & ~3;
187 index = reg / 4;
188
189 /*
190 * While each channel has its own memory-mapped extended config
191 * space, it's generally only accessible when in endpoint mode.
192 * When in root complex mode, the controller is unable to target
193 * itself with either type 0 or type 1 accesses, and indeed, any
194 * controller initiated target transfer to its own config space
195 * result in a completer abort.
196 *
197 * Each channel effectively only supports a single device, but as
198 * the same channel <-> device access works for any PCI_SLOT()
199 * value, we cheat a bit here and bind the controller's config
200 * space to devfn 0 in order to enable self-enumeration. In this
201 * case the regular ECAR/ECDR path is sidelined and the mangled
202 * config access itself is initiated as an internal bus transaction.
203 */
204 if (pci_is_root_bus(bus)) {
205 if (dev != 0)
206 return PCIBIOS_DEVICE_NOT_FOUND;
207
208 if (access_type == PCI_ACCESS_READ) {
209 *data = pci_read_reg(pcie, PCICONF(index));
210 } else {
211 /* Keep an eye out for changes to the root bus number */
212 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
213 pcie->root_bus_nr = *data & 0xff;
214
215 pci_write_reg(pcie, *data, PCICONF(index));
216 }
217
218 return PCIBIOS_SUCCESSFUL;
219 }
220
221 if (pcie->root_bus_nr < 0)
222 return PCIBIOS_DEVICE_NOT_FOUND;
223
224 /* Clear errors */
225 pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
226
227 /* Set the PIO address */
228 pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
229 PCIE_CONF_FUNC(func) | reg, PCIECAR);
230
231 /* Enable the configuration access */
232 if (bus->parent->number == pcie->root_bus_nr)
233 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
234 else
235 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
236
237 /* Check for errors */
238 if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 /* Check for master and target aborts */
242 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
243 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
244 return PCIBIOS_DEVICE_NOT_FOUND;
245
246 if (access_type == PCI_ACCESS_READ)
247 *data = pci_read_reg(pcie, PCIECDR);
248 else
249 pci_write_reg(pcie, *data, PCIECDR);
250
251 /* Disable the configuration access */
252 pci_write_reg(pcie, 0, PCIECCTLR);
253
254 return PCIBIOS_SUCCESSFUL;
255 }
256
257 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
258 int where, int size, u32 *val)
259 {
260 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
261 int ret;
262
263 if ((size == 2) && (where & 1))
264 return PCIBIOS_BAD_REGISTER_NUMBER;
265 else if ((size == 4) && (where & 3))
266 return PCIBIOS_BAD_REGISTER_NUMBER;
267
268 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
269 bus, devfn, where, val);
270 if (ret != PCIBIOS_SUCCESSFUL) {
271 *val = 0xffffffff;
272 return ret;
273 }
274
275 if (size == 1)
276 *val = (*val >> (8 * (where & 3))) & 0xff;
277 else if (size == 2)
278 *val = (*val >> (8 * (where & 2))) & 0xffff;
279
280 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
281 "where=0x%04x size=%d val=0x%08lx\n", bus->number,
282 devfn, where, size, (unsigned long)*val);
283
284 return ret;
285 }
286
287 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
288 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
289 int where, int size, u32 val)
290 {
291 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
292 int shift, ret;
293 u32 data;
294
295 if ((size == 2) && (where & 1))
296 return PCIBIOS_BAD_REGISTER_NUMBER;
297 else if ((size == 4) && (where & 3))
298 return PCIBIOS_BAD_REGISTER_NUMBER;
299
300 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
301 bus, devfn, where, &data);
302 if (ret != PCIBIOS_SUCCESSFUL)
303 return ret;
304
305 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
306 "where=0x%04x size=%d val=0x%08lx\n", bus->number,
307 devfn, where, size, (unsigned long)val);
308
309 if (size == 1) {
310 shift = 8 * (where & 3);
311 data &= ~(0xff << shift);
312 data |= ((val & 0xff) << shift);
313 } else if (size == 2) {
314 shift = 8 * (where & 2);
315 data &= ~(0xffff << shift);
316 data |= ((val & 0xffff) << shift);
317 } else
318 data = val;
319
320 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
321 bus, devfn, where, &data);
322
323 return ret;
324 }
325
326 static struct pci_ops rcar_pcie_ops = {
327 .read = rcar_pcie_read_conf,
328 .write = rcar_pcie_write_conf,
329 };
330
331 static void rcar_pcie_setup_window(int win, struct resource *res,
332 struct rcar_pcie *pcie)
333 {
334 /* Setup PCIe address space mappings for each resource */
335 resource_size_t size;
336 u32 mask;
337
338 pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
339
340 /*
341 * The PAMR mask is calculated in units of 128Bytes, which
342 * keeps things pretty simple.
343 */
344 size = resource_size(res);
345 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
346 pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
347
348 pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
349 pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
350
351 /* First resource is for IO */
352 mask = PAR_ENABLE;
353 if (res->flags & IORESOURCE_IO)
354 mask |= IO_SPACE;
355
356 pci_write_reg(pcie, mask, PCIEPTCTLR(win));
357 }
358
359 static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
360 {
361 struct rcar_pcie *pcie = sys_to_pcie(sys);
362 struct resource *res;
363 int i;
364
365 pcie->root_bus_nr = -1;
366
367 /* Setup PCI resources */
368 for (i = 0; i < PCI_MAX_RESOURCES; i++) {
369
370 res = &pcie->res[i];
371 if (!res->flags)
372 continue;
373
374 rcar_pcie_setup_window(i, res, pcie);
375
376 if (res->flags & IORESOURCE_IO)
377 pci_ioremap_io(nr * SZ_64K, res->start);
378 else
379 pci_add_resource(&sys->resources, res);
380 }
381 pci_add_resource(&sys->resources, &pcie->busn);
382
383 return 1;
384 }
385
386 static void rcar_pcie_add_bus(struct pci_bus *bus)
387 {
388 if (IS_ENABLED(CONFIG_PCI_MSI)) {
389 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
390
391 bus->msi = &pcie->msi.chip;
392 }
393 }
394
395 struct hw_pci rcar_pci = {
396 .setup = rcar_pcie_setup,
397 .map_irq = of_irq_parse_and_map_pci,
398 .ops = &rcar_pcie_ops,
399 .add_bus = rcar_pcie_add_bus,
400 };
401
402 static void rcar_pcie_enable(struct rcar_pcie *pcie)
403 {
404 struct platform_device *pdev = to_platform_device(pcie->dev);
405
406 rcar_pci.nr_controllers = 1;
407 rcar_pci.private_data = (void **)&pcie;
408
409 pci_common_init_dev(&pdev->dev, &rcar_pci);
410 #ifdef CONFIG_PCI_DOMAINS
411 rcar_pci.domain++;
412 #endif
413 }
414
415 static int phy_wait_for_ack(struct rcar_pcie *pcie)
416 {
417 unsigned int timeout = 100;
418
419 while (timeout--) {
420 if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
421 return 0;
422
423 udelay(100);
424 }
425
426 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
427
428 return -ETIMEDOUT;
429 }
430
431 static void phy_write_reg(struct rcar_pcie *pcie,
432 unsigned int rate, unsigned int addr,
433 unsigned int lane, unsigned int data)
434 {
435 unsigned long phyaddr;
436
437 phyaddr = WRITE_CMD |
438 ((rate & 1) << RATE_POS) |
439 ((lane & 0xf) << LANE_POS) |
440 ((addr & 0xff) << ADR_POS);
441
442 /* Set write data */
443 pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
444 pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
445
446 /* Ignore errors as they will be dealt with if the data link is down */
447 phy_wait_for_ack(pcie);
448
449 /* Clear command */
450 pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
451 pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
452
453 /* Ignore errors as they will be dealt with if the data link is down */
454 phy_wait_for_ack(pcie);
455 }
456
457 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
458 {
459 unsigned int timeout = 10;
460
461 while (timeout--) {
462 if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
463 return 0;
464
465 msleep(5);
466 }
467
468 return -ETIMEDOUT;
469 }
470
471 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
472 {
473 int err;
474
475 /* Begin initialization */
476 pci_write_reg(pcie, 0, PCIETCTLR);
477
478 /* Set mode */
479 pci_write_reg(pcie, 1, PCIEMSR);
480
481 /*
482 * Initial header for port config space is type 1, set the device
483 * class to match. Hardware takes care of propagating the IDSETR
484 * settings, so there is no need to bother with a quirk.
485 */
486 pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
487
488 /*
489 * Setup Secondary Bus Number & Subordinate Bus Number, even though
490 * they aren't used, to avoid bridge being detected as broken.
491 */
492 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
493 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
494
495 /* Initialize default capabilities. */
496 rcar_rmw32(pcie, REXPCAP(0), 0, PCI_CAP_ID_EXP);
497 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
498 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
499 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
500 PCI_HEADER_TYPE_BRIDGE);
501
502 /* Enable data link layer active state reporting */
503 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), 0, PCI_EXP_LNKCAP_DLLLARC);
504
505 /* Write out the physical slot number = 0 */
506 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
507
508 /* Set the completion timer timeout to the maximum 50ms. */
509 rcar_rmw32(pcie, TLCTLR+1, 0x3f, 50);
510
511 /* Terminate list of capabilities (Next Capability Offset=0) */
512 rcar_rmw32(pcie, RVCCAP(0), 0xfff0, 0);
513
514 /* Enable MAC data scrambling. */
515 rcar_rmw32(pcie, MACCTLR, SCRAMBLE_DISABLE, 0);
516
517 /* Enable MSI */
518 if (IS_ENABLED(CONFIG_PCI_MSI))
519 pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
520
521 /* Finish initialization - establish a PCI Express link */
522 pci_write_reg(pcie, CFINIT, PCIETCTLR);
523
524 /* This will timeout if we don't have a link. */
525 err = rcar_pcie_wait_for_dl(pcie);
526 if (err)
527 return err;
528
529 /* Enable INTx interrupts */
530 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
531
532 /* Enable slave Bus Mastering */
533 rcar_rmw32(pcie, RCONF(PCI_STATUS), PCI_STATUS_DEVSEL_MASK,
534 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
535 PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST);
536
537 wmb();
538
539 return 0;
540 }
541
542 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
543 {
544 unsigned int timeout = 10;
545
546 /* Initialize the phy */
547 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
548 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
549 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
550 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
551 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
552 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
553 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
554 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
555 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
556 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
557 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
558 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
559
560 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
561 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
562 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
563
564 while (timeout--) {
565 if (pci_read_reg(pcie, H1_PCIEPHYSR))
566 return rcar_pcie_hw_init(pcie);
567
568 msleep(5);
569 }
570
571 return -ETIMEDOUT;
572 }
573
574 static int rcar_msi_alloc(struct rcar_msi *chip)
575 {
576 int msi;
577
578 mutex_lock(&chip->lock);
579
580 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
581 if (msi < INT_PCI_MSI_NR)
582 set_bit(msi, chip->used);
583 else
584 msi = -ENOSPC;
585
586 mutex_unlock(&chip->lock);
587
588 return msi;
589 }
590
591 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
592 {
593 mutex_lock(&chip->lock);
594 clear_bit(irq, chip->used);
595 mutex_unlock(&chip->lock);
596 }
597
598 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
599 {
600 struct rcar_pcie *pcie = data;
601 struct rcar_msi *msi = &pcie->msi;
602 unsigned long reg;
603
604 reg = pci_read_reg(pcie, PCIEMSIFR);
605
606 /* MSI & INTx share an interrupt - we only handle MSI here */
607 if (!reg)
608 return IRQ_NONE;
609
610 while (reg) {
611 unsigned int index = find_first_bit(&reg, 32);
612 unsigned int irq;
613
614 /* clear the interrupt */
615 pci_write_reg(pcie, 1 << index, PCIEMSIFR);
616
617 irq = irq_find_mapping(msi->domain, index);
618 if (irq) {
619 if (test_bit(index, msi->used))
620 generic_handle_irq(irq);
621 else
622 dev_info(pcie->dev, "unhandled MSI\n");
623 } else {
624 /* Unknown MSI, just clear it */
625 dev_dbg(pcie->dev, "unexpected MSI\n");
626 }
627
628 /* see if there's any more pending in this vector */
629 reg = pci_read_reg(pcie, PCIEMSIFR);
630 }
631
632 return IRQ_HANDLED;
633 }
634
635 static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
636 struct msi_desc *desc)
637 {
638 struct rcar_msi *msi = to_rcar_msi(chip);
639 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
640 struct msi_msg msg;
641 unsigned int irq;
642 int hwirq;
643
644 hwirq = rcar_msi_alloc(msi);
645 if (hwirq < 0)
646 return hwirq;
647
648 irq = irq_create_mapping(msi->domain, hwirq);
649 if (!irq) {
650 rcar_msi_free(msi, hwirq);
651 return -EINVAL;
652 }
653
654 irq_set_msi_desc(irq, desc);
655
656 msg.address_lo = pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
657 msg.address_hi = pci_read_reg(pcie, PCIEMSIAUR);
658 msg.data = hwirq;
659
660 write_msi_msg(irq, &msg);
661
662 return 0;
663 }
664
665 static void rcar_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
666 {
667 struct rcar_msi *msi = to_rcar_msi(chip);
668 struct irq_data *d = irq_get_irq_data(irq);
669
670 rcar_msi_free(msi, d->hwirq);
671 }
672
673 static struct irq_chip rcar_msi_irq_chip = {
674 .name = "R-Car PCIe MSI",
675 .irq_enable = unmask_msi_irq,
676 .irq_disable = mask_msi_irq,
677 .irq_mask = mask_msi_irq,
678 .irq_unmask = unmask_msi_irq,
679 };
680
681 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
682 irq_hw_number_t hwirq)
683 {
684 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
685 irq_set_chip_data(irq, domain->host_data);
686 set_irq_flags(irq, IRQF_VALID);
687
688 return 0;
689 }
690
691 static const struct irq_domain_ops msi_domain_ops = {
692 .map = rcar_msi_map,
693 };
694
695 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
696 {
697 struct platform_device *pdev = to_platform_device(pcie->dev);
698 struct rcar_msi *msi = &pcie->msi;
699 unsigned long base;
700 int err;
701
702 mutex_init(&msi->lock);
703
704 msi->chip.dev = pcie->dev;
705 msi->chip.setup_irq = rcar_msi_setup_irq;
706 msi->chip.teardown_irq = rcar_msi_teardown_irq;
707
708 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
709 &msi_domain_ops, &msi->chip);
710 if (!msi->domain) {
711 dev_err(&pdev->dev, "failed to create IRQ domain\n");
712 return -ENOMEM;
713 }
714
715 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
716 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
717 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
718 if (err < 0) {
719 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
720 goto err;
721 }
722
723 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
724 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
725 if (err < 0) {
726 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
727 goto err;
728 }
729
730 /* setup MSI data target */
731 msi->pages = __get_free_pages(GFP_KERNEL, 0);
732 base = virt_to_phys((void *)msi->pages);
733
734 pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
735 pci_write_reg(pcie, 0, PCIEMSIAUR);
736
737 /* enable all MSI interrupts */
738 pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
739
740 return 0;
741
742 err:
743 irq_domain_remove(msi->domain);
744 return err;
745 }
746
747 static int rcar_pcie_get_resources(struct platform_device *pdev,
748 struct rcar_pcie *pcie)
749 {
750 struct resource res;
751 int err, i;
752
753 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
754 if (err)
755 return err;
756
757 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
758 if (IS_ERR(pcie->clk)) {
759 dev_err(pcie->dev, "cannot get platform clock\n");
760 return PTR_ERR(pcie->clk);
761 }
762 err = clk_prepare_enable(pcie->clk);
763 if (err)
764 goto fail_clk;
765
766 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
767 if (IS_ERR(pcie->bus_clk)) {
768 dev_err(pcie->dev, "cannot get pcie bus clock\n");
769 err = PTR_ERR(pcie->bus_clk);
770 goto fail_clk;
771 }
772 err = clk_prepare_enable(pcie->bus_clk);
773 if (err)
774 goto err_map_reg;
775
776 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
777 if (i < 0) {
778 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
779 err = -ENOENT;
780 goto err_map_reg;
781 }
782 pcie->msi.irq1 = i;
783
784 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
785 if (i < 0) {
786 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
787 err = -ENOENT;
788 goto err_map_reg;
789 }
790 pcie->msi.irq2 = i;
791
792 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
793 if (IS_ERR(pcie->base)) {
794 err = PTR_ERR(pcie->base);
795 goto err_map_reg;
796 }
797
798 return 0;
799
800 err_map_reg:
801 clk_disable_unprepare(pcie->bus_clk);
802 fail_clk:
803 clk_disable_unprepare(pcie->clk);
804
805 return err;
806 }
807
808 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
809 struct of_pci_range *range,
810 int *index)
811 {
812 u64 restype = range->flags;
813 u64 cpu_addr = range->cpu_addr;
814 u64 cpu_end = range->cpu_addr + range->size;
815 u64 pci_addr = range->pci_addr;
816 u32 flags = LAM_64BIT | LAR_ENABLE;
817 u64 mask;
818 u64 size;
819 int idx = *index;
820
821 if (restype & IORESOURCE_PREFETCH)
822 flags |= LAM_PREFETCH;
823
824 /*
825 * If the size of the range is larger than the alignment of the start
826 * address, we have to use multiple entries to perform the mapping.
827 */
828 if (cpu_addr > 0) {
829 unsigned long nr_zeros = __ffs64(cpu_addr);
830 u64 alignment = 1ULL << nr_zeros;
831 size = min(range->size, alignment);
832 } else {
833 size = range->size;
834 }
835 /* Hardware supports max 4GiB inbound region */
836 size = min(size, 1ULL << 32);
837
838 mask = roundup_pow_of_two(size) - 1;
839 mask &= ~0xf;
840
841 while (cpu_addr < cpu_end) {
842 /*
843 * Set up 64-bit inbound regions as the range parser doesn't
844 * distinguish between 32 and 64-bit types.
845 */
846 pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
847 pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
848 pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
849
850 pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
851 pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
852 pci_write_reg(pcie, 0, PCIELAMR(idx+1));
853
854 pci_addr += size;
855 cpu_addr += size;
856 idx += 2;
857
858 if (idx > MAX_NR_INBOUND_MAPS) {
859 dev_err(pcie->dev, "Failed to map inbound regions!\n");
860 return -EINVAL;
861 }
862 }
863 *index = idx;
864
865 return 0;
866 }
867
868 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
869 struct device_node *node)
870 {
871 const int na = 3, ns = 2;
872 int rlen;
873
874 parser->node = node;
875 parser->pna = of_n_addr_cells(node);
876 parser->np = parser->pna + na + ns;
877
878 parser->range = of_get_property(node, "dma-ranges", &rlen);
879 if (!parser->range)
880 return -ENOENT;
881
882 parser->end = parser->range + rlen / sizeof(__be32);
883 return 0;
884 }
885
886 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
887 struct device_node *np)
888 {
889 struct of_pci_range range;
890 struct of_pci_range_parser parser;
891 int index = 0;
892 int err;
893
894 if (pci_dma_range_parser_init(&parser, np))
895 return -EINVAL;
896
897 /* Get the dma-ranges from DT */
898 for_each_of_pci_range(&parser, &range) {
899 u64 end = range.cpu_addr + range.size - 1;
900 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
901 range.flags, range.cpu_addr, end, range.pci_addr);
902
903 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
904 if (err)
905 return err;
906 }
907
908 return 0;
909 }
910
911 static const struct of_device_id rcar_pcie_of_match[] = {
912 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
913 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
914 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
915 {},
916 };
917 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
918
919 static int rcar_pcie_probe(struct platform_device *pdev)
920 {
921 struct rcar_pcie *pcie;
922 unsigned int data;
923 struct of_pci_range range;
924 struct of_pci_range_parser parser;
925 const struct of_device_id *of_id;
926 int err, win = 0;
927 int (*hw_init_fn)(struct rcar_pcie *);
928
929 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
930 if (!pcie)
931 return -ENOMEM;
932
933 pcie->dev = &pdev->dev;
934 platform_set_drvdata(pdev, pcie);
935
936 /* Get the bus range */
937 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
938 dev_err(&pdev->dev, "failed to parse bus-range property\n");
939 return -EINVAL;
940 }
941
942 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
943 dev_err(&pdev->dev, "missing ranges property\n");
944 return -EINVAL;
945 }
946
947 err = rcar_pcie_get_resources(pdev, pcie);
948 if (err < 0) {
949 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
950 return err;
951 }
952
953 for_each_of_pci_range(&parser, &range) {
954 of_pci_range_to_resource(&range, pdev->dev.of_node,
955 &pcie->res[win++]);
956
957 if (win > PCI_MAX_RESOURCES)
958 break;
959 }
960
961 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
962 if (err)
963 return err;
964
965 if (IS_ENABLED(CONFIG_PCI_MSI)) {
966 err = rcar_pcie_enable_msi(pcie);
967 if (err < 0) {
968 dev_err(&pdev->dev,
969 "failed to enable MSI support: %d\n",
970 err);
971 return err;
972 }
973 }
974
975 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
976 if (!of_id || !of_id->data)
977 return -EINVAL;
978 hw_init_fn = of_id->data;
979
980 /* Failure to get a link might just be that no cards are inserted */
981 err = hw_init_fn(pcie);
982 if (err) {
983 dev_info(&pdev->dev, "PCIe link down\n");
984 return 0;
985 }
986
987 data = pci_read_reg(pcie, MACSR);
988 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
989
990 rcar_pcie_enable(pcie);
991
992 return 0;
993 }
994
995 static struct platform_driver rcar_pcie_driver = {
996 .driver = {
997 .name = DRV_NAME,
998 .owner = THIS_MODULE,
999 .of_match_table = rcar_pcie_of_match,
1000 .suppress_bind_attrs = true,
1001 },
1002 .probe = rcar_pcie_probe,
1003 };
1004 module_platform_driver(rcar_pcie_driver);
1005
1006 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1007 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1008 MODULE_LICENSE("GPLv2");
Linux kernel - Deliverables
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