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PCI: rcar: Remove redundant config accessor register number checks
[deliverable/linux.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPARL(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPARH(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_chip chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119 };
120
121 static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
122 {
123 return container_of(chip, struct rcar_msi, chip);
124 }
125
126 /* Structure representing the PCIe interface */
127 struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
130 struct resource res[PCI_MAX_RESOURCES];
131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
135 struct rcar_msi msi;
136 };
137
138 static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139 {
140 return sys->private_data;
141 }
142
143 static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
149 static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
150 {
151 return readl(pcie->base + reg);
152 }
153
154 enum {
155 PCI_ACCESS_READ,
156 PCI_ACCESS_WRITE,
157 };
158
159 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
160 {
161 int shift = 8 * (where & 3);
162 u32 val = pci_read_reg(pcie, where & ~3);
163
164 val &= ~(mask << shift);
165 val |= data << shift;
166 pci_write_reg(pcie, val, where & ~3);
167 }
168
169 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
170 {
171 int shift = 8 * (where & 3);
172 u32 val = pci_read_reg(pcie, where & ~3);
173
174 return val >> shift;
175 }
176
177 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
178 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
179 unsigned char access_type, struct pci_bus *bus,
180 unsigned int devfn, int where, u32 *data)
181 {
182 int dev, func, reg, index;
183
184 dev = PCI_SLOT(devfn);
185 func = PCI_FUNC(devfn);
186 reg = where & ~3;
187 index = reg / 4;
188
189 /*
190 * While each channel has its own memory-mapped extended config
191 * space, it's generally only accessible when in endpoint mode.
192 * When in root complex mode, the controller is unable to target
193 * itself with either type 0 or type 1 accesses, and indeed, any
194 * controller initiated target transfer to its own config space
195 * result in a completer abort.
196 *
197 * Each channel effectively only supports a single device, but as
198 * the same channel <-> device access works for any PCI_SLOT()
199 * value, we cheat a bit here and bind the controller's config
200 * space to devfn 0 in order to enable self-enumeration. In this
201 * case the regular ECAR/ECDR path is sidelined and the mangled
202 * config access itself is initiated as an internal bus transaction.
203 */
204 if (pci_is_root_bus(bus)) {
205 if (dev != 0)
206 return PCIBIOS_DEVICE_NOT_FOUND;
207
208 if (access_type == PCI_ACCESS_READ) {
209 *data = pci_read_reg(pcie, PCICONF(index));
210 } else {
211 /* Keep an eye out for changes to the root bus number */
212 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
213 pcie->root_bus_nr = *data & 0xff;
214
215 pci_write_reg(pcie, *data, PCICONF(index));
216 }
217
218 return PCIBIOS_SUCCESSFUL;
219 }
220
221 if (pcie->root_bus_nr < 0)
222 return PCIBIOS_DEVICE_NOT_FOUND;
223
224 /* Clear errors */
225 pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
226
227 /* Set the PIO address */
228 pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
229 PCIE_CONF_FUNC(func) | reg, PCIECAR);
230
231 /* Enable the configuration access */
232 if (bus->parent->number == pcie->root_bus_nr)
233 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
234 else
235 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
236
237 /* Check for errors */
238 if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 /* Check for master and target aborts */
242 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
243 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
244 return PCIBIOS_DEVICE_NOT_FOUND;
245
246 if (access_type == PCI_ACCESS_READ)
247 *data = pci_read_reg(pcie, PCIECDR);
248 else
249 pci_write_reg(pcie, *data, PCIECDR);
250
251 /* Disable the configuration access */
252 pci_write_reg(pcie, 0, PCIECCTLR);
253
254 return PCIBIOS_SUCCESSFUL;
255 }
256
257 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
258 int where, int size, u32 *val)
259 {
260 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
261 int ret;
262
263 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
264 bus, devfn, where, val);
265 if (ret != PCIBIOS_SUCCESSFUL) {
266 *val = 0xffffffff;
267 return ret;
268 }
269
270 if (size == 1)
271 *val = (*val >> (8 * (where & 3))) & 0xff;
272 else if (size == 2)
273 *val = (*val >> (8 * (where & 2))) & 0xffff;
274
275 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
276 bus->number, devfn, where, size, (unsigned long)*val);
277
278 return ret;
279 }
280
281 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
282 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
283 int where, int size, u32 val)
284 {
285 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
286 int shift, ret;
287 u32 data;
288
289 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
290 bus, devfn, where, &data);
291 if (ret != PCIBIOS_SUCCESSFUL)
292 return ret;
293
294 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
295 bus->number, devfn, where, size, (unsigned long)val);
296
297 if (size == 1) {
298 shift = 8 * (where & 3);
299 data &= ~(0xff << shift);
300 data |= ((val & 0xff) << shift);
301 } else if (size == 2) {
302 shift = 8 * (where & 2);
303 data &= ~(0xffff << shift);
304 data |= ((val & 0xffff) << shift);
305 } else
306 data = val;
307
308 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
309 bus, devfn, where, &data);
310
311 return ret;
312 }
313
314 static struct pci_ops rcar_pcie_ops = {
315 .read = rcar_pcie_read_conf,
316 .write = rcar_pcie_write_conf,
317 };
318
319 static void rcar_pcie_setup_window(int win, struct resource *res,
320 struct rcar_pcie *pcie)
321 {
322 /* Setup PCIe address space mappings for each resource */
323 resource_size_t size;
324 u32 mask;
325
326 pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
327
328 /*
329 * The PAMR mask is calculated in units of 128Bytes, which
330 * keeps things pretty simple.
331 */
332 size = resource_size(res);
333 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
334 pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
335
336 pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
337 pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
338
339 /* First resource is for IO */
340 mask = PAR_ENABLE;
341 if (res->flags & IORESOURCE_IO)
342 mask |= IO_SPACE;
343
344 pci_write_reg(pcie, mask, PCIEPTCTLR(win));
345 }
346
347 static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
348 {
349 struct rcar_pcie *pcie = sys_to_pcie(sys);
350 struct resource *res;
351 int i;
352
353 pcie->root_bus_nr = -1;
354
355 /* Setup PCI resources */
356 for (i = 0; i < PCI_MAX_RESOURCES; i++) {
357
358 res = &pcie->res[i];
359 if (!res->flags)
360 continue;
361
362 rcar_pcie_setup_window(i, res, pcie);
363
364 if (res->flags & IORESOURCE_IO)
365 pci_ioremap_io(nr * SZ_64K, res->start);
366 else
367 pci_add_resource(&sys->resources, res);
368 }
369 pci_add_resource(&sys->resources, &pcie->busn);
370
371 return 1;
372 }
373
374 static void rcar_pcie_add_bus(struct pci_bus *bus)
375 {
376 if (IS_ENABLED(CONFIG_PCI_MSI)) {
377 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
378
379 bus->msi = &pcie->msi.chip;
380 }
381 }
382
383 struct hw_pci rcar_pci = {
384 .setup = rcar_pcie_setup,
385 .map_irq = of_irq_parse_and_map_pci,
386 .ops = &rcar_pcie_ops,
387 .add_bus = rcar_pcie_add_bus,
388 };
389
390 static void rcar_pcie_enable(struct rcar_pcie *pcie)
391 {
392 struct platform_device *pdev = to_platform_device(pcie->dev);
393
394 rcar_pci.nr_controllers = 1;
395 rcar_pci.private_data = (void **)&pcie;
396
397 pci_common_init_dev(&pdev->dev, &rcar_pci);
398 #ifdef CONFIG_PCI_DOMAINS
399 rcar_pci.domain++;
400 #endif
401 }
402
403 static int phy_wait_for_ack(struct rcar_pcie *pcie)
404 {
405 unsigned int timeout = 100;
406
407 while (timeout--) {
408 if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
409 return 0;
410
411 udelay(100);
412 }
413
414 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
415
416 return -ETIMEDOUT;
417 }
418
419 static void phy_write_reg(struct rcar_pcie *pcie,
420 unsigned int rate, unsigned int addr,
421 unsigned int lane, unsigned int data)
422 {
423 unsigned long phyaddr;
424
425 phyaddr = WRITE_CMD |
426 ((rate & 1) << RATE_POS) |
427 ((lane & 0xf) << LANE_POS) |
428 ((addr & 0xff) << ADR_POS);
429
430 /* Set write data */
431 pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
432 pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
433
434 /* Ignore errors as they will be dealt with if the data link is down */
435 phy_wait_for_ack(pcie);
436
437 /* Clear command */
438 pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
439 pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
440
441 /* Ignore errors as they will be dealt with if the data link is down */
442 phy_wait_for_ack(pcie);
443 }
444
445 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
446 {
447 unsigned int timeout = 10;
448
449 while (timeout--) {
450 if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
451 return 0;
452
453 msleep(5);
454 }
455
456 return -ETIMEDOUT;
457 }
458
459 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
460 {
461 int err;
462
463 /* Begin initialization */
464 pci_write_reg(pcie, 0, PCIETCTLR);
465
466 /* Set mode */
467 pci_write_reg(pcie, 1, PCIEMSR);
468
469 /*
470 * Initial header for port config space is type 1, set the device
471 * class to match. Hardware takes care of propagating the IDSETR
472 * settings, so there is no need to bother with a quirk.
473 */
474 pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
475
476 /*
477 * Setup Secondary Bus Number & Subordinate Bus Number, even though
478 * they aren't used, to avoid bridge being detected as broken.
479 */
480 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
481 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
482
483 /* Initialize default capabilities. */
484 rcar_rmw32(pcie, REXPCAP(0), 0, PCI_CAP_ID_EXP);
485 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
486 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
487 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
488 PCI_HEADER_TYPE_BRIDGE);
489
490 /* Enable data link layer active state reporting */
491 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), 0, PCI_EXP_LNKCAP_DLLLARC);
492
493 /* Write out the physical slot number = 0 */
494 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
495
496 /* Set the completion timer timeout to the maximum 50ms. */
497 rcar_rmw32(pcie, TLCTLR+1, 0x3f, 50);
498
499 /* Terminate list of capabilities (Next Capability Offset=0) */
500 rcar_rmw32(pcie, RVCCAP(0), 0xfff0, 0);
501
502 /* Enable MAC data scrambling. */
503 rcar_rmw32(pcie, MACCTLR, SCRAMBLE_DISABLE, 0);
504
505 /* Enable MSI */
506 if (IS_ENABLED(CONFIG_PCI_MSI))
507 pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
508
509 /* Finish initialization - establish a PCI Express link */
510 pci_write_reg(pcie, CFINIT, PCIETCTLR);
511
512 /* This will timeout if we don't have a link. */
513 err = rcar_pcie_wait_for_dl(pcie);
514 if (err)
515 return err;
516
517 /* Enable INTx interrupts */
518 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
519
520 /* Enable slave Bus Mastering */
521 rcar_rmw32(pcie, RCONF(PCI_STATUS), PCI_STATUS_DEVSEL_MASK,
522 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
523 PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST);
524
525 wmb();
526
527 return 0;
528 }
529
530 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
531 {
532 unsigned int timeout = 10;
533
534 /* Initialize the phy */
535 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
536 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
537 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
538 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
539 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
540 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
541 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
542 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
543 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
544 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
545 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
546 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
547
548 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
549 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
550 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
551
552 while (timeout--) {
553 if (pci_read_reg(pcie, H1_PCIEPHYSR))
554 return rcar_pcie_hw_init(pcie);
555
556 msleep(5);
557 }
558
559 return -ETIMEDOUT;
560 }
561
562 static int rcar_msi_alloc(struct rcar_msi *chip)
563 {
564 int msi;
565
566 mutex_lock(&chip->lock);
567
568 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
569 if (msi < INT_PCI_MSI_NR)
570 set_bit(msi, chip->used);
571 else
572 msi = -ENOSPC;
573
574 mutex_unlock(&chip->lock);
575
576 return msi;
577 }
578
579 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
580 {
581 mutex_lock(&chip->lock);
582 clear_bit(irq, chip->used);
583 mutex_unlock(&chip->lock);
584 }
585
586 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
587 {
588 struct rcar_pcie *pcie = data;
589 struct rcar_msi *msi = &pcie->msi;
590 unsigned long reg;
591
592 reg = pci_read_reg(pcie, PCIEMSIFR);
593
594 /* MSI & INTx share an interrupt - we only handle MSI here */
595 if (!reg)
596 return IRQ_NONE;
597
598 while (reg) {
599 unsigned int index = find_first_bit(&reg, 32);
600 unsigned int irq;
601
602 /* clear the interrupt */
603 pci_write_reg(pcie, 1 << index, PCIEMSIFR);
604
605 irq = irq_find_mapping(msi->domain, index);
606 if (irq) {
607 if (test_bit(index, msi->used))
608 generic_handle_irq(irq);
609 else
610 dev_info(pcie->dev, "unhandled MSI\n");
611 } else {
612 /* Unknown MSI, just clear it */
613 dev_dbg(pcie->dev, "unexpected MSI\n");
614 }
615
616 /* see if there's any more pending in this vector */
617 reg = pci_read_reg(pcie, PCIEMSIFR);
618 }
619
620 return IRQ_HANDLED;
621 }
622
623 static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
624 struct msi_desc *desc)
625 {
626 struct rcar_msi *msi = to_rcar_msi(chip);
627 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
628 struct msi_msg msg;
629 unsigned int irq;
630 int hwirq;
631
632 hwirq = rcar_msi_alloc(msi);
633 if (hwirq < 0)
634 return hwirq;
635
636 irq = irq_create_mapping(msi->domain, hwirq);
637 if (!irq) {
638 rcar_msi_free(msi, hwirq);
639 return -EINVAL;
640 }
641
642 irq_set_msi_desc(irq, desc);
643
644 msg.address_lo = pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
645 msg.address_hi = pci_read_reg(pcie, PCIEMSIAUR);
646 msg.data = hwirq;
647
648 write_msi_msg(irq, &msg);
649
650 return 0;
651 }
652
653 static void rcar_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
654 {
655 struct rcar_msi *msi = to_rcar_msi(chip);
656 struct irq_data *d = irq_get_irq_data(irq);
657
658 rcar_msi_free(msi, d->hwirq);
659 }
660
661 static struct irq_chip rcar_msi_irq_chip = {
662 .name = "R-Car PCIe MSI",
663 .irq_enable = unmask_msi_irq,
664 .irq_disable = mask_msi_irq,
665 .irq_mask = mask_msi_irq,
666 .irq_unmask = unmask_msi_irq,
667 };
668
669 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
670 irq_hw_number_t hwirq)
671 {
672 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
673 irq_set_chip_data(irq, domain->host_data);
674 set_irq_flags(irq, IRQF_VALID);
675
676 return 0;
677 }
678
679 static const struct irq_domain_ops msi_domain_ops = {
680 .map = rcar_msi_map,
681 };
682
683 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
684 {
685 struct platform_device *pdev = to_platform_device(pcie->dev);
686 struct rcar_msi *msi = &pcie->msi;
687 unsigned long base;
688 int err;
689
690 mutex_init(&msi->lock);
691
692 msi->chip.dev = pcie->dev;
693 msi->chip.setup_irq = rcar_msi_setup_irq;
694 msi->chip.teardown_irq = rcar_msi_teardown_irq;
695
696 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
697 &msi_domain_ops, &msi->chip);
698 if (!msi->domain) {
699 dev_err(&pdev->dev, "failed to create IRQ domain\n");
700 return -ENOMEM;
701 }
702
703 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
704 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
705 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
706 if (err < 0) {
707 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
708 goto err;
709 }
710
711 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
712 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
713 if (err < 0) {
714 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
715 goto err;
716 }
717
718 /* setup MSI data target */
719 msi->pages = __get_free_pages(GFP_KERNEL, 0);
720 base = virt_to_phys((void *)msi->pages);
721
722 pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
723 pci_write_reg(pcie, 0, PCIEMSIAUR);
724
725 /* enable all MSI interrupts */
726 pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
727
728 return 0;
729
730 err:
731 irq_domain_remove(msi->domain);
732 return err;
733 }
734
735 static int rcar_pcie_get_resources(struct platform_device *pdev,
736 struct rcar_pcie *pcie)
737 {
738 struct resource res;
739 int err, i;
740
741 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
742 if (err)
743 return err;
744
745 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
746 if (IS_ERR(pcie->clk)) {
747 dev_err(pcie->dev, "cannot get platform clock\n");
748 return PTR_ERR(pcie->clk);
749 }
750 err = clk_prepare_enable(pcie->clk);
751 if (err)
752 goto fail_clk;
753
754 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
755 if (IS_ERR(pcie->bus_clk)) {
756 dev_err(pcie->dev, "cannot get pcie bus clock\n");
757 err = PTR_ERR(pcie->bus_clk);
758 goto fail_clk;
759 }
760 err = clk_prepare_enable(pcie->bus_clk);
761 if (err)
762 goto err_map_reg;
763
764 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
765 if (i < 0) {
766 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
767 err = -ENOENT;
768 goto err_map_reg;
769 }
770 pcie->msi.irq1 = i;
771
772 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
773 if (i < 0) {
774 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
775 err = -ENOENT;
776 goto err_map_reg;
777 }
778 pcie->msi.irq2 = i;
779
780 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
781 if (IS_ERR(pcie->base)) {
782 err = PTR_ERR(pcie->base);
783 goto err_map_reg;
784 }
785
786 return 0;
787
788 err_map_reg:
789 clk_disable_unprepare(pcie->bus_clk);
790 fail_clk:
791 clk_disable_unprepare(pcie->clk);
792
793 return err;
794 }
795
796 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
797 struct of_pci_range *range,
798 int *index)
799 {
800 u64 restype = range->flags;
801 u64 cpu_addr = range->cpu_addr;
802 u64 cpu_end = range->cpu_addr + range->size;
803 u64 pci_addr = range->pci_addr;
804 u32 flags = LAM_64BIT | LAR_ENABLE;
805 u64 mask;
806 u64 size;
807 int idx = *index;
808
809 if (restype & IORESOURCE_PREFETCH)
810 flags |= LAM_PREFETCH;
811
812 /*
813 * If the size of the range is larger than the alignment of the start
814 * address, we have to use multiple entries to perform the mapping.
815 */
816 if (cpu_addr > 0) {
817 unsigned long nr_zeros = __ffs64(cpu_addr);
818 u64 alignment = 1ULL << nr_zeros;
819 size = min(range->size, alignment);
820 } else {
821 size = range->size;
822 }
823 /* Hardware supports max 4GiB inbound region */
824 size = min(size, 1ULL << 32);
825
826 mask = roundup_pow_of_two(size) - 1;
827 mask &= ~0xf;
828
829 while (cpu_addr < cpu_end) {
830 /*
831 * Set up 64-bit inbound regions as the range parser doesn't
832 * distinguish between 32 and 64-bit types.
833 */
834 pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
835 pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
836 pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
837
838 pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
839 pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
840 pci_write_reg(pcie, 0, PCIELAMR(idx+1));
841
842 pci_addr += size;
843 cpu_addr += size;
844 idx += 2;
845
846 if (idx > MAX_NR_INBOUND_MAPS) {
847 dev_err(pcie->dev, "Failed to map inbound regions!\n");
848 return -EINVAL;
849 }
850 }
851 *index = idx;
852
853 return 0;
854 }
855
856 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
857 struct device_node *node)
858 {
859 const int na = 3, ns = 2;
860 int rlen;
861
862 parser->node = node;
863 parser->pna = of_n_addr_cells(node);
864 parser->np = parser->pna + na + ns;
865
866 parser->range = of_get_property(node, "dma-ranges", &rlen);
867 if (!parser->range)
868 return -ENOENT;
869
870 parser->end = parser->range + rlen / sizeof(__be32);
871 return 0;
872 }
873
874 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
875 struct device_node *np)
876 {
877 struct of_pci_range range;
878 struct of_pci_range_parser parser;
879 int index = 0;
880 int err;
881
882 if (pci_dma_range_parser_init(&parser, np))
883 return -EINVAL;
884
885 /* Get the dma-ranges from DT */
886 for_each_of_pci_range(&parser, &range) {
887 u64 end = range.cpu_addr + range.size - 1;
888 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
889 range.flags, range.cpu_addr, end, range.pci_addr);
890
891 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
892 if (err)
893 return err;
894 }
895
896 return 0;
897 }
898
899 static const struct of_device_id rcar_pcie_of_match[] = {
900 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
901 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
902 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
903 {},
904 };
905 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
906
907 static int rcar_pcie_probe(struct platform_device *pdev)
908 {
909 struct rcar_pcie *pcie;
910 unsigned int data;
911 struct of_pci_range range;
912 struct of_pci_range_parser parser;
913 const struct of_device_id *of_id;
914 int err, win = 0;
915 int (*hw_init_fn)(struct rcar_pcie *);
916
917 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
918 if (!pcie)
919 return -ENOMEM;
920
921 pcie->dev = &pdev->dev;
922 platform_set_drvdata(pdev, pcie);
923
924 /* Get the bus range */
925 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
926 dev_err(&pdev->dev, "failed to parse bus-range property\n");
927 return -EINVAL;
928 }
929
930 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
931 dev_err(&pdev->dev, "missing ranges property\n");
932 return -EINVAL;
933 }
934
935 err = rcar_pcie_get_resources(pdev, pcie);
936 if (err < 0) {
937 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
938 return err;
939 }
940
941 for_each_of_pci_range(&parser, &range) {
942 of_pci_range_to_resource(&range, pdev->dev.of_node,
943 &pcie->res[win++]);
944
945 if (win > PCI_MAX_RESOURCES)
946 break;
947 }
948
949 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
950 if (err)
951 return err;
952
953 if (IS_ENABLED(CONFIG_PCI_MSI)) {
954 err = rcar_pcie_enable_msi(pcie);
955 if (err < 0) {
956 dev_err(&pdev->dev,
957 "failed to enable MSI support: %d\n",
958 err);
959 return err;
960 }
961 }
962
963 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
964 if (!of_id || !of_id->data)
965 return -EINVAL;
966 hw_init_fn = of_id->data;
967
968 /* Failure to get a link might just be that no cards are inserted */
969 err = hw_init_fn(pcie);
970 if (err) {
971 dev_info(&pdev->dev, "PCIe link down\n");
972 return 0;
973 }
974
975 data = pci_read_reg(pcie, MACSR);
976 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
977
978 rcar_pcie_enable(pcie);
979
980 return 0;
981 }
982
983 static struct platform_driver rcar_pcie_driver = {
984 .driver = {
985 .name = DRV_NAME,
986 .owner = THIS_MODULE,
987 .of_match_table = rcar_pcie_of_match,
988 .suppress_bind_attrs = true,
989 },
990 .probe = rcar_pcie_probe,
991 };
992 module_platform_driver(rcar_pcie_driver);
993
994 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
995 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
996 MODULE_LICENSE("GPLv2");
Linux kernel - Deliverables
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