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Merge tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette...
[deliverable/linux.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPARL(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPARH(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_chip chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119 };
120
121 static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
122 {
123 return container_of(chip, struct rcar_msi, chip);
124 }
125
126 /* Structure representing the PCIe interface */
127 struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
130 struct resource res[PCI_MAX_RESOURCES];
131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
135 struct rcar_msi msi;
136 };
137
138 static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139 {
140 return sys->private_data;
141 }
142
143 static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
149 static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
150 {
151 return readl(pcie->base + reg);
152 }
153
154 enum {
155 PCI_ACCESS_READ,
156 PCI_ACCESS_WRITE,
157 };
158
159 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
160 {
161 int shift = 8 * (where & 3);
162 u32 val = pci_read_reg(pcie, where & ~3);
163
164 val &= ~(mask << shift);
165 val |= data << shift;
166 pci_write_reg(pcie, val, where & ~3);
167 }
168
169 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
170 {
171 int shift = 8 * (where & 3);
172 u32 val = pci_read_reg(pcie, where & ~3);
173
174 return val >> shift;
175 }
176
177 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
178 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
179 unsigned char access_type, struct pci_bus *bus,
180 unsigned int devfn, int where, u32 *data)
181 {
182 int dev, func, reg, index;
183
184 dev = PCI_SLOT(devfn);
185 func = PCI_FUNC(devfn);
186 reg = where & ~3;
187 index = reg / 4;
188
189 /*
190 * While each channel has its own memory-mapped extended config
191 * space, it's generally only accessible when in endpoint mode.
192 * When in root complex mode, the controller is unable to target
193 * itself with either type 0 or type 1 accesses, and indeed, any
194 * controller initiated target transfer to its own config space
195 * result in a completer abort.
196 *
197 * Each channel effectively only supports a single device, but as
198 * the same channel <-> device access works for any PCI_SLOT()
199 * value, we cheat a bit here and bind the controller's config
200 * space to devfn 0 in order to enable self-enumeration. In this
201 * case the regular ECAR/ECDR path is sidelined and the mangled
202 * config access itself is initiated as an internal bus transaction.
203 */
204 if (pci_is_root_bus(bus)) {
205 if (dev != 0)
206 return PCIBIOS_DEVICE_NOT_FOUND;
207
208 if (access_type == PCI_ACCESS_READ) {
209 *data = pci_read_reg(pcie, PCICONF(index));
210 } else {
211 /* Keep an eye out for changes to the root bus number */
212 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
213 pcie->root_bus_nr = *data & 0xff;
214
215 pci_write_reg(pcie, *data, PCICONF(index));
216 }
217
218 return PCIBIOS_SUCCESSFUL;
219 }
220
221 if (pcie->root_bus_nr < 0)
222 return PCIBIOS_DEVICE_NOT_FOUND;
223
224 /* Clear errors */
225 pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
226
227 /* Set the PIO address */
228 pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
229 PCIE_CONF_FUNC(func) | reg, PCIECAR);
230
231 /* Enable the configuration access */
232 if (bus->parent->number == pcie->root_bus_nr)
233 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
234 else
235 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
236
237 /* Check for errors */
238 if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 /* Check for master and target aborts */
242 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
243 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
244 return PCIBIOS_DEVICE_NOT_FOUND;
245
246 if (access_type == PCI_ACCESS_READ)
247 *data = pci_read_reg(pcie, PCIECDR);
248 else
249 pci_write_reg(pcie, *data, PCIECDR);
250
251 /* Disable the configuration access */
252 pci_write_reg(pcie, 0, PCIECCTLR);
253
254 return PCIBIOS_SUCCESSFUL;
255 }
256
257 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
258 int where, int size, u32 *val)
259 {
260 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
261 int ret;
262
263 if ((size == 2) && (where & 1))
264 return PCIBIOS_BAD_REGISTER_NUMBER;
265 else if ((size == 4) && (where & 3))
266 return PCIBIOS_BAD_REGISTER_NUMBER;
267
268 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
269 bus, devfn, where, val);
270 if (ret != PCIBIOS_SUCCESSFUL) {
271 *val = 0xffffffff;
272 return ret;
273 }
274
275 if (size == 1)
276 *val = (*val >> (8 * (where & 3))) & 0xff;
277 else if (size == 2)
278 *val = (*val >> (8 * (where & 2))) & 0xffff;
279
280 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
281 bus->number, devfn, where, size, (unsigned long)*val);
282
283 return ret;
284 }
285
286 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
287 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
288 int where, int size, u32 val)
289 {
290 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
291 int shift, ret;
292 u32 data;
293
294 if ((size == 2) && (where & 1))
295 return PCIBIOS_BAD_REGISTER_NUMBER;
296 else if ((size == 4) && (where & 3))
297 return PCIBIOS_BAD_REGISTER_NUMBER;
298
299 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
300 bus, devfn, where, &data);
301 if (ret != PCIBIOS_SUCCESSFUL)
302 return ret;
303
304 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
305 bus->number, devfn, where, size, (unsigned long)val);
306
307 if (size == 1) {
308 shift = 8 * (where & 3);
309 data &= ~(0xff << shift);
310 data |= ((val & 0xff) << shift);
311 } else if (size == 2) {
312 shift = 8 * (where & 2);
313 data &= ~(0xffff << shift);
314 data |= ((val & 0xffff) << shift);
315 } else
316 data = val;
317
318 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
319 bus, devfn, where, &data);
320
321 return ret;
322 }
323
324 static struct pci_ops rcar_pcie_ops = {
325 .read = rcar_pcie_read_conf,
326 .write = rcar_pcie_write_conf,
327 };
328
329 static void rcar_pcie_setup_window(int win, struct resource *res,
330 struct rcar_pcie *pcie)
331 {
332 /* Setup PCIe address space mappings for each resource */
333 resource_size_t size;
334 u32 mask;
335
336 pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
337
338 /*
339 * The PAMR mask is calculated in units of 128Bytes, which
340 * keeps things pretty simple.
341 */
342 size = resource_size(res);
343 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
344 pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
345
346 pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
347 pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
348
349 /* First resource is for IO */
350 mask = PAR_ENABLE;
351 if (res->flags & IORESOURCE_IO)
352 mask |= IO_SPACE;
353
354 pci_write_reg(pcie, mask, PCIEPTCTLR(win));
355 }
356
357 static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
358 {
359 struct rcar_pcie *pcie = sys_to_pcie(sys);
360 struct resource *res;
361 int i;
362
363 pcie->root_bus_nr = -1;
364
365 /* Setup PCI resources */
366 for (i = 0; i < PCI_MAX_RESOURCES; i++) {
367
368 res = &pcie->res[i];
369 if (!res->flags)
370 continue;
371
372 rcar_pcie_setup_window(i, res, pcie);
373
374 if (res->flags & IORESOURCE_IO)
375 pci_ioremap_io(nr * SZ_64K, res->start);
376 else
377 pci_add_resource(&sys->resources, res);
378 }
379 pci_add_resource(&sys->resources, &pcie->busn);
380
381 return 1;
382 }
383
384 static void rcar_pcie_add_bus(struct pci_bus *bus)
385 {
386 if (IS_ENABLED(CONFIG_PCI_MSI)) {
387 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
388
389 bus->msi = &pcie->msi.chip;
390 }
391 }
392
393 struct hw_pci rcar_pci = {
394 .setup = rcar_pcie_setup,
395 .map_irq = of_irq_parse_and_map_pci,
396 .ops = &rcar_pcie_ops,
397 .add_bus = rcar_pcie_add_bus,
398 };
399
400 static void rcar_pcie_enable(struct rcar_pcie *pcie)
401 {
402 struct platform_device *pdev = to_platform_device(pcie->dev);
403
404 rcar_pci.nr_controllers = 1;
405 rcar_pci.private_data = (void **)&pcie;
406
407 pci_common_init_dev(&pdev->dev, &rcar_pci);
408 #ifdef CONFIG_PCI_DOMAINS
409 rcar_pci.domain++;
410 #endif
411 }
412
413 static int phy_wait_for_ack(struct rcar_pcie *pcie)
414 {
415 unsigned int timeout = 100;
416
417 while (timeout--) {
418 if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
419 return 0;
420
421 udelay(100);
422 }
423
424 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
425
426 return -ETIMEDOUT;
427 }
428
429 static void phy_write_reg(struct rcar_pcie *pcie,
430 unsigned int rate, unsigned int addr,
431 unsigned int lane, unsigned int data)
432 {
433 unsigned long phyaddr;
434
435 phyaddr = WRITE_CMD |
436 ((rate & 1) << RATE_POS) |
437 ((lane & 0xf) << LANE_POS) |
438 ((addr & 0xff) << ADR_POS);
439
440 /* Set write data */
441 pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
442 pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
443
444 /* Ignore errors as they will be dealt with if the data link is down */
445 phy_wait_for_ack(pcie);
446
447 /* Clear command */
448 pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
449 pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
450
451 /* Ignore errors as they will be dealt with if the data link is down */
452 phy_wait_for_ack(pcie);
453 }
454
455 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
456 {
457 unsigned int timeout = 10;
458
459 while (timeout--) {
460 if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
461 return 0;
462
463 msleep(5);
464 }
465
466 return -ETIMEDOUT;
467 }
468
469 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
470 {
471 int err;
472
473 /* Begin initialization */
474 pci_write_reg(pcie, 0, PCIETCTLR);
475
476 /* Set mode */
477 pci_write_reg(pcie, 1, PCIEMSR);
478
479 /*
480 * Initial header for port config space is type 1, set the device
481 * class to match. Hardware takes care of propagating the IDSETR
482 * settings, so there is no need to bother with a quirk.
483 */
484 pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
485
486 /*
487 * Setup Secondary Bus Number & Subordinate Bus Number, even though
488 * they aren't used, to avoid bridge being detected as broken.
489 */
490 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
491 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
492
493 /* Initialize default capabilities. */
494 rcar_rmw32(pcie, REXPCAP(0), 0, PCI_CAP_ID_EXP);
495 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
496 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
497 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
498 PCI_HEADER_TYPE_BRIDGE);
499
500 /* Enable data link layer active state reporting */
501 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), 0, PCI_EXP_LNKCAP_DLLLARC);
502
503 /* Write out the physical slot number = 0 */
504 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
505
506 /* Set the completion timer timeout to the maximum 50ms. */
507 rcar_rmw32(pcie, TLCTLR+1, 0x3f, 50);
508
509 /* Terminate list of capabilities (Next Capability Offset=0) */
510 rcar_rmw32(pcie, RVCCAP(0), 0xfff0, 0);
511
512 /* Enable MAC data scrambling. */
513 rcar_rmw32(pcie, MACCTLR, SCRAMBLE_DISABLE, 0);
514
515 /* Enable MSI */
516 if (IS_ENABLED(CONFIG_PCI_MSI))
517 pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
518
519 /* Finish initialization - establish a PCI Express link */
520 pci_write_reg(pcie, CFINIT, PCIETCTLR);
521
522 /* This will timeout if we don't have a link. */
523 err = rcar_pcie_wait_for_dl(pcie);
524 if (err)
525 return err;
526
527 /* Enable INTx interrupts */
528 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
529
530 /* Enable slave Bus Mastering */
531 rcar_rmw32(pcie, RCONF(PCI_STATUS), PCI_STATUS_DEVSEL_MASK,
532 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
533 PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST);
534
535 wmb();
536
537 return 0;
538 }
539
540 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
541 {
542 unsigned int timeout = 10;
543
544 /* Initialize the phy */
545 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
546 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
547 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
548 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
549 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
550 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
551 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
552 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
553 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
554 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
555 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
556 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
557
558 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
559 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
560 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
561
562 while (timeout--) {
563 if (pci_read_reg(pcie, H1_PCIEPHYSR))
564 return rcar_pcie_hw_init(pcie);
565
566 msleep(5);
567 }
568
569 return -ETIMEDOUT;
570 }
571
572 static int rcar_msi_alloc(struct rcar_msi *chip)
573 {
574 int msi;
575
576 mutex_lock(&chip->lock);
577
578 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
579 if (msi < INT_PCI_MSI_NR)
580 set_bit(msi, chip->used);
581 else
582 msi = -ENOSPC;
583
584 mutex_unlock(&chip->lock);
585
586 return msi;
587 }
588
589 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
590 {
591 mutex_lock(&chip->lock);
592 clear_bit(irq, chip->used);
593 mutex_unlock(&chip->lock);
594 }
595
596 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
597 {
598 struct rcar_pcie *pcie = data;
599 struct rcar_msi *msi = &pcie->msi;
600 unsigned long reg;
601
602 reg = pci_read_reg(pcie, PCIEMSIFR);
603
604 /* MSI & INTx share an interrupt - we only handle MSI here */
605 if (!reg)
606 return IRQ_NONE;
607
608 while (reg) {
609 unsigned int index = find_first_bit(&reg, 32);
610 unsigned int irq;
611
612 /* clear the interrupt */
613 pci_write_reg(pcie, 1 << index, PCIEMSIFR);
614
615 irq = irq_find_mapping(msi->domain, index);
616 if (irq) {
617 if (test_bit(index, msi->used))
618 generic_handle_irq(irq);
619 else
620 dev_info(pcie->dev, "unhandled MSI\n");
621 } else {
622 /* Unknown MSI, just clear it */
623 dev_dbg(pcie->dev, "unexpected MSI\n");
624 }
625
626 /* see if there's any more pending in this vector */
627 reg = pci_read_reg(pcie, PCIEMSIFR);
628 }
629
630 return IRQ_HANDLED;
631 }
632
633 static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
634 struct msi_desc *desc)
635 {
636 struct rcar_msi *msi = to_rcar_msi(chip);
637 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
638 struct msi_msg msg;
639 unsigned int irq;
640 int hwirq;
641
642 hwirq = rcar_msi_alloc(msi);
643 if (hwirq < 0)
644 return hwirq;
645
646 irq = irq_create_mapping(msi->domain, hwirq);
647 if (!irq) {
648 rcar_msi_free(msi, hwirq);
649 return -EINVAL;
650 }
651
652 irq_set_msi_desc(irq, desc);
653
654 msg.address_lo = pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
655 msg.address_hi = pci_read_reg(pcie, PCIEMSIAUR);
656 msg.data = hwirq;
657
658 write_msi_msg(irq, &msg);
659
660 return 0;
661 }
662
663 static void rcar_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
664 {
665 struct rcar_msi *msi = to_rcar_msi(chip);
666 struct irq_data *d = irq_get_irq_data(irq);
667
668 rcar_msi_free(msi, d->hwirq);
669 }
670
671 static struct irq_chip rcar_msi_irq_chip = {
672 .name = "R-Car PCIe MSI",
673 .irq_enable = unmask_msi_irq,
674 .irq_disable = mask_msi_irq,
675 .irq_mask = mask_msi_irq,
676 .irq_unmask = unmask_msi_irq,
677 };
678
679 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
680 irq_hw_number_t hwirq)
681 {
682 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
683 irq_set_chip_data(irq, domain->host_data);
684 set_irq_flags(irq, IRQF_VALID);
685
686 return 0;
687 }
688
689 static const struct irq_domain_ops msi_domain_ops = {
690 .map = rcar_msi_map,
691 };
692
693 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
694 {
695 struct platform_device *pdev = to_platform_device(pcie->dev);
696 struct rcar_msi *msi = &pcie->msi;
697 unsigned long base;
698 int err;
699
700 mutex_init(&msi->lock);
701
702 msi->chip.dev = pcie->dev;
703 msi->chip.setup_irq = rcar_msi_setup_irq;
704 msi->chip.teardown_irq = rcar_msi_teardown_irq;
705
706 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
707 &msi_domain_ops, &msi->chip);
708 if (!msi->domain) {
709 dev_err(&pdev->dev, "failed to create IRQ domain\n");
710 return -ENOMEM;
711 }
712
713 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
714 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
715 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
716 if (err < 0) {
717 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
718 goto err;
719 }
720
721 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
722 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
723 if (err < 0) {
724 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
725 goto err;
726 }
727
728 /* setup MSI data target */
729 msi->pages = __get_free_pages(GFP_KERNEL, 0);
730 base = virt_to_phys((void *)msi->pages);
731
732 pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
733 pci_write_reg(pcie, 0, PCIEMSIAUR);
734
735 /* enable all MSI interrupts */
736 pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
737
738 return 0;
739
740 err:
741 irq_domain_remove(msi->domain);
742 return err;
743 }
744
745 static int rcar_pcie_get_resources(struct platform_device *pdev,
746 struct rcar_pcie *pcie)
747 {
748 struct resource res;
749 int err, i;
750
751 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
752 if (err)
753 return err;
754
755 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
756 if (IS_ERR(pcie->clk)) {
757 dev_err(pcie->dev, "cannot get platform clock\n");
758 return PTR_ERR(pcie->clk);
759 }
760 err = clk_prepare_enable(pcie->clk);
761 if (err)
762 goto fail_clk;
763
764 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
765 if (IS_ERR(pcie->bus_clk)) {
766 dev_err(pcie->dev, "cannot get pcie bus clock\n");
767 err = PTR_ERR(pcie->bus_clk);
768 goto fail_clk;
769 }
770 err = clk_prepare_enable(pcie->bus_clk);
771 if (err)
772 goto err_map_reg;
773
774 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
775 if (i < 0) {
776 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
777 err = -ENOENT;
778 goto err_map_reg;
779 }
780 pcie->msi.irq1 = i;
781
782 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
783 if (i < 0) {
784 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
785 err = -ENOENT;
786 goto err_map_reg;
787 }
788 pcie->msi.irq2 = i;
789
790 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
791 if (IS_ERR(pcie->base)) {
792 err = PTR_ERR(pcie->base);
793 goto err_map_reg;
794 }
795
796 return 0;
797
798 err_map_reg:
799 clk_disable_unprepare(pcie->bus_clk);
800 fail_clk:
801 clk_disable_unprepare(pcie->clk);
802
803 return err;
804 }
805
806 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
807 struct of_pci_range *range,
808 int *index)
809 {
810 u64 restype = range->flags;
811 u64 cpu_addr = range->cpu_addr;
812 u64 cpu_end = range->cpu_addr + range->size;
813 u64 pci_addr = range->pci_addr;
814 u32 flags = LAM_64BIT | LAR_ENABLE;
815 u64 mask;
816 u64 size;
817 int idx = *index;
818
819 if (restype & IORESOURCE_PREFETCH)
820 flags |= LAM_PREFETCH;
821
822 /*
823 * If the size of the range is larger than the alignment of the start
824 * address, we have to use multiple entries to perform the mapping.
825 */
826 if (cpu_addr > 0) {
827 unsigned long nr_zeros = __ffs64(cpu_addr);
828 u64 alignment = 1ULL << nr_zeros;
829 size = min(range->size, alignment);
830 } else {
831 size = range->size;
832 }
833 /* Hardware supports max 4GiB inbound region */
834 size = min(size, 1ULL << 32);
835
836 mask = roundup_pow_of_two(size) - 1;
837 mask &= ~0xf;
838
839 while (cpu_addr < cpu_end) {
840 /*
841 * Set up 64-bit inbound regions as the range parser doesn't
842 * distinguish between 32 and 64-bit types.
843 */
844 pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
845 pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
846 pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
847
848 pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
849 pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
850 pci_write_reg(pcie, 0, PCIELAMR(idx+1));
851
852 pci_addr += size;
853 cpu_addr += size;
854 idx += 2;
855
856 if (idx > MAX_NR_INBOUND_MAPS) {
857 dev_err(pcie->dev, "Failed to map inbound regions!\n");
858 return -EINVAL;
859 }
860 }
861 *index = idx;
862
863 return 0;
864 }
865
866 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
867 struct device_node *node)
868 {
869 const int na = 3, ns = 2;
870 int rlen;
871
872 parser->node = node;
873 parser->pna = of_n_addr_cells(node);
874 parser->np = parser->pna + na + ns;
875
876 parser->range = of_get_property(node, "dma-ranges", &rlen);
877 if (!parser->range)
878 return -ENOENT;
879
880 parser->end = parser->range + rlen / sizeof(__be32);
881 return 0;
882 }
883
884 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
885 struct device_node *np)
886 {
887 struct of_pci_range range;
888 struct of_pci_range_parser parser;
889 int index = 0;
890 int err;
891
892 if (pci_dma_range_parser_init(&parser, np))
893 return -EINVAL;
894
895 /* Get the dma-ranges from DT */
896 for_each_of_pci_range(&parser, &range) {
897 u64 end = range.cpu_addr + range.size - 1;
898 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
899 range.flags, range.cpu_addr, end, range.pci_addr);
900
901 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
902 if (err)
903 return err;
904 }
905
906 return 0;
907 }
908
909 static const struct of_device_id rcar_pcie_of_match[] = {
910 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
911 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
912 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
913 {},
914 };
915 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
916
917 static int rcar_pcie_probe(struct platform_device *pdev)
918 {
919 struct rcar_pcie *pcie;
920 unsigned int data;
921 struct of_pci_range range;
922 struct of_pci_range_parser parser;
923 const struct of_device_id *of_id;
924 int err, win = 0;
925 int (*hw_init_fn)(struct rcar_pcie *);
926
927 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
928 if (!pcie)
929 return -ENOMEM;
930
931 pcie->dev = &pdev->dev;
932 platform_set_drvdata(pdev, pcie);
933
934 /* Get the bus range */
935 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
936 dev_err(&pdev->dev, "failed to parse bus-range property\n");
937 return -EINVAL;
938 }
939
940 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
941 dev_err(&pdev->dev, "missing ranges property\n");
942 return -EINVAL;
943 }
944
945 err = rcar_pcie_get_resources(pdev, pcie);
946 if (err < 0) {
947 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
948 return err;
949 }
950
951 for_each_of_pci_range(&parser, &range) {
952 of_pci_range_to_resource(&range, pdev->dev.of_node,
953 &pcie->res[win++]);
954
955 if (win > PCI_MAX_RESOURCES)
956 break;
957 }
958
959 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
960 if (err)
961 return err;
962
963 if (IS_ENABLED(CONFIG_PCI_MSI)) {
964 err = rcar_pcie_enable_msi(pcie);
965 if (err < 0) {
966 dev_err(&pdev->dev,
967 "failed to enable MSI support: %d\n",
968 err);
969 return err;
970 }
971 }
972
973 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
974 if (!of_id || !of_id->data)
975 return -EINVAL;
976 hw_init_fn = of_id->data;
977
978 /* Failure to get a link might just be that no cards are inserted */
979 err = hw_init_fn(pcie);
980 if (err) {
981 dev_info(&pdev->dev, "PCIe link down\n");
982 return 0;
983 }
984
985 data = pci_read_reg(pcie, MACSR);
986 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
987
988 rcar_pcie_enable(pcie);
989
990 return 0;
991 }
992
993 static struct platform_driver rcar_pcie_driver = {
994 .driver = {
995 .name = DRV_NAME,
996 .owner = THIS_MODULE,
997 .of_match_table = rcar_pcie_of_match,
998 .suppress_bind_attrs = true,
999 },
1000 .probe = rcar_pcie_probe,
1001 };
1002 module_platform_driver(rcar_pcie_driver);
1003
1004 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1005 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1006 MODULE_LICENSE("GPLv2");
Linux kernel - Deliverables
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