drivers/pci/host/pcie-xilinx.c

   1 /*
   2  * PCIe host controller driver for Xilinx AXI PCIe Bridge
   3  *
   4  * Copyright (c) 2012 - 2014 Xilinx, Inc.
   5  *
   6  * Based on the Tegra PCIe driver
   7  *
   8  * Bits taken from Synopsys Designware Host controller driver and
   9  * ARM PCI Host generic driver.
  10  *
  11  * This program is free software: you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/interrupt.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/msi.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_pci.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/pci.h>
  28 #include <linux/platform_device.h>
  29
  30 /* Register definitions */
  31 #define XILINX_PCIE_REG_BIR             0x00000130
  32 #define XILINX_PCIE_REG_IDR             0x00000138
  33 #define XILINX_PCIE_REG_IMR             0x0000013c
  34 #define XILINX_PCIE_REG_PSCR            0x00000144
  35 #define XILINX_PCIE_REG_RPSC            0x00000148
  36 #define XILINX_PCIE_REG_MSIBASE1        0x0000014c
  37 #define XILINX_PCIE_REG_MSIBASE2        0x00000150
  38 #define XILINX_PCIE_REG_RPEFR           0x00000154
  39 #define XILINX_PCIE_REG_RPIFR1          0x00000158
  40 #define XILINX_PCIE_REG_RPIFR2          0x0000015c
  41
  42 /* Interrupt registers definitions */
  43 #define XILINX_PCIE_INTR_LINK_DOWN      BIT(0)
  44 #define XILINX_PCIE_INTR_ECRC_ERR       BIT(1)
  45 #define XILINX_PCIE_INTR_STR_ERR        BIT(2)
  46 #define XILINX_PCIE_INTR_HOT_RESET      BIT(3)
  47 #define XILINX_PCIE_INTR_CFG_TIMEOUT    BIT(8)
  48 #define XILINX_PCIE_INTR_CORRECTABLE    BIT(9)
  49 #define XILINX_PCIE_INTR_NONFATAL       BIT(10)
  50 #define XILINX_PCIE_INTR_FATAL          BIT(11)
  51 #define XILINX_PCIE_INTR_INTX           BIT(16)
  52 #define XILINX_PCIE_INTR_MSI            BIT(17)
  53 #define XILINX_PCIE_INTR_SLV_UNSUPP     BIT(20)
  54 #define XILINX_PCIE_INTR_SLV_UNEXP      BIT(21)
  55 #define XILINX_PCIE_INTR_SLV_COMPL      BIT(22)
  56 #define XILINX_PCIE_INTR_SLV_ERRP       BIT(23)
  57 #define XILINX_PCIE_INTR_SLV_CMPABT     BIT(24)
  58 #define XILINX_PCIE_INTR_SLV_ILLBUR     BIT(25)
  59 #define XILINX_PCIE_INTR_MST_DECERR     BIT(26)
  60 #define XILINX_PCIE_INTR_MST_SLVERR     BIT(27)
  61 #define XILINX_PCIE_INTR_MST_ERRP       BIT(28)
  62 #define XILINX_PCIE_IMR_ALL_MASK        0x1FF30FED
  63 #define XILINX_PCIE_IDR_ALL_MASK        0xFFFFFFFF
  64
  65 /* Root Port Error FIFO Read Register definitions */
  66 #define XILINX_PCIE_RPEFR_ERR_VALID     BIT(18)
  67 #define XILINX_PCIE_RPEFR_REQ_ID        GENMASK(15, 0)
  68 #define XILINX_PCIE_RPEFR_ALL_MASK      0xFFFFFFFF
  69
  70 /* Root Port Interrupt FIFO Read Register 1 definitions */
  71 #define XILINX_PCIE_RPIFR1_INTR_VALID   BIT(31)
  72 #define XILINX_PCIE_RPIFR1_MSI_INTR     BIT(30)
  73 #define XILINX_PCIE_RPIFR1_INTR_MASK    GENMASK(28, 27)
  74 #define XILINX_PCIE_RPIFR1_ALL_MASK     0xFFFFFFFF
  75 #define XILINX_PCIE_RPIFR1_INTR_SHIFT   27
  76
  77 /* Bridge Info Register definitions */
  78 #define XILINX_PCIE_BIR_ECAM_SZ_MASK    GENMASK(18, 16)
  79 #define XILINX_PCIE_BIR_ECAM_SZ_SHIFT   16
  80
  81 /* Root Port Interrupt FIFO Read Register 2 definitions */
  82 #define XILINX_PCIE_RPIFR2_MSG_DATA     GENMASK(15, 0)
  83
  84 /* Root Port Status/control Register definitions */
  85 #define XILINX_PCIE_REG_RPSC_BEN        BIT(0)
  86
  87 /* Phy Status/Control Register definitions */
  88 #define XILINX_PCIE_REG_PSCR_LNKUP      BIT(11)
  89
  90 /* ECAM definitions */
  91 #define ECAM_BUS_NUM_SHIFT              20
  92 #define ECAM_DEV_NUM_SHIFT              12
  93
  94 /* Number of MSI IRQs */
  95 #define XILINX_NUM_MSI_IRQS             128
  96
  97 /* Number of Memory Resources */
  98 #define XILINX_MAX_NUM_RESOURCES        3
  99
 100 /**
 101  * struct xilinx_pcie_port - PCIe port information
 102  * @reg_base: IO Mapped Register Base
 103  * @irq: Interrupt number
 104  * @msi_pages: MSI pages
 105  * @root_busno: Root Bus number
 106  * @dev: Device pointer
 107  * @irq_domain: IRQ domain pointer
 108  * @bus_range: Bus range
 109  * @resources: Bus Resources
 110  */
 111 struct xilinx_pcie_port {
 112         void __iomem *reg_base;
 113         u32 irq;
 114         unsigned long msi_pages;
 115         u8 root_busno;
 116         struct device *dev;
 117         struct irq_domain *irq_domain;
 118         struct resource bus_range;
 119         struct list_head resources;
 120 };
 121
 122 static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
 123
 124 static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
 125 {
 126         return sys->private_data;
 127 }
 128
 129 static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
 130 {
 131         return readl(port->reg_base + reg);
 132 }
 133
 134 static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
 135 {
 136         writel(val, port->reg_base + reg);
 137 }
 138
 139 static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
 140 {
 141         return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
 142                 XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
 143 }
 144
 145 /**
 146  * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
 147  * @port: PCIe port information
 148  */
 149 static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
 150 {
 151         unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
 152
 153         if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
 154                 dev_dbg(port->dev, "Requester ID %lu\n",
 155                         val & XILINX_PCIE_RPEFR_REQ_ID);
 156                 pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
 157                            XILINX_PCIE_REG_RPEFR);
 158         }
 159 }
 160
 161 /**
 162  * xilinx_pcie_valid_device - Check if a valid device is present on bus
 163  * @bus: PCI Bus structure
 164  * @devfn: device/function
 165  *
 166  * Return: 'true' on success and 'false' if invalid device is found
 167  */
 168 static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 169 {
 170         struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
 171
 172         /* Check if link is up when trying to access downstream ports */
 173         if (bus->number != port->root_busno)
 174                 if (!xilinx_pcie_link_is_up(port))
 175                         return false;
 176
 177         /* Only one device down on each root port */
 178         if (bus->number == port->root_busno && devfn > 0)
 179                 return false;
 180
 181         /*
 182          * Do not read more than one device on the bus directly attached
 183          * to RC.
 184          */
 185         if (bus->primary == port->root_busno && devfn > 0)
 186                 return false;
 187
 188         return true;
 189 }
 190
 191 /**
 192  * xilinx_pcie_map_bus - Get configuration base
 193  * @bus: PCI Bus structure
 194  * @devfn: Device/function
 195  * @where: Offset from base
 196  *
 197  * Return: Base address of the configuration space needed to be
 198  *         accessed.
 199  */
 200 static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
 201                                          unsigned int devfn, int where)
 202 {
 203         struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
 204         int relbus;
 205
 206         if (!xilinx_pcie_valid_device(bus, devfn))
 207                 return NULL;
 208
 209         relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
 210                  (devfn << ECAM_DEV_NUM_SHIFT);
 211
 212         return port->reg_base + relbus + where;
 213 }
 214
 215 /* PCIe operations */
 216 static struct pci_ops xilinx_pcie_ops = {
 217         .map_bus = xilinx_pcie_map_bus,
 218         .read   = pci_generic_config_read,
 219         .write  = pci_generic_config_write,
 220 };
 221
 222 /* MSI functions */
 223
 224 /**
 225  * xilinx_pcie_destroy_msi - Free MSI number
 226  * @irq: IRQ to be freed
 227  */
 228 static void xilinx_pcie_destroy_msi(unsigned int irq)
 229 {
 230         struct irq_desc *desc;
 231         struct msi_desc *msi;
 232         struct xilinx_pcie_port *port;
 233
 234         desc = irq_to_desc(irq);
 235         msi = irq_desc_get_msi_desc(desc);
 236         port = sys_to_pcie(msi->dev->bus->sysdata);
 237
 238         if (!test_bit(irq, msi_irq_in_use))
 239                 dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
 240         else
 241                 clear_bit(irq, msi_irq_in_use);
 242 }
 243
 244 /**
 245  * xilinx_pcie_assign_msi - Allocate MSI number
 246  * @port: PCIe port structure
 247  *
 248  * Return: A valid IRQ on success and error value on failure.
 249  */
 250 static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
 251 {
 252         int pos;
 253
 254         pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
 255         if (pos < XILINX_NUM_MSI_IRQS)
 256                 set_bit(pos, msi_irq_in_use);
 257         else
 258                 return -ENOSPC;
 259
 260         return pos;
 261 }
 262
 263 /**
 264  * xilinx_msi_teardown_irq - Destroy the MSI
 265  * @chip: MSI Chip descriptor
 266  * @irq: MSI IRQ to destroy
 267  */
 268 static void xilinx_msi_teardown_irq(struct msi_controller *chip,
 269                                     unsigned int irq)
 270 {
 271         xilinx_pcie_destroy_msi(irq);
 272 }
 273
 274 /**
 275  * xilinx_pcie_msi_setup_irq - Setup MSI request
 276  * @chip: MSI chip pointer
 277  * @pdev: PCIe device pointer
 278  * @desc: MSI descriptor pointer
 279  *
 280  * Return: '0' on success and error value on failure
 281  */
 282 static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
 283                                      struct pci_dev *pdev,
 284                                      struct msi_desc *desc)
 285 {
 286         struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
 287         unsigned int irq;
 288         int hwirq;
 289         struct msi_msg msg;
 290         phys_addr_t msg_addr;
 291
 292         hwirq = xilinx_pcie_assign_msi(port);
 293         if (hwirq < 0)
 294                 return hwirq;
 295
 296         irq = irq_create_mapping(port->irq_domain, hwirq);
 297         if (!irq)
 298                 return -EINVAL;
 299
 300         irq_set_msi_desc(irq, desc);
 301
 302         msg_addr = virt_to_phys((void *)port->msi_pages);
 303
 304         msg.address_hi = 0;
 305         msg.address_lo = msg_addr;
 306         msg.data = irq;
 307
 308         pci_write_msi_msg(irq, &msg);
 309
 310         return 0;
 311 }
 312
 313 /* MSI Chip Descriptor */
 314 static struct msi_controller xilinx_pcie_msi_chip = {
 315         .setup_irq = xilinx_pcie_msi_setup_irq,
 316         .teardown_irq = xilinx_msi_teardown_irq,
 317 };
 318
 319 /* HW Interrupt Chip Descriptor */
 320 static struct irq_chip xilinx_msi_irq_chip = {
 321         .name = "Xilinx PCIe MSI",
 322         .irq_enable = pci_msi_unmask_irq,
 323         .irq_disable = pci_msi_mask_irq,
 324         .irq_mask = pci_msi_mask_irq,
 325         .irq_unmask = pci_msi_unmask_irq,
 326 };
 327
 328 /**
 329  * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
 330  * @domain: IRQ domain
 331  * @irq: Virtual IRQ number
 332  * @hwirq: HW interrupt number
 333  *
 334  * Return: Always returns 0.
 335  */
 336 static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
 337                                irq_hw_number_t hwirq)
 338 {
 339         irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
 340         irq_set_chip_data(irq, domain->host_data);
 341
 342         return 0;
 343 }
 344
 345 /* IRQ Domain operations */
 346 static const struct irq_domain_ops msi_domain_ops = {
 347         .map = xilinx_pcie_msi_map,
 348 };
 349
 350 /**
 351  * xilinx_pcie_enable_msi - Enable MSI support
 352  * @port: PCIe port information
 353  */
 354 static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
 355 {
 356         phys_addr_t msg_addr;
 357
 358         port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
 359         msg_addr = virt_to_phys((void *)port->msi_pages);
 360         pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
 361         pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
 362 }
 363
 364 /* INTx Functions */
 365
 366 /**
 367  * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
 368  * @domain: IRQ domain
 369  * @irq: Virtual IRQ number
 370  * @hwirq: HW interrupt number
 371  *
 372  * Return: Always returns 0.
 373  */
 374 static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 375                                 irq_hw_number_t hwirq)
 376 {
 377         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 378         irq_set_chip_data(irq, domain->host_data);
 379
 380         return 0;
 381 }
 382
 383 /* INTx IRQ Domain operations */
 384 static const struct irq_domain_ops intx_domain_ops = {
 385         .map = xilinx_pcie_intx_map,
 386 };
 387
 388 /* PCIe HW Functions */
 389
 390 /**
 391  * xilinx_pcie_intr_handler - Interrupt Service Handler
 392  * @irq: IRQ number
 393  * @data: PCIe port information
 394  *
 395  * Return: IRQ_HANDLED on success and IRQ_NONE on failure
 396  */
 397 static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 398 {
 399         struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
 400         u32 val, mask, status, msi_data;
 401
 402         /* Read interrupt decode and mask registers */
 403         val = pcie_read(port, XILINX_PCIE_REG_IDR);
 404         mask = pcie_read(port, XILINX_PCIE_REG_IMR);
 405
 406         status = val & mask;
 407         if (!status)
 408                 return IRQ_NONE;
 409
 410         if (status & XILINX_PCIE_INTR_LINK_DOWN)
 411                 dev_warn(port->dev, "Link Down\n");
 412
 413         if (status & XILINX_PCIE_INTR_ECRC_ERR)
 414                 dev_warn(port->dev, "ECRC failed\n");
 415
 416         if (status & XILINX_PCIE_INTR_STR_ERR)
 417                 dev_warn(port->dev, "Streaming error\n");
 418
 419         if (status & XILINX_PCIE_INTR_HOT_RESET)
 420                 dev_info(port->dev, "Hot reset\n");
 421
 422         if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
 423                 dev_warn(port->dev, "ECAM access timeout\n");
 424
 425         if (status & XILINX_PCIE_INTR_CORRECTABLE) {
 426                 dev_warn(port->dev, "Correctable error message\n");
 427                 xilinx_pcie_clear_err_interrupts(port);
 428         }
 429
 430         if (status & XILINX_PCIE_INTR_NONFATAL) {
 431                 dev_warn(port->dev, "Non fatal error message\n");
 432                 xilinx_pcie_clear_err_interrupts(port);
 433         }
 434
 435         if (status & XILINX_PCIE_INTR_FATAL) {
 436                 dev_warn(port->dev, "Fatal error message\n");
 437                 xilinx_pcie_clear_err_interrupts(port);
 438         }
 439
 440         if (status & XILINX_PCIE_INTR_INTX) {
 441                 /* INTx interrupt received */
 442                 val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
 443
 444                 /* Check whether interrupt valid */
 445                 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
 446                         dev_warn(port->dev, "RP Intr FIFO1 read error\n");
 447                         return IRQ_HANDLED;
 448                 }
 449
 450                 if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
 451                         /* Clear interrupt FIFO register 1 */
 452                         pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
 453                                    XILINX_PCIE_REG_RPIFR1);
 454
 455                         /* Handle INTx Interrupt */
 456                         val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
 457                                 XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
 458                         generic_handle_irq(irq_find_mapping(port->irq_domain,
 459                                                             val));
 460                 }
 461         }
 462
 463         if (status & XILINX_PCIE_INTR_MSI) {
 464                 /* MSI Interrupt */
 465                 val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
 466
 467                 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
 468                         dev_warn(port->dev, "RP Intr FIFO1 read error\n");
 469                         return IRQ_HANDLED;
 470                 }
 471
 472                 if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
 473                         msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
 474                                    XILINX_PCIE_RPIFR2_MSG_DATA;
 475
 476                         /* Clear interrupt FIFO register 1 */
 477                         pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
 478                                    XILINX_PCIE_REG_RPIFR1);
 479
 480                         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 481                                 /* Handle MSI Interrupt */
 482                                 generic_handle_irq(msi_data);
 483                         }
 484                 }
 485         }
 486
 487         if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
 488                 dev_warn(port->dev, "Slave unsupported request\n");
 489
 490         if (status & XILINX_PCIE_INTR_SLV_UNEXP)
 491                 dev_warn(port->dev, "Slave unexpected completion\n");
 492
 493         if (status & XILINX_PCIE_INTR_SLV_COMPL)
 494                 dev_warn(port->dev, "Slave completion timeout\n");
 495
 496         if (status & XILINX_PCIE_INTR_SLV_ERRP)
 497                 dev_warn(port->dev, "Slave Error Poison\n");
 498
 499         if (status & XILINX_PCIE_INTR_SLV_CMPABT)
 500                 dev_warn(port->dev, "Slave Completer Abort\n");
 501
 502         if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
 503                 dev_warn(port->dev, "Slave Illegal Burst\n");
 504
 505         if (status & XILINX_PCIE_INTR_MST_DECERR)
 506                 dev_warn(port->dev, "Master decode error\n");
 507
 508         if (status & XILINX_PCIE_INTR_MST_SLVERR)
 509                 dev_warn(port->dev, "Master slave error\n");
 510
 511         if (status & XILINX_PCIE_INTR_MST_ERRP)
 512                 dev_warn(port->dev, "Master error poison\n");
 513
 514         /* Clear the Interrupt Decode register */
 515         pcie_write(port, status, XILINX_PCIE_REG_IDR);
 516
 517         return IRQ_HANDLED;
 518 }
 519
 520 /**
 521  * xilinx_pcie_free_irq_domain - Free IRQ domain
 522  * @port: PCIe port information
 523  */
 524 static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
 525 {
 526         int i;
 527         u32 irq, num_irqs;
 528
 529         /* Free IRQ Domain */
 530         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 531
 532                 free_pages(port->msi_pages, 0);
 533
 534                 num_irqs = XILINX_NUM_MSI_IRQS;
 535         } else {
 536                 /* INTx */
 537                 num_irqs = 4;
 538         }
 539
 540         for (i = 0; i < num_irqs; i++) {
 541                 irq = irq_find_mapping(port->irq_domain, i);
 542                 if (irq > 0)
 543                         irq_dispose_mapping(irq);
 544         }
 545
 546         irq_domain_remove(port->irq_domain);
 547 }
 548
 549 /**
 550  * xilinx_pcie_init_irq_domain - Initialize IRQ domain
 551  * @port: PCIe port information
 552  *
 553  * Return: '0' on success and error value on failure
 554  */
 555 static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
 556 {
 557         struct device *dev = port->dev;
 558         struct device_node *node = dev->of_node;
 559         struct device_node *pcie_intc_node;
 560
 561         /* Setup INTx */
 562         pcie_intc_node = of_get_next_child(node, NULL);
 563         if (!pcie_intc_node) {
 564                 dev_err(dev, "No PCIe Intc node found\n");
 565                 return PTR_ERR(pcie_intc_node);
 566         }
 567
 568         port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
 569                                                  &intx_domain_ops,
 570                                                  port);
 571         if (!port->irq_domain) {
 572                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 573                 return PTR_ERR(port->irq_domain);
 574         }
 575
 576         /* Setup MSI */
 577         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 578                 port->irq_domain = irq_domain_add_linear(node,
 579                                                          XILINX_NUM_MSI_IRQS,
 580                                                          &msi_domain_ops,
 581                                                          &xilinx_pcie_msi_chip);
 582                 if (!port->irq_domain) {
 583                         dev_err(dev, "Failed to get a MSI IRQ domain\n");
 584                         return PTR_ERR(port->irq_domain);
 585                 }
 586
 587                 xilinx_pcie_enable_msi(port);
 588         }
 589
 590         return 0;
 591 }
 592
 593 /**
 594  * xilinx_pcie_init_port - Initialize hardware
 595  * @port: PCIe port information
 596  */
 597 static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
 598 {
 599         if (xilinx_pcie_link_is_up(port))
 600                 dev_info(port->dev, "PCIe Link is UP\n");
 601         else
 602                 dev_info(port->dev, "PCIe Link is DOWN\n");
 603
 604         /* Disable all interrupts */
 605         pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
 606                    XILINX_PCIE_REG_IMR);
 607
 608         /* Clear pending interrupts */
 609         pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
 610                          XILINX_PCIE_IMR_ALL_MASK,
 611                    XILINX_PCIE_REG_IDR);
 612
 613         /* Enable all interrupts */
 614         pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
 615
 616         /* Enable the Bridge enable bit */
 617         pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
 618                          XILINX_PCIE_REG_RPSC_BEN,
 619                    XILINX_PCIE_REG_RPSC);
 620 }
 621
 622 /**
 623  * xilinx_pcie_setup - Setup memory resources
 624  * @nr: Bus number
 625  * @sys: Per controller structure
 626  *
 627  * Return: '1' on success and error value on failure
 628  */
 629 static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
 630 {
 631         struct xilinx_pcie_port *port = sys_to_pcie(sys);
 632
 633         list_splice_init(&port->resources, &sys->resources);
 634
 635         return 1;
 636 }
 637
 638 /**
 639  * xilinx_pcie_scan_bus - Scan PCIe bus for devices
 640  * @nr: Bus number
 641  * @sys: Per controller structure
 642  *
 643  * Return: Valid Bus pointer on success and NULL on failure
 644  */
 645 static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 646 {
 647         struct xilinx_pcie_port *port = sys_to_pcie(sys);
 648         struct pci_bus *bus;
 649
 650         port->root_busno = sys->busnr;
 651         bus = pci_scan_root_bus(port->dev, sys->busnr, &xilinx_pcie_ops,
 652                                 sys, &sys->resources);
 653
 654         return bus;
 655 }
 656
 657 /**
 658  * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
 659  * @port: PCIe port information
 660  *
 661  * Return: '0' on success and error value on failure
 662  */
 663 static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
 664 {
 665         struct device *dev = port->dev;
 666         struct device_node *node = dev->of_node;
 667         struct resource *mem;
 668         resource_size_t offset;
 669         struct of_pci_range_parser parser;
 670         struct of_pci_range range;
 671         struct resource_entry *win;
 672         int err = 0, mem_resno = 0;
 673
 674         /* Get the ranges */
 675         if (of_pci_range_parser_init(&parser, node)) {
 676                 dev_err(dev, "missing \"ranges\" property\n");
 677                 return -EINVAL;
 678         }
 679
 680         /* Parse the ranges and add the resources found to the list */
 681         for_each_of_pci_range(&parser, &range) {
 682
 683                 if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
 684                         dev_err(dev, "Maximum memory resources exceeded\n");
 685                         return -EINVAL;
 686                 }
 687
 688                 mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
 689                 if (!mem) {
 690                         err = -ENOMEM;
 691                         goto free_resources;
 692                 }
 693
 694                 of_pci_range_to_resource(&range, node, mem);
 695
 696                 switch (mem->flags & IORESOURCE_TYPE_BITS) {
 697                 case IORESOURCE_MEM:
 698                         offset = range.cpu_addr - range.pci_addr;
 699                         mem_resno++;
 700                         break;
 701                 default:
 702                         err = -EINVAL;
 703                         break;
 704                 }
 705
 706                 if (err < 0) {
 707                         dev_warn(dev, "Invalid resource found %pR\n", mem);
 708                         continue;
 709                 }
 710
 711                 err = request_resource(&iomem_resource, mem);
 712                 if (err)
 713                         goto free_resources;
 714
 715                 pci_add_resource_offset(&port->resources, mem, offset);
 716         }
 717
 718         /* Get the bus range */
 719         if (of_pci_parse_bus_range(node, &port->bus_range)) {
 720                 u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
 721                 u8 last;
 722
 723                 last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
 724                         XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
 725
 726                 port->bus_range = (struct resource) {
 727                         .name   = node->name,
 728                         .start  = 0,
 729                         .end    = last,
 730                         .flags  = IORESOURCE_BUS,
 731                 };
 732         }
 733
 734         /* Register bus resource */
 735         pci_add_resource(&port->resources, &port->bus_range);
 736
 737         return 0;
 738
 739 free_resources:
 740         release_child_resources(&iomem_resource);
 741         resource_list_for_each_entry(win, &port->resources)
 742                 devm_kfree(dev, win->res);
 743         pci_free_resource_list(&port->resources);
 744
 745         return err;
 746 }
 747
 748 /**
 749  * xilinx_pcie_parse_dt - Parse Device tree
 750  * @port: PCIe port information
 751  *
 752  * Return: '0' on success and error value on failure
 753  */
 754 static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
 755 {
 756         struct device *dev = port->dev;
 757         struct device_node *node = dev->of_node;
 758         struct resource regs;
 759         const char *type;
 760         int err;
 761
 762         type = of_get_property(node, "device_type", NULL);
 763         if (!type || strcmp(type, "pci")) {
 764                 dev_err(dev, "invalid \"device_type\" %s\n", type);
 765                 return -EINVAL;
 766         }
 767
 768         err = of_address_to_resource(node, 0, &regs);
 769         if (err) {
 770                 dev_err(dev, "missing \"reg\" property\n");
 771                 return err;
 772         }
 773
 774         port->reg_base = devm_ioremap_resource(dev, &regs);
 775         if (IS_ERR(port->reg_base))
 776                 return PTR_ERR(port->reg_base);
 777
 778         port->irq = irq_of_parse_and_map(node, 0);
 779         err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
 780                                IRQF_SHARED, "xilinx-pcie", port);
 781         if (err) {
 782                 dev_err(dev, "unable to request irq %d\n", port->irq);
 783                 return err;
 784         }
 785
 786         return 0;
 787 }
 788
 789 /**
 790  * xilinx_pcie_probe - Probe function
 791  * @pdev: Platform device pointer
 792  *
 793  * Return: '0' on success and error value on failure
 794  */
 795 static int xilinx_pcie_probe(struct platform_device *pdev)
 796 {
 797         struct xilinx_pcie_port *port;
 798         struct hw_pci hw;
 799         struct device *dev = &pdev->dev;
 800         int err;
 801
 802         if (!dev->of_node)
 803                 return -ENODEV;
 804
 805         port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
 806         if (!port)
 807                 return -ENOMEM;
 808
 809         port->dev = dev;
 810
 811         err = xilinx_pcie_parse_dt(port);
 812         if (err) {
 813                 dev_err(dev, "Parsing DT failed\n");
 814                 return err;
 815         }
 816
 817         xilinx_pcie_init_port(port);
 818
 819         err = xilinx_pcie_init_irq_domain(port);
 820         if (err) {
 821                 dev_err(dev, "Failed creating IRQ Domain\n");
 822                 return err;
 823         }
 824
 825         /*
 826          * Parse PCI ranges, configuration bus range and
 827          * request their resources
 828          */
 829         INIT_LIST_HEAD(&port->resources);
 830         err = xilinx_pcie_parse_and_add_res(port);
 831         if (err) {
 832                 dev_err(dev, "Failed adding resources\n");
 833                 return err;
 834         }
 835
 836         platform_set_drvdata(pdev, port);
 837
 838         /* Register the device */
 839         memset(&hw, 0, sizeof(hw));
 840         hw = (struct hw_pci) {
 841                 .nr_controllers = 1,
 842                 .private_data   = (void **)&port,
 843                 .setup          = xilinx_pcie_setup,
 844                 .map_irq        = of_irq_parse_and_map_pci,
 845                 .scan           = xilinx_pcie_scan_bus,
 846                 .ops            = &xilinx_pcie_ops,
 847         };
 848
 849 #ifdef CONFIG_PCI_MSI
 850         xilinx_pcie_msi_chip.dev = port->dev;
 851         hw.msi_ctrl = &xilinx_pcie_msi_chip;
 852 #endif
 853         pci_common_init_dev(dev, &hw);
 854
 855         return 0;
 856 }
 857
 858 /**
 859  * xilinx_pcie_remove - Remove function
 860  * @pdev: Platform device pointer
 861  *
 862  * Return: '0' always
 863  */
 864 static int xilinx_pcie_remove(struct platform_device *pdev)
 865 {
 866         struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
 867
 868         xilinx_pcie_free_irq_domain(port);
 869
 870         return 0;
 871 }
 872
 873 static struct of_device_id xilinx_pcie_of_match[] = {
 874         { .compatible = "xlnx,axi-pcie-host-1.00.a", },
 875         {}
 876 };
 877
 878 static struct platform_driver xilinx_pcie_driver = {
 879         .driver = {
 880                 .name = "xilinx-pcie",
 881                 .of_match_table = xilinx_pcie_of_match,
 882                 .suppress_bind_attrs = true,
 883         },
 884         .probe = xilinx_pcie_probe,
 885         .remove = xilinx_pcie_remove,
 886 };
 887 module_platform_driver(xilinx_pcie_driver);
 888
 889 MODULE_AUTHOR("Xilinx Inc");
 890 MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
 891 MODULE_LICENSE("GPL v2");