2 * IBM Hot Plug Controller Driver
4 * Written By: Jyoti Shah, IBM Corporation
6 * Copyright (C) 2001-2003 IBM Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Send feedback to <gregkh@us.ibm.com>
30 #include <linux/wait.h>
31 #include <linux/time.h>
32 #include <linux/delay.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/mutex.h>
40 static int to_debug
= 0;
41 #define debug_polling(fmt, arg...) do { if (to_debug) debug (fmt, arg); } while (0)
43 //----------------------------------------------------------------------------
45 //----------------------------------------------------------------------------
46 #define CMD_COMPLETE_TOUT_SEC 60 // give HPC 60 sec to finish cmd
47 #define HPC_CTLR_WORKING_TOUT 60 // give HPC 60 sec to finish cmd
48 #define HPC_GETACCESS_TIMEOUT 60 // seconds
49 #define POLL_INTERVAL_SEC 2 // poll HPC every 2 seconds
50 #define POLL_LATCH_CNT 5 // poll latch 5 times, then poll slots
52 //----------------------------------------------------------------------------
53 // Winnipeg Architected Register Offsets
54 //----------------------------------------------------------------------------
55 #define WPG_I2CMBUFL_OFFSET 0x08 // I2C Message Buffer Low
56 #define WPG_I2CMOSUP_OFFSET 0x10 // I2C Master Operation Setup Reg
57 #define WPG_I2CMCNTL_OFFSET 0x20 // I2C Master Control Register
58 #define WPG_I2CPARM_OFFSET 0x40 // I2C Parameter Register
59 #define WPG_I2CSTAT_OFFSET 0x70 // I2C Status Register
61 //----------------------------------------------------------------------------
62 // Winnipeg Store Type commands (Add this commands to the register offset)
63 //----------------------------------------------------------------------------
64 #define WPG_I2C_AND 0x1000 // I2C AND operation
65 #define WPG_I2C_OR 0x2000 // I2C OR operation
67 //----------------------------------------------------------------------------
68 // Command set for I2C Master Operation Setup Register
69 //----------------------------------------------------------------------------
70 #define WPG_READATADDR_MASK 0x00010000 // read,bytes,I2C shifted,index
71 #define WPG_WRITEATADDR_MASK 0x40010000 // write,bytes,I2C shifted,index
72 #define WPG_READDIRECT_MASK 0x10010000
73 #define WPG_WRITEDIRECT_MASK 0x60010000
76 //----------------------------------------------------------------------------
77 // bit masks for I2C Master Control Register
78 //----------------------------------------------------------------------------
79 #define WPG_I2CMCNTL_STARTOP_MASK 0x00000002 // Start the Operation
81 //----------------------------------------------------------------------------
83 //----------------------------------------------------------------------------
84 #define WPG_I2C_IOREMAP_SIZE 0x2044 // size of linear address interval
86 //----------------------------------------------------------------------------
88 //----------------------------------------------------------------------------
89 #define WPG_1ST_SLOT_INDEX 0x01 // index - 1st slot for ctlr
90 #define WPG_CTLR_INDEX 0x0F // index - ctlr
91 #define WPG_1ST_EXTSLOT_INDEX 0x10 // index - 1st ext slot for ctlr
92 #define WPG_1ST_BUS_INDEX 0x1F // index - 1st bus for ctlr
94 //----------------------------------------------------------------------------
96 //----------------------------------------------------------------------------
97 // if bits 20,22,25,26,27,29,30 are OFF return 1
98 #define HPC_I2CSTATUS_CHECK(s) ((u8)((s & 0x00000A76) ? 0 : 1))
100 //----------------------------------------------------------------------------
102 //----------------------------------------------------------------------------
103 static int ibmphp_shutdown
;
105 static struct mutex sem_hpcaccess
; // lock access to HPC
106 static struct semaphore semOperations
; // lock all operations and
107 // access to data structures
108 static struct semaphore sem_exit
; // make sure polling thread goes away
109 //----------------------------------------------------------------------------
110 // local function prototypes
111 //----------------------------------------------------------------------------
112 static u8
i2c_ctrl_read (struct controller
*, void __iomem
*, u8
);
113 static u8
i2c_ctrl_write (struct controller
*, void __iomem
*, u8
, u8
);
114 static u8
hpc_writecmdtoindex (u8
, u8
);
115 static u8
hpc_readcmdtoindex (u8
, u8
);
116 static void get_hpc_access (void);
117 static void free_hpc_access (void);
118 static void poll_hpc (void);
119 static int process_changeinstatus (struct slot
*, struct slot
*);
120 static int process_changeinlatch (u8
, u8
, struct controller
*);
121 static int hpc_poll_thread (void *);
122 static int hpc_wait_ctlr_notworking (int, struct controller
*, void __iomem
*, u8
*);
123 //----------------------------------------------------------------------------
126 /*----------------------------------------------------------------------
127 * Name: ibmphp_hpc_initvars
129 * Action: initialize semaphores and variables
130 *---------------------------------------------------------------------*/
131 void __init
ibmphp_hpc_initvars (void)
133 debug ("%s - Entry\n", __FUNCTION__
);
135 mutex_init(&sem_hpcaccess
);
136 init_MUTEX (&semOperations
);
137 init_MUTEX_LOCKED (&sem_exit
);
142 debug ("%s - Exit\n", __FUNCTION__
);
145 /*----------------------------------------------------------------------
146 * Name: i2c_ctrl_read
148 * Action: read from HPC over I2C
150 *---------------------------------------------------------------------*/
151 static u8
i2c_ctrl_read (struct controller
*ctlr_ptr
, void __iomem
*WPGBbar
, u8 index
)
155 void __iomem
*wpg_addr
; // base addr + offset
156 unsigned long wpg_data
; // data to/from WPG LOHI format
157 unsigned long ultemp
;
158 unsigned long data
; // actual data HILO format
160 debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__
, WPGBbar
, index
);
162 //--------------------------------------------------------------------
164 // read at address, byte length, I2C address (shifted), index
165 // or read direct, byte length, index
166 if (ctlr_ptr
->ctlr_type
== 0x02) {
167 data
= WPG_READATADDR_MASK
;
168 // fill in I2C address
169 ultemp
= (unsigned long)ctlr_ptr
->u
.wpeg_ctlr
.i2c_addr
;
170 ultemp
= ultemp
>> 1;
171 data
|= (ultemp
<< 8);
174 data
|= (unsigned long)index
;
175 } else if (ctlr_ptr
->ctlr_type
== 0x04) {
176 data
= WPG_READDIRECT_MASK
;
179 ultemp
= (unsigned long)index
;
180 ultemp
= ultemp
<< 8;
183 err ("this controller type is not supported \n");
187 wpg_data
= swab32 (data
); // swap data before writing
188 wpg_addr
= WPGBbar
+ WPG_I2CMOSUP_OFFSET
;
189 writel (wpg_data
, wpg_addr
);
191 //--------------------------------------------------------------------
192 // READ - step 2 : clear the message buffer
194 wpg_data
= swab32 (data
);
195 wpg_addr
= WPGBbar
+ WPG_I2CMBUFL_OFFSET
;
196 writel (wpg_data
, wpg_addr
);
198 //--------------------------------------------------------------------
199 // READ - step 3 : issue start operation, I2C master control bit 30:ON
200 // 2020 : [20] OR operation at [20] offset 0x20
201 data
= WPG_I2CMCNTL_STARTOP_MASK
;
202 wpg_data
= swab32 (data
);
203 wpg_addr
= WPGBbar
+ WPG_I2CMCNTL_OFFSET
+ WPG_I2C_OR
;
204 writel (wpg_data
, wpg_addr
);
206 //--------------------------------------------------------------------
207 // READ - step 4 : wait until start operation bit clears
208 i
= CMD_COMPLETE_TOUT_SEC
;
211 wpg_addr
= WPGBbar
+ WPG_I2CMCNTL_OFFSET
;
212 wpg_data
= readl (wpg_addr
);
213 data
= swab32 (wpg_data
);
214 if (!(data
& WPG_I2CMCNTL_STARTOP_MASK
))
219 debug ("%s - Error : WPG timeout\n", __FUNCTION__
);
222 //--------------------------------------------------------------------
223 // READ - step 5 : read I2C status register
224 i
= CMD_COMPLETE_TOUT_SEC
;
227 wpg_addr
= WPGBbar
+ WPG_I2CSTAT_OFFSET
;
228 wpg_data
= readl (wpg_addr
);
229 data
= swab32 (wpg_data
);
230 if (HPC_I2CSTATUS_CHECK (data
))
235 debug ("ctrl_read - Exit Error:I2C timeout\n");
239 //--------------------------------------------------------------------
240 // READ - step 6 : get DATA
241 wpg_addr
= WPGBbar
+ WPG_I2CMBUFL_OFFSET
;
242 wpg_data
= readl (wpg_addr
);
243 data
= swab32 (wpg_data
);
247 debug_polling ("%s - Exit index[%x] status[%x]\n", __FUNCTION__
, index
, status
);
252 /*----------------------------------------------------------------------
253 * Name: i2c_ctrl_write
255 * Action: write to HPC over I2C
257 * Return 0 or error codes
258 *---------------------------------------------------------------------*/
259 static u8
i2c_ctrl_write (struct controller
*ctlr_ptr
, void __iomem
*WPGBbar
, u8 index
, u8 cmd
)
262 void __iomem
*wpg_addr
; // base addr + offset
263 unsigned long wpg_data
; // data to/from WPG LOHI format
264 unsigned long ultemp
;
265 unsigned long data
; // actual data HILO format
268 debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__
, WPGBbar
, index
, cmd
);
271 //--------------------------------------------------------------------
273 // write at address, byte length, I2C address (shifted), index
274 // or write direct, byte length, index
277 if (ctlr_ptr
->ctlr_type
== 0x02) {
278 data
= WPG_WRITEATADDR_MASK
;
279 // fill in I2C address
280 ultemp
= (unsigned long)ctlr_ptr
->u
.wpeg_ctlr
.i2c_addr
;
281 ultemp
= ultemp
>> 1;
282 data
|= (ultemp
<< 8);
285 data
|= (unsigned long)index
;
286 } else if (ctlr_ptr
->ctlr_type
== 0x04) {
287 data
= WPG_WRITEDIRECT_MASK
;
290 ultemp
= (unsigned long)index
;
291 ultemp
= ultemp
<< 8;
294 err ("this controller type is not supported \n");
298 wpg_data
= swab32 (data
); // swap data before writing
299 wpg_addr
= WPGBbar
+ WPG_I2CMOSUP_OFFSET
;
300 writel (wpg_data
, wpg_addr
);
302 //--------------------------------------------------------------------
303 // WRITE - step 2 : clear the message buffer
304 data
= 0x00000000 | (unsigned long)cmd
;
305 wpg_data
= swab32 (data
);
306 wpg_addr
= WPGBbar
+ WPG_I2CMBUFL_OFFSET
;
307 writel (wpg_data
, wpg_addr
);
309 //--------------------------------------------------------------------
310 // WRITE - step 3 : issue start operation,I2C master control bit 30:ON
311 // 2020 : [20] OR operation at [20] offset 0x20
312 data
= WPG_I2CMCNTL_STARTOP_MASK
;
313 wpg_data
= swab32 (data
);
314 wpg_addr
= WPGBbar
+ WPG_I2CMCNTL_OFFSET
+ WPG_I2C_OR
;
315 writel (wpg_data
, wpg_addr
);
317 //--------------------------------------------------------------------
318 // WRITE - step 4 : wait until start operation bit clears
319 i
= CMD_COMPLETE_TOUT_SEC
;
322 wpg_addr
= WPGBbar
+ WPG_I2CMCNTL_OFFSET
;
323 wpg_data
= readl (wpg_addr
);
324 data
= swab32 (wpg_data
);
325 if (!(data
& WPG_I2CMCNTL_STARTOP_MASK
))
330 debug ("%s - Exit Error:WPG timeout\n", __FUNCTION__
);
334 //--------------------------------------------------------------------
335 // WRITE - step 5 : read I2C status register
336 i
= CMD_COMPLETE_TOUT_SEC
;
339 wpg_addr
= WPGBbar
+ WPG_I2CSTAT_OFFSET
;
340 wpg_data
= readl (wpg_addr
);
341 data
= swab32 (wpg_data
);
342 if (HPC_I2CSTATUS_CHECK (data
))
347 debug ("ctrl_read - Error : I2C timeout\n");
351 debug_polling ("%s Exit rc[%x]\n", __FUNCTION__
, rc
);
355 //------------------------------------------------------------
356 // Read from ISA type HPC
357 //------------------------------------------------------------
358 static u8
isa_ctrl_read (struct controller
*ctlr_ptr
, u8 offset
)
364 start_address
= ctlr_ptr
->u
.isa_ctlr
.io_start
;
365 end_address
= ctlr_ptr
->u
.isa_ctlr
.io_end
;
366 data
= inb (start_address
+ offset
);
370 //--------------------------------------------------------------
371 // Write to ISA type HPC
372 //--------------------------------------------------------------
373 static void isa_ctrl_write (struct controller
*ctlr_ptr
, u8 offset
, u8 data
)
378 start_address
= ctlr_ptr
->u
.isa_ctlr
.io_start
;
379 port_address
= start_address
+ (u16
) offset
;
380 outb (data
, port_address
);
383 static u8
pci_ctrl_read (struct controller
*ctrl
, u8 offset
)
386 debug ("inside pci_ctrl_read\n");
388 pci_read_config_byte (ctrl
->ctrl_dev
, HPC_PCI_OFFSET
+ offset
, &data
);
392 static u8
pci_ctrl_write (struct controller
*ctrl
, u8 offset
, u8 data
)
395 debug ("inside pci_ctrl_write\n");
396 if (ctrl
->ctrl_dev
) {
397 pci_write_config_byte (ctrl
->ctrl_dev
, HPC_PCI_OFFSET
+ offset
, data
);
403 static u8
ctrl_read (struct controller
*ctlr
, void __iomem
*base
, u8 offset
)
406 switch (ctlr
->ctlr_type
) {
408 rc
= isa_ctrl_read (ctlr
, offset
);
411 rc
= pci_ctrl_read (ctlr
, offset
);
415 rc
= i2c_ctrl_read (ctlr
, base
, offset
);
423 static u8
ctrl_write (struct controller
*ctlr
, void __iomem
*base
, u8 offset
, u8 data
)
426 switch (ctlr
->ctlr_type
) {
428 isa_ctrl_write(ctlr
, offset
, data
);
431 rc
= pci_ctrl_write (ctlr
, offset
, data
);
435 rc
= i2c_ctrl_write(ctlr
, base
, offset
, data
);
442 /*----------------------------------------------------------------------
443 * Name: hpc_writecmdtoindex()
445 * Action: convert a write command to proper index within a controller
447 * Return index, HPC_ERROR
448 *---------------------------------------------------------------------*/
449 static u8
hpc_writecmdtoindex (u8 cmd
, u8 index
)
454 case HPC_CTLR_ENABLEIRQ
: // 0x00.N.15
455 case HPC_CTLR_CLEARIRQ
: // 0x06.N.15
456 case HPC_CTLR_RESET
: // 0x07.N.15
457 case HPC_CTLR_IRQSTEER
: // 0x08.N.15
458 case HPC_CTLR_DISABLEIRQ
: // 0x01.N.15
459 case HPC_ALLSLOT_ON
: // 0x11.N.15
460 case HPC_ALLSLOT_OFF
: // 0x12.N.15
464 case HPC_SLOT_OFF
: // 0x02.Y.0-14
465 case HPC_SLOT_ON
: // 0x03.Y.0-14
466 case HPC_SLOT_ATTNOFF
: // 0x04.N.0-14
467 case HPC_SLOT_ATTNON
: // 0x05.N.0-14
468 case HPC_SLOT_BLINKLED
: // 0x13.N.0-14
472 case HPC_BUS_33CONVMODE
:
473 case HPC_BUS_66CONVMODE
:
474 case HPC_BUS_66PCIXMODE
:
475 case HPC_BUS_100PCIXMODE
:
476 case HPC_BUS_133PCIXMODE
:
477 rc
= index
+ WPG_1ST_BUS_INDEX
- 1;
481 err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd
);
488 /*----------------------------------------------------------------------
489 * Name: hpc_readcmdtoindex()
491 * Action: convert a read command to proper index within a controller
493 * Return index, HPC_ERROR
494 *---------------------------------------------------------------------*/
495 static u8
hpc_readcmdtoindex (u8 cmd
, u8 index
)
500 case READ_CTLRSTATUS
:
503 case READ_SLOTSTATUS
:
507 case READ_EXTSLOTSTATUS
:
508 rc
= index
+ WPG_1ST_EXTSLOT_INDEX
;
511 rc
= index
+ WPG_1ST_BUS_INDEX
- 1;
513 case READ_SLOTLATCHLOWREG
:
519 case READ_HPCOPTIONS
:
528 /*----------------------------------------------------------------------
529 * Name: HPCreadslot()
531 * Action: issue a READ command to HPC
533 * Input: pslot - cannot be NULL for READ_ALLSTAT
534 * pstatus - can be NULL for READ_ALLSTAT
536 * Return 0 or error codes
537 *---------------------------------------------------------------------*/
538 int ibmphp_hpc_readslot (struct slot
* pslot
, u8 cmd
, u8
* pstatus
)
540 void __iomem
*wpg_bbar
= NULL
;
541 struct controller
*ctlr_ptr
;
542 struct list_head
*pslotlist
;
547 debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __FUNCTION__
, pslot
, cmd
, pstatus
);
550 || ((pstatus
== NULL
) && (cmd
!= READ_ALLSTAT
) && (cmd
!= READ_BUSSTATUS
))) {
552 err ("%s - Error invalid pointer, rc[%d]\n", __FUNCTION__
, rc
);
556 if (cmd
== READ_BUSSTATUS
) {
557 busindex
= ibmphp_get_bus_index (pslot
->bus
);
560 err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__
, rc
);
563 index
= (u8
) busindex
;
565 index
= pslot
->ctlr_index
;
567 index
= hpc_readcmdtoindex (cmd
, index
);
569 if (index
== HPC_ERROR
) {
571 err ("%s - Exit Error:invalid index, rc[%d]\n", __FUNCTION__
, rc
);
575 ctlr_ptr
= pslot
->ctrl
;
579 //--------------------------------------------------------------------
580 // map physical address to logical address
581 //--------------------------------------------------------------------
582 if ((ctlr_ptr
->ctlr_type
== 2) || (ctlr_ptr
->ctlr_type
== 4))
583 wpg_bbar
= ioremap (ctlr_ptr
->u
.wpeg_ctlr
.wpegbbar
, WPG_I2C_IOREMAP_SIZE
);
585 //--------------------------------------------------------------------
586 // check controller status before reading
587 //--------------------------------------------------------------------
588 rc
= hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT
, ctlr_ptr
, wpg_bbar
, &status
);
592 // update the slot structure
593 pslot
->ctrl
->status
= status
;
594 pslot
->status
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
595 rc
= hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT
, ctlr_ptr
, wpg_bbar
,
598 pslot
->ext_status
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
+ WPG_1ST_EXTSLOT_INDEX
);
602 case READ_SLOTSTATUS
:
603 // DO NOT update the slot structure
604 *pstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
607 case READ_EXTSLOTSTATUS
:
608 // DO NOT update the slot structure
609 *pstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
612 case READ_CTLRSTATUS
:
613 // DO NOT update the slot structure
618 pslot
->busstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
621 *pstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
623 case READ_HPCOPTIONS
:
624 *pstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
626 case READ_SLOTLATCHLOWREG
:
627 // DO NOT update the slot structure
628 *pstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
633 list_for_each (pslotlist
, &ibmphp_slot_head
) {
634 pslot
= list_entry (pslotlist
, struct slot
, ibm_slot_list
);
635 index
= pslot
->ctlr_index
;
636 rc
= hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT
, ctlr_ptr
,
639 pslot
->status
= ctrl_read (ctlr_ptr
, wpg_bbar
, index
);
640 rc
= hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT
,
641 ctlr_ptr
, wpg_bbar
, &status
);
644 ctrl_read (ctlr_ptr
, wpg_bbar
,
645 index
+ WPG_1ST_EXTSLOT_INDEX
);
647 err ("%s - Error ctrl_read failed\n", __FUNCTION__
);
658 //--------------------------------------------------------------------
660 //--------------------------------------------------------------------
662 // remove physical to logical address mapping
663 if ((ctlr_ptr
->ctlr_type
== 2) || (ctlr_ptr
->ctlr_type
== 4))
668 debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__
, rc
);
672 /*----------------------------------------------------------------------
673 * Name: ibmphp_hpc_writeslot()
675 * Action: issue a WRITE command to HPC
676 *---------------------------------------------------------------------*/
677 int ibmphp_hpc_writeslot (struct slot
* pslot
, u8 cmd
)
679 void __iomem
*wpg_bbar
= NULL
;
680 struct controller
*ctlr_ptr
;
687 debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __FUNCTION__
, pslot
, cmd
);
690 err ("%s - Error Exit rc[%d]\n", __FUNCTION__
, rc
);
694 if ((cmd
== HPC_BUS_33CONVMODE
) || (cmd
== HPC_BUS_66CONVMODE
) ||
695 (cmd
== HPC_BUS_66PCIXMODE
) || (cmd
== HPC_BUS_100PCIXMODE
) ||
696 (cmd
== HPC_BUS_133PCIXMODE
)) {
697 busindex
= ibmphp_get_bus_index (pslot
->bus
);
700 err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__
, rc
);
703 index
= (u8
) busindex
;
705 index
= pslot
->ctlr_index
;
707 index
= hpc_writecmdtoindex (cmd
, index
);
709 if (index
== HPC_ERROR
) {
711 err ("%s - Error Exit rc[%d]\n", __FUNCTION__
, rc
);
715 ctlr_ptr
= pslot
->ctrl
;
719 //--------------------------------------------------------------------
720 // map physical address to logical address
721 //--------------------------------------------------------------------
722 if ((ctlr_ptr
->ctlr_type
== 2) || (ctlr_ptr
->ctlr_type
== 4)) {
723 wpg_bbar
= ioremap (ctlr_ptr
->u
.wpeg_ctlr
.wpegbbar
, WPG_I2C_IOREMAP_SIZE
);
725 debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __FUNCTION__
,
726 ctlr_ptr
->ctlr_id
, (ulong
) (ctlr_ptr
->u
.wpeg_ctlr
.wpegbbar
), (ulong
) wpg_bbar
,
727 ctlr_ptr
->u
.wpeg_ctlr
.i2c_addr
);
729 //--------------------------------------------------------------------
730 // check controller status before writing
731 //--------------------------------------------------------------------
732 rc
= hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT
, ctlr_ptr
, wpg_bbar
, &status
);
735 ctrl_write (ctlr_ptr
, wpg_bbar
, index
, cmd
);
737 //--------------------------------------------------------------------
738 // check controller is still not working on the command
739 //--------------------------------------------------------------------
740 timeout
= CMD_COMPLETE_TOUT_SEC
;
743 rc
= hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT
, ctlr_ptr
, wpg_bbar
,
746 if (NEEDTOCHECK_CMDSTATUS (cmd
)) {
747 if (CTLR_FINISHED (status
) == HPC_CTLR_FINISHED_YES
)
756 err ("%s - Error command complete timeout\n", __FUNCTION__
);
762 ctlr_ptr
->status
= status
;
766 // remove physical to logical address mapping
767 if ((ctlr_ptr
->ctlr_type
== 2) || (ctlr_ptr
->ctlr_type
== 4))
771 debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__
, rc
);
775 /*----------------------------------------------------------------------
776 * Name: get_hpc_access()
778 * Action: make sure only one process can access HPC at one time
779 *---------------------------------------------------------------------*/
780 static void get_hpc_access (void)
782 mutex_lock(&sem_hpcaccess
);
785 /*----------------------------------------------------------------------
786 * Name: free_hpc_access()
787 *---------------------------------------------------------------------*/
788 void free_hpc_access (void)
790 mutex_unlock(&sem_hpcaccess
);
793 /*----------------------------------------------------------------------
794 * Name: ibmphp_lock_operations()
796 * Action: make sure only one process can change the data structure
797 *---------------------------------------------------------------------*/
798 void ibmphp_lock_operations (void)
800 down (&semOperations
);
804 /*----------------------------------------------------------------------
805 * Name: ibmphp_unlock_operations()
806 *---------------------------------------------------------------------*/
807 void ibmphp_unlock_operations (void)
809 debug ("%s - Entry\n", __FUNCTION__
);
812 debug ("%s - Exit\n", __FUNCTION__
);
815 /*----------------------------------------------------------------------
817 *---------------------------------------------------------------------*/
818 #define POLL_LATCH_REGISTER 0
821 static void poll_hpc (void)
824 struct slot
*pslot
= NULL
;
825 struct list_head
*pslotlist
;
827 int poll_state
= POLL_LATCH_REGISTER
;
828 u8 oldlatchlow
= 0x00;
829 u8 curlatchlow
= 0x00;
831 u8 ctrl_count
= 0x00;
833 debug ("%s - Entry\n", __FUNCTION__
);
835 while (!ibmphp_shutdown
) {
839 /* try to get the lock to do some kind of hardware access */
840 down (&semOperations
);
842 switch (poll_state
) {
843 case POLL_LATCH_REGISTER
:
844 oldlatchlow
= curlatchlow
;
846 list_for_each (pslotlist
, &ibmphp_slot_head
) {
847 if (ctrl_count
>= ibmphp_get_total_controllers())
849 pslot
= list_entry (pslotlist
, struct slot
, ibm_slot_list
);
850 if (pslot
->ctrl
->ctlr_relative_id
== ctrl_count
) {
852 if (READ_SLOT_LATCH (pslot
->ctrl
)) {
853 rc
= ibmphp_hpc_readslot (pslot
,
854 READ_SLOTLATCHLOWREG
,
856 if (oldlatchlow
!= curlatchlow
)
857 process_changeinlatch (oldlatchlow
,
864 poll_state
= POLL_SLEEP
;
867 list_for_each (pslotlist
, &ibmphp_slot_head
) {
868 pslot
= list_entry (pslotlist
, struct slot
, ibm_slot_list
);
869 // make a copy of the old status
870 memcpy ((void *) &myslot
, (void *) pslot
,
871 sizeof (struct slot
));
872 rc
= ibmphp_hpc_readslot (pslot
, READ_ALLSTAT
, NULL
);
873 if ((myslot
.status
!= pslot
->status
)
874 || (myslot
.ext_status
!= pslot
->ext_status
))
875 process_changeinstatus (pslot
, &myslot
);
878 list_for_each (pslotlist
, &ibmphp_slot_head
) {
879 if (ctrl_count
>= ibmphp_get_total_controllers())
881 pslot
= list_entry (pslotlist
, struct slot
, ibm_slot_list
);
882 if (pslot
->ctrl
->ctlr_relative_id
== ctrl_count
) {
884 if (READ_SLOT_LATCH (pslot
->ctrl
))
885 rc
= ibmphp_hpc_readslot (pslot
,
886 READ_SLOTLATCHLOWREG
,
891 poll_state
= POLL_SLEEP
;
894 /* don't sleep with a lock on the hardware */
896 msleep(POLL_INTERVAL_SEC
* 1000);
901 down (&semOperations
);
903 if (poll_count
>= POLL_LATCH_CNT
) {
905 poll_state
= POLL_SLOTS
;
907 poll_state
= POLL_LATCH_REGISTER
;
910 /* give up the hardware semaphore */
912 /* sleep for a short time just for good measure */
916 debug ("%s - Exit\n", __FUNCTION__
);
920 /*----------------------------------------------------------------------
921 * Name: process_changeinstatus
923 * Action: compare old and new slot status, process the change in status
925 * Input: pointer to slot struct, old slot struct
927 * Return 0 or error codes
934 *---------------------------------------------------------------------*/
935 static int process_changeinstatus (struct slot
*pslot
, struct slot
*poldslot
)
942 debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot
, poldslot
);
944 // bit 0 - HPC_SLOT_POWER
945 if ((pslot
->status
& 0x01) != (poldslot
->status
& 0x01))
948 // bit 1 - HPC_SLOT_CONNECT
951 // bit 2 - HPC_SLOT_ATTN
952 if ((pslot
->status
& 0x04) != (poldslot
->status
& 0x04))
955 // bit 3 - HPC_SLOT_PRSNT2
956 // bit 4 - HPC_SLOT_PRSNT1
957 if (((pslot
->status
& 0x08) != (poldslot
->status
& 0x08))
958 || ((pslot
->status
& 0x10) != (poldslot
->status
& 0x10)))
961 // bit 5 - HPC_SLOT_PWRGD
962 if ((pslot
->status
& 0x20) != (poldslot
->status
& 0x20))
963 // OFF -> ON: ignore, ON -> OFF: disable slot
964 if ((poldslot
->status
& 0x20) && (SLOT_CONNECT (poldslot
->status
) == HPC_SLOT_CONNECTED
) && (SLOT_PRESENT (poldslot
->status
)))
967 // bit 6 - HPC_SLOT_BUS_SPEED
970 // bit 7 - HPC_SLOT_LATCH
971 if ((pslot
->status
& 0x80) != (poldslot
->status
& 0x80)) {
974 if (pslot
->status
& 0x80) {
975 if (SLOT_PWRGD (pslot
->status
)) {
976 // power goes on and off after closing latch
977 // check again to make sure power is still ON
979 rc
= ibmphp_hpc_readslot (pslot
, READ_SLOTSTATUS
, &status
);
980 if (SLOT_PWRGD (status
))
982 else // overwrite power in pslot to OFF
983 pslot
->status
&= ~HPC_SLOT_POWER
;
987 else if ((SLOT_PWRGD (poldslot
->status
) == HPC_SLOT_PWRGD_GOOD
)
988 && (SLOT_CONNECT (poldslot
->status
) == HPC_SLOT_CONNECTED
) && (SLOT_PRESENT (poldslot
->status
))) {
993 // bit 4 - HPC_SLOT_BLINK_ATTN
994 if ((pslot
->ext_status
& 0x08) != (poldslot
->ext_status
& 0x08))
998 debug ("process_changeinstatus - disable slot\n");
1000 rc
= ibmphp_do_disable_slot (pslot
);
1003 if (update
|| disable
) {
1004 ibmphp_update_slot_info (pslot
);
1007 debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __FUNCTION__
, rc
, disable
, update
);
1012 /*----------------------------------------------------------------------
1013 * Name: process_changeinlatch
1015 * Action: compare old and new latch reg status, process the change
1017 * Input: old and current latch register status
1019 * Return 0 or error codes
1021 *---------------------------------------------------------------------*/
1022 static int process_changeinlatch (u8 old
, u8
new, struct controller
*ctrl
)
1024 struct slot myslot
, *pslot
;
1029 debug ("%s - Entry old[%x], new[%x]\n", __FUNCTION__
, old
, new);
1030 // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots
1032 for (i
= ctrl
->starting_slot_num
; i
<= ctrl
->ending_slot_num
; i
++) {
1034 if ((mask
& old
) != (mask
& new)) {
1035 pslot
= ibmphp_get_slot_from_physical_num (i
);
1037 memcpy ((void *) &myslot
, (void *) pslot
, sizeof (struct slot
));
1038 rc
= ibmphp_hpc_readslot (pslot
, READ_ALLSTAT
, NULL
);
1039 debug ("%s - call process_changeinstatus for slot[%d]\n", __FUNCTION__
, i
);
1040 process_changeinstatus (pslot
, &myslot
);
1043 err ("%s - Error bad pointer for slot[%d]\n", __FUNCTION__
, i
);
1047 debug ("%s - Exit rc[%d]\n", __FUNCTION__
, rc
);
1051 /*----------------------------------------------------------------------
1052 * Name: hpc_poll_thread
1058 *---------------------------------------------------------------------*/
1059 static int hpc_poll_thread (void *data
)
1061 debug ("%s - Entry\n", __FUNCTION__
);
1063 daemonize("hpc_poll");
1064 allow_signal(SIGKILL
);
1069 debug ("%s - Exit\n", __FUNCTION__
);
1074 /*----------------------------------------------------------------------
1075 * Name: ibmphp_hpc_start_poll_thread
1077 * Action: start polling thread
1078 *---------------------------------------------------------------------*/
1079 int __init
ibmphp_hpc_start_poll_thread (void)
1083 debug ("%s - Entry\n", __FUNCTION__
);
1085 tid_poll
= kernel_thread (hpc_poll_thread
, NULL
, 0);
1087 err ("%s - Error, thread not started\n", __FUNCTION__
);
1091 debug ("%s - Exit tid_poll[%d] rc[%d]\n", __FUNCTION__
, tid_poll
, rc
);
1095 /*----------------------------------------------------------------------
1096 * Name: ibmphp_hpc_stop_poll_thread
1098 * Action: stop polling thread and cleanup
1099 *---------------------------------------------------------------------*/
1100 void __exit
ibmphp_hpc_stop_poll_thread (void)
1102 debug ("%s - Entry\n", __FUNCTION__
);
1104 ibmphp_shutdown
= 1;
1105 debug ("before locking operations \n");
1106 ibmphp_lock_operations ();
1107 debug ("after locking operations \n");
1109 // wait for poll thread to exit
1110 debug ("before sem_exit down \n");
1112 debug ("after sem_exit down \n");
1115 debug ("before free_hpc_access \n");
1117 debug ("after free_hpc_access \n");
1118 ibmphp_unlock_operations ();
1119 debug ("after unlock operations \n");
1121 debug ("after sem exit up\n");
1123 debug ("%s - Exit\n", __FUNCTION__
);
1126 /*----------------------------------------------------------------------
1127 * Name: hpc_wait_ctlr_notworking
1129 * Action: wait until the controller is in a not working state
1131 * Return 0, HPC_ERROR
1133 *---------------------------------------------------------------------*/
1134 static int hpc_wait_ctlr_notworking (int timeout
, struct controller
*ctlr_ptr
, void __iomem
*wpg_bbar
,
1140 debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout
);
1143 *pstatus
= ctrl_read (ctlr_ptr
, wpg_bbar
, WPG_CTLR_INDEX
);
1144 if (*pstatus
== HPC_ERROR
) {
1148 if (CTLR_WORKING (*pstatus
) == HPC_CTLR_WORKING_NO
)
1154 err ("HPCreadslot - Error ctlr timeout\n");
1160 debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc
, *pstatus
);