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[IA64] update sn2_defconfig
[deliverable/linux.git] / drivers / pci / hotplug / pciehp_hpc.c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42 #ifdef DEBUG
43 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
44 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
45 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
46 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
47 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
48 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
49 /* Redefine this flagword to set debug level */
50 #define DEBUG_LEVEL DBG_K_STANDARD
51
52 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
53
54 #define DBG_PRINT( dbg_flags, args... ) \
55 do { \
56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
57 { \
58 int len; \
59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
60 __FILE__, __LINE__, __FUNCTION__ ); \
61 sprintf( __dbg_str_buf + len, args ); \
62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
63 } \
64 } while (0)
65
66 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
67 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
68 #else
69 #define DEFINE_DBG_BUFFER
70 #define DBG_ENTER_ROUTINE
71 #define DBG_LEAVE_ROUTINE
72 #endif /* DEBUG */
73
74 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
75
76 struct ctrl_reg {
77 u8 cap_id;
78 u8 nxt_ptr;
79 u16 cap_reg;
80 u32 dev_cap;
81 u16 dev_ctrl;
82 u16 dev_status;
83 u32 lnk_cap;
84 u16 lnk_ctrl;
85 u16 lnk_status;
86 u32 slot_cap;
87 u16 slot_ctrl;
88 u16 slot_status;
89 u16 root_ctrl;
90 u16 rsvp;
91 u32 root_status;
92 } __attribute__ ((packed));
93
94 /* offsets to the controller registers based on the above structure layout */
95 enum ctrl_offsets {
96 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
97 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
98 CAPREG = offsetof(struct ctrl_reg, cap_reg),
99 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
100 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
101 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
102 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
103 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
104 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
105 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
106 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
107 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
108 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
109 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
110 };
111
112 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
113 {
114 struct pci_dev *dev = ctrl->pci_dev;
115 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
116 }
117
118 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
119 {
120 struct pci_dev *dev = ctrl->pci_dev;
121 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
122 }
123
124 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
125 {
126 struct pci_dev *dev = ctrl->pci_dev;
127 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
128 }
129
130 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
131 {
132 struct pci_dev *dev = ctrl->pci_dev;
133 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
134 }
135
136 /* Field definitions in PCI Express Capabilities Register */
137 #define CAP_VER 0x000F
138 #define DEV_PORT_TYPE 0x00F0
139 #define SLOT_IMPL 0x0100
140 #define MSG_NUM 0x3E00
141
142 /* Device or Port Type */
143 #define NAT_ENDPT 0x00
144 #define LEG_ENDPT 0x01
145 #define ROOT_PORT 0x04
146 #define UP_STREAM 0x05
147 #define DN_STREAM 0x06
148 #define PCIE_PCI_BRDG 0x07
149 #define PCI_PCIE_BRDG 0x10
150
151 /* Field definitions in Device Capabilities Register */
152 #define DATTN_BUTTN_PRSN 0x1000
153 #define DATTN_LED_PRSN 0x2000
154 #define DPWR_LED_PRSN 0x4000
155
156 /* Field definitions in Link Capabilities Register */
157 #define MAX_LNK_SPEED 0x000F
158 #define MAX_LNK_WIDTH 0x03F0
159
160 /* Link Width Encoding */
161 #define LNK_X1 0x01
162 #define LNK_X2 0x02
163 #define LNK_X4 0x04
164 #define LNK_X8 0x08
165 #define LNK_X12 0x0C
166 #define LNK_X16 0x10
167 #define LNK_X32 0x20
168
169 /*Field definitions of Link Status Register */
170 #define LNK_SPEED 0x000F
171 #define NEG_LINK_WD 0x03F0
172 #define LNK_TRN_ERR 0x0400
173 #define LNK_TRN 0x0800
174 #define SLOT_CLK_CONF 0x1000
175
176 /* Field definitions in Slot Capabilities Register */
177 #define ATTN_BUTTN_PRSN 0x00000001
178 #define PWR_CTRL_PRSN 0x00000002
179 #define MRL_SENS_PRSN 0x00000004
180 #define ATTN_LED_PRSN 0x00000008
181 #define PWR_LED_PRSN 0x00000010
182 #define HP_SUPR_RM_SUP 0x00000020
183 #define HP_CAP 0x00000040
184 #define SLOT_PWR_VALUE 0x000003F8
185 #define SLOT_PWR_LIMIT 0x00000C00
186 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
187
188 /* Field definitions in Slot Control Register */
189 #define ATTN_BUTTN_ENABLE 0x0001
190 #define PWR_FAULT_DETECT_ENABLE 0x0002
191 #define MRL_DETECT_ENABLE 0x0004
192 #define PRSN_DETECT_ENABLE 0x0008
193 #define CMD_CMPL_INTR_ENABLE 0x0010
194 #define HP_INTR_ENABLE 0x0020
195 #define ATTN_LED_CTRL 0x00C0
196 #define PWR_LED_CTRL 0x0300
197 #define PWR_CTRL 0x0400
198 #define EMI_CTRL 0x0800
199
200 /* Attention indicator and Power indicator states */
201 #define LED_ON 0x01
202 #define LED_BLINK 0x10
203 #define LED_OFF 0x11
204
205 /* Power Control Command */
206 #define POWER_ON 0
207 #define POWER_OFF 0x0400
208
209 /* EMI Status defines */
210 #define EMI_DISENGAGED 0
211 #define EMI_ENGAGED 1
212
213 /* Field definitions in Slot Status Register */
214 #define ATTN_BUTTN_PRESSED 0x0001
215 #define PWR_FAULT_DETECTED 0x0002
216 #define MRL_SENS_CHANGED 0x0004
217 #define PRSN_DETECT_CHANGED 0x0008
218 #define CMD_COMPLETED 0x0010
219 #define MRL_STATE 0x0020
220 #define PRSN_STATE 0x0040
221 #define EMI_STATE 0x0080
222 #define EMI_STATUS_BIT 7
223
224 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
225
226 static irqreturn_t pcie_isr(int irq, void *dev_id);
227 static void start_int_poll_timer(struct controller *ctrl, int sec);
228
229 /* This is the interrupt polling timeout function. */
230 static void int_poll_timeout(unsigned long data)
231 {
232 struct controller *ctrl = (struct controller *)data;
233
234 DBG_ENTER_ROUTINE
235
236 /* Poll for interrupt events. regs == NULL => polling */
237 pcie_isr(0, ctrl);
238
239 init_timer(&ctrl->poll_timer);
240 if (!pciehp_poll_time)
241 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
242
243 start_int_poll_timer(ctrl, pciehp_poll_time);
244 }
245
246 /* This function starts the interrupt polling timer. */
247 static void start_int_poll_timer(struct controller *ctrl, int sec)
248 {
249 /* Clamp to sane value */
250 if ((sec <= 0) || (sec > 60))
251 sec = 2;
252
253 ctrl->poll_timer.function = &int_poll_timeout;
254 ctrl->poll_timer.data = (unsigned long)ctrl;
255 ctrl->poll_timer.expires = jiffies + sec * HZ;
256 add_timer(&ctrl->poll_timer);
257 }
258
259 static inline int pcie_wait_cmd(struct controller *ctrl)
260 {
261 int retval = 0;
262 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
263 unsigned long timeout = msecs_to_jiffies(msecs);
264 int rc;
265
266 rc = wait_event_interruptible_timeout(ctrl->queue,
267 !ctrl->cmd_busy, timeout);
268 if (!rc)
269 dbg("Command not completed in 1000 msec\n");
270 else if (rc < 0) {
271 retval = -EINTR;
272 info("Command was interrupted by a signal\n");
273 }
274
275 return retval;
276 }
277
278 /**
279 * pcie_write_cmd - Issue controller command
280 * @slot: slot to which the command is issued
281 * @cmd: command value written to slot control register
282 * @mask: bitmask of slot control register to be modified
283 */
284 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
285 {
286 struct controller *ctrl = slot->ctrl;
287 int retval = 0;
288 u16 slot_status;
289 u16 slot_ctrl;
290 unsigned long flags;
291
292 DBG_ENTER_ROUTINE
293
294 mutex_lock(&ctrl->ctrl_lock);
295
296 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
297 if (retval) {
298 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
299 goto out;
300 }
301
302 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
303 /* After 1 sec and CMD_COMPLETED still not set, just
304 proceed forward to issue the next command according
305 to spec. Just print out the error message */
306 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
307 __FUNCTION__);
308 }
309
310 spin_lock_irqsave(&ctrl->lock, flags);
311 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
312 if (retval) {
313 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
314 goto out_spin_unlock;
315 }
316
317 slot_ctrl &= ~mask;
318 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
319
320 ctrl->cmd_busy = 1;
321 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
322 if (retval)
323 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
324
325 out_spin_unlock:
326 spin_unlock_irqrestore(&ctrl->lock, flags);
327
328 /*
329 * Wait for command completion.
330 */
331 if (!retval)
332 retval = pcie_wait_cmd(ctrl);
333 out:
334 mutex_unlock(&ctrl->ctrl_lock);
335 DBG_LEAVE_ROUTINE
336 return retval;
337 }
338
339 static int hpc_check_lnk_status(struct controller *ctrl)
340 {
341 u16 lnk_status;
342 int retval = 0;
343
344 DBG_ENTER_ROUTINE
345
346 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
347 if (retval) {
348 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
349 return retval;
350 }
351
352 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
353 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
354 !(lnk_status & NEG_LINK_WD)) {
355 err("%s : Link Training Error occurs \n", __FUNCTION__);
356 retval = -1;
357 return retval;
358 }
359
360 DBG_LEAVE_ROUTINE
361 return retval;
362 }
363
364
365 static int hpc_get_attention_status(struct slot *slot, u8 *status)
366 {
367 struct controller *ctrl = slot->ctrl;
368 u16 slot_ctrl;
369 u8 atten_led_state;
370 int retval = 0;
371
372 DBG_ENTER_ROUTINE
373
374 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
375 if (retval) {
376 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
377 return retval;
378 }
379
380 dbg("%s: SLOTCTRL %x, value read %x\n",
381 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
382
383 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
384
385 switch (atten_led_state) {
386 case 0:
387 *status = 0xFF; /* Reserved */
388 break;
389 case 1:
390 *status = 1; /* On */
391 break;
392 case 2:
393 *status = 2; /* Blink */
394 break;
395 case 3:
396 *status = 0; /* Off */
397 break;
398 default:
399 *status = 0xFF;
400 break;
401 }
402
403 DBG_LEAVE_ROUTINE
404 return 0;
405 }
406
407 static int hpc_get_power_status(struct slot *slot, u8 *status)
408 {
409 struct controller *ctrl = slot->ctrl;
410 u16 slot_ctrl;
411 u8 pwr_state;
412 int retval = 0;
413
414 DBG_ENTER_ROUTINE
415
416 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
417 if (retval) {
418 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
419 return retval;
420 }
421 dbg("%s: SLOTCTRL %x value read %x\n",
422 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
423
424 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
425
426 switch (pwr_state) {
427 case 0:
428 *status = 1;
429 break;
430 case 1:
431 *status = 0;
432 break;
433 default:
434 *status = 0xFF;
435 break;
436 }
437
438 DBG_LEAVE_ROUTINE
439 return retval;
440 }
441
442
443 static int hpc_get_latch_status(struct slot *slot, u8 *status)
444 {
445 struct controller *ctrl = slot->ctrl;
446 u16 slot_status;
447 int retval = 0;
448
449 DBG_ENTER_ROUTINE
450
451 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
452 if (retval) {
453 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
454 return retval;
455 }
456
457 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
458
459 DBG_LEAVE_ROUTINE
460 return 0;
461 }
462
463 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
464 {
465 struct controller *ctrl = slot->ctrl;
466 u16 slot_status;
467 u8 card_state;
468 int retval = 0;
469
470 DBG_ENTER_ROUTINE
471
472 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
473 if (retval) {
474 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
475 return retval;
476 }
477 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
478 *status = (card_state == 1) ? 1 : 0;
479
480 DBG_LEAVE_ROUTINE
481 return 0;
482 }
483
484 static int hpc_query_power_fault(struct slot *slot)
485 {
486 struct controller *ctrl = slot->ctrl;
487 u16 slot_status;
488 u8 pwr_fault;
489 int retval = 0;
490
491 DBG_ENTER_ROUTINE
492
493 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
494 if (retval) {
495 err("%s: Cannot check for power fault\n", __FUNCTION__);
496 return retval;
497 }
498 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
499
500 DBG_LEAVE_ROUTINE
501 return pwr_fault;
502 }
503
504 static int hpc_get_emi_status(struct slot *slot, u8 *status)
505 {
506 struct controller *ctrl = slot->ctrl;
507 u16 slot_status;
508 int retval = 0;
509
510 DBG_ENTER_ROUTINE
511
512 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
513 if (retval) {
514 err("%s : Cannot check EMI status\n", __FUNCTION__);
515 return retval;
516 }
517 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
518
519 DBG_LEAVE_ROUTINE
520 return retval;
521 }
522
523 static int hpc_toggle_emi(struct slot *slot)
524 {
525 u16 slot_cmd;
526 u16 cmd_mask;
527 int rc;
528
529 DBG_ENTER_ROUTINE
530
531 slot_cmd = EMI_CTRL;
532 cmd_mask = EMI_CTRL;
533 if (!pciehp_poll_mode) {
534 slot_cmd = slot_cmd | HP_INTR_ENABLE;
535 cmd_mask = cmd_mask | HP_INTR_ENABLE;
536 }
537
538 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
539 slot->last_emi_toggle = get_seconds();
540 DBG_LEAVE_ROUTINE
541 return rc;
542 }
543
544 static int hpc_set_attention_status(struct slot *slot, u8 value)
545 {
546 struct controller *ctrl = slot->ctrl;
547 u16 slot_cmd;
548 u16 cmd_mask;
549 int rc;
550
551 DBG_ENTER_ROUTINE
552
553 cmd_mask = ATTN_LED_CTRL;
554 switch (value) {
555 case 0 : /* turn off */
556 slot_cmd = 0x00C0;
557 break;
558 case 1: /* turn on */
559 slot_cmd = 0x0040;
560 break;
561 case 2: /* turn blink */
562 slot_cmd = 0x0080;
563 break;
564 default:
565 return -1;
566 }
567 if (!pciehp_poll_mode) {
568 slot_cmd = slot_cmd | HP_INTR_ENABLE;
569 cmd_mask = cmd_mask | HP_INTR_ENABLE;
570 }
571
572 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
573 dbg("%s: SLOTCTRL %x write cmd %x\n",
574 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
575
576 DBG_LEAVE_ROUTINE
577 return rc;
578 }
579
580
581 static void hpc_set_green_led_on(struct slot *slot)
582 {
583 struct controller *ctrl = slot->ctrl;
584 u16 slot_cmd;
585 u16 cmd_mask;
586
587 DBG_ENTER_ROUTINE
588
589 slot_cmd = 0x0100;
590 cmd_mask = PWR_LED_CTRL;
591 if (!pciehp_poll_mode) {
592 slot_cmd = slot_cmd | HP_INTR_ENABLE;
593 cmd_mask = cmd_mask | HP_INTR_ENABLE;
594 }
595
596 pcie_write_cmd(slot, slot_cmd, cmd_mask);
597
598 dbg("%s: SLOTCTRL %x write cmd %x\n",
599 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
600 DBG_LEAVE_ROUTINE
601 return;
602 }
603
604 static void hpc_set_green_led_off(struct slot *slot)
605 {
606 struct controller *ctrl = slot->ctrl;
607 u16 slot_cmd;
608 u16 cmd_mask;
609
610 DBG_ENTER_ROUTINE
611
612 slot_cmd = 0x0300;
613 cmd_mask = PWR_LED_CTRL;
614 if (!pciehp_poll_mode) {
615 slot_cmd = slot_cmd | HP_INTR_ENABLE;
616 cmd_mask = cmd_mask | HP_INTR_ENABLE;
617 }
618
619 pcie_write_cmd(slot, slot_cmd, cmd_mask);
620 dbg("%s: SLOTCTRL %x write cmd %x\n",
621 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
622
623 DBG_LEAVE_ROUTINE
624 return;
625 }
626
627 static void hpc_set_green_led_blink(struct slot *slot)
628 {
629 struct controller *ctrl = slot->ctrl;
630 u16 slot_cmd;
631 u16 cmd_mask;
632
633 DBG_ENTER_ROUTINE
634
635 slot_cmd = 0x0200;
636 cmd_mask = PWR_LED_CTRL;
637 if (!pciehp_poll_mode) {
638 slot_cmd = slot_cmd | HP_INTR_ENABLE;
639 cmd_mask = cmd_mask | HP_INTR_ENABLE;
640 }
641
642 pcie_write_cmd(slot, slot_cmd, cmd_mask);
643
644 dbg("%s: SLOTCTRL %x write cmd %x\n",
645 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
646 DBG_LEAVE_ROUTINE
647 return;
648 }
649
650 static void hpc_release_ctlr(struct controller *ctrl)
651 {
652 DBG_ENTER_ROUTINE
653
654 if (pciehp_poll_mode)
655 del_timer(&ctrl->poll_timer);
656 else
657 free_irq(ctrl->pci_dev->irq, ctrl);
658
659 /*
660 * If this is the last controller to be released, destroy the
661 * pciehp work queue
662 */
663 if (atomic_dec_and_test(&pciehp_num_controllers))
664 destroy_workqueue(pciehp_wq);
665
666 DBG_LEAVE_ROUTINE
667 }
668
669 static int hpc_power_on_slot(struct slot * slot)
670 {
671 struct controller *ctrl = slot->ctrl;
672 u16 slot_cmd;
673 u16 cmd_mask;
674 u16 slot_status;
675 int retval = 0;
676
677 DBG_ENTER_ROUTINE
678
679 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
680
681 /* Clear sticky power-fault bit from previous power failures */
682 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
683 if (retval) {
684 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
685 return retval;
686 }
687 slot_status &= PWR_FAULT_DETECTED;
688 if (slot_status) {
689 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
690 if (retval) {
691 err("%s: Cannot write to SLOTSTATUS register\n",
692 __FUNCTION__);
693 return retval;
694 }
695 }
696
697 slot_cmd = POWER_ON;
698 cmd_mask = PWR_CTRL;
699 /* Enable detection that we turned off at slot power-off time */
700 if (!pciehp_poll_mode) {
701 slot_cmd = slot_cmd |
702 PWR_FAULT_DETECT_ENABLE |
703 MRL_DETECT_ENABLE |
704 PRSN_DETECT_ENABLE |
705 HP_INTR_ENABLE;
706 cmd_mask = cmd_mask |
707 PWR_FAULT_DETECT_ENABLE |
708 MRL_DETECT_ENABLE |
709 PRSN_DETECT_ENABLE |
710 HP_INTR_ENABLE;
711 }
712
713 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
714
715 if (retval) {
716 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
717 return -1;
718 }
719 dbg("%s: SLOTCTRL %x write cmd %x\n",
720 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
721
722 DBG_LEAVE_ROUTINE
723
724 return retval;
725 }
726
727 static int hpc_power_off_slot(struct slot * slot)
728 {
729 struct controller *ctrl = slot->ctrl;
730 u16 slot_cmd;
731 u16 cmd_mask;
732 int retval = 0;
733
734 DBG_ENTER_ROUTINE
735
736 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
737
738 slot_cmd = POWER_OFF;
739 cmd_mask = PWR_CTRL;
740 /*
741 * If we get MRL or presence detect interrupts now, the isr
742 * will notice the sticky power-fault bit too and issue power
743 * indicator change commands. This will lead to an endless loop
744 * of command completions, since the power-fault bit remains on
745 * till the slot is powered on again.
746 */
747 if (!pciehp_poll_mode) {
748 slot_cmd = (slot_cmd &
749 ~PWR_FAULT_DETECT_ENABLE &
750 ~MRL_DETECT_ENABLE &
751 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
752 cmd_mask = cmd_mask |
753 PWR_FAULT_DETECT_ENABLE |
754 MRL_DETECT_ENABLE |
755 PRSN_DETECT_ENABLE |
756 HP_INTR_ENABLE;
757 }
758
759 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
760 if (retval) {
761 err("%s: Write command failed!\n", __FUNCTION__);
762 return -1;
763 }
764 dbg("%s: SLOTCTRL %x write cmd %x\n",
765 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
766
767 DBG_LEAVE_ROUTINE
768
769 return retval;
770 }
771
772 static irqreturn_t pcie_isr(int irq, void *dev_id)
773 {
774 struct controller *ctrl = (struct controller *)dev_id;
775 u16 slot_status, intr_detect, intr_loc;
776 u16 temp_word;
777 int hp_slot = 0; /* only 1 slot per PCI Express port */
778 int rc = 0;
779 unsigned long flags;
780
781 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
782 if (rc) {
783 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
784 return IRQ_NONE;
785 }
786
787 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
788 PRSN_DETECT_CHANGED | CMD_COMPLETED );
789
790 intr_loc = slot_status & intr_detect;
791
792 /* Check to see if it was our interrupt */
793 if ( !intr_loc )
794 return IRQ_NONE;
795
796 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
797 /* Mask Hot-plug Interrupt Enable */
798 if (!pciehp_poll_mode) {
799 spin_lock_irqsave(&ctrl->lock, flags);
800 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
801 if (rc) {
802 err("%s: Cannot read SLOT_CTRL register\n",
803 __FUNCTION__);
804 spin_unlock_irqrestore(&ctrl->lock, flags);
805 return IRQ_NONE;
806 }
807
808 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
809 __FUNCTION__, temp_word);
810 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
811 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
812 if (rc) {
813 err("%s: Cannot write to SLOTCTRL register\n",
814 __FUNCTION__);
815 spin_unlock_irqrestore(&ctrl->lock, flags);
816 return IRQ_NONE;
817 }
818 spin_unlock_irqrestore(&ctrl->lock, flags);
819
820 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
821 if (rc) {
822 err("%s: Cannot read SLOT_STATUS register\n",
823 __FUNCTION__);
824 return IRQ_NONE;
825 }
826 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
827 __FUNCTION__, slot_status);
828
829 /* Clear command complete interrupt caused by this write */
830 temp_word = 0x1f;
831 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
832 if (rc) {
833 err("%s: Cannot write to SLOTSTATUS register\n",
834 __FUNCTION__);
835 return IRQ_NONE;
836 }
837 }
838
839 if (intr_loc & CMD_COMPLETED) {
840 /*
841 * Command Complete Interrupt Pending
842 */
843 ctrl->cmd_busy = 0;
844 wake_up_interruptible(&ctrl->queue);
845 }
846
847 if (intr_loc & MRL_SENS_CHANGED)
848 pciehp_handle_switch_change(hp_slot, ctrl);
849
850 if (intr_loc & ATTN_BUTTN_PRESSED)
851 pciehp_handle_attention_button(hp_slot, ctrl);
852
853 if (intr_loc & PRSN_DETECT_CHANGED)
854 pciehp_handle_presence_change(hp_slot, ctrl);
855
856 if (intr_loc & PWR_FAULT_DETECTED)
857 pciehp_handle_power_fault(hp_slot, ctrl);
858
859 /* Clear all events after serving them */
860 temp_word = 0x1F;
861 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
862 if (rc) {
863 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
864 return IRQ_NONE;
865 }
866 /* Unmask Hot-plug Interrupt Enable */
867 if (!pciehp_poll_mode) {
868 spin_lock_irqsave(&ctrl->lock, flags);
869 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
870 if (rc) {
871 err("%s: Cannot read SLOTCTRL register\n",
872 __FUNCTION__);
873 spin_unlock_irqrestore(&ctrl->lock, flags);
874 return IRQ_NONE;
875 }
876
877 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
878 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
879
880 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
881 if (rc) {
882 err("%s: Cannot write to SLOTCTRL register\n",
883 __FUNCTION__);
884 spin_unlock_irqrestore(&ctrl->lock, flags);
885 return IRQ_NONE;
886 }
887 spin_unlock_irqrestore(&ctrl->lock, flags);
888
889 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
890 if (rc) {
891 err("%s: Cannot read SLOT_STATUS register\n",
892 __FUNCTION__);
893 return IRQ_NONE;
894 }
895
896 /* Clear command complete interrupt caused by this write */
897 temp_word = 0x1F;
898 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
899 if (rc) {
900 err("%s: Cannot write to SLOTSTATUS failed\n",
901 __FUNCTION__);
902 return IRQ_NONE;
903 }
904 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
905 __FUNCTION__, temp_word);
906 }
907
908 return IRQ_HANDLED;
909 }
910
911 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
912 {
913 struct controller *ctrl = slot->ctrl;
914 enum pcie_link_speed lnk_speed;
915 u32 lnk_cap;
916 int retval = 0;
917
918 DBG_ENTER_ROUTINE
919
920 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
921 if (retval) {
922 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
923 return retval;
924 }
925
926 switch (lnk_cap & 0x000F) {
927 case 1:
928 lnk_speed = PCIE_2PT5GB;
929 break;
930 default:
931 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
932 break;
933 }
934
935 *value = lnk_speed;
936 dbg("Max link speed = %d\n", lnk_speed);
937 DBG_LEAVE_ROUTINE
938 return retval;
939 }
940
941 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
942 {
943 struct controller *ctrl = slot->ctrl;
944 enum pcie_link_width lnk_wdth;
945 u32 lnk_cap;
946 int retval = 0;
947
948 DBG_ENTER_ROUTINE
949
950 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
951 if (retval) {
952 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
953 return retval;
954 }
955
956 switch ((lnk_cap & 0x03F0) >> 4){
957 case 0:
958 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
959 break;
960 case 1:
961 lnk_wdth = PCIE_LNK_X1;
962 break;
963 case 2:
964 lnk_wdth = PCIE_LNK_X2;
965 break;
966 case 4:
967 lnk_wdth = PCIE_LNK_X4;
968 break;
969 case 8:
970 lnk_wdth = PCIE_LNK_X8;
971 break;
972 case 12:
973 lnk_wdth = PCIE_LNK_X12;
974 break;
975 case 16:
976 lnk_wdth = PCIE_LNK_X16;
977 break;
978 case 32:
979 lnk_wdth = PCIE_LNK_X32;
980 break;
981 default:
982 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
983 break;
984 }
985
986 *value = lnk_wdth;
987 dbg("Max link width = %d\n", lnk_wdth);
988 DBG_LEAVE_ROUTINE
989 return retval;
990 }
991
992 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
993 {
994 struct controller *ctrl = slot->ctrl;
995 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
996 int retval = 0;
997 u16 lnk_status;
998
999 DBG_ENTER_ROUTINE
1000
1001 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1002 if (retval) {
1003 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
1004 return retval;
1005 }
1006
1007 switch (lnk_status & 0x0F) {
1008 case 1:
1009 lnk_speed = PCIE_2PT5GB;
1010 break;
1011 default:
1012 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1013 break;
1014 }
1015
1016 *value = lnk_speed;
1017 dbg("Current link speed = %d\n", lnk_speed);
1018 DBG_LEAVE_ROUTINE
1019 return retval;
1020 }
1021
1022 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1023 {
1024 struct controller *ctrl = slot->ctrl;
1025 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1026 int retval = 0;
1027 u16 lnk_status;
1028
1029 DBG_ENTER_ROUTINE
1030
1031 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1032 if (retval) {
1033 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
1034 return retval;
1035 }
1036
1037 switch ((lnk_status & 0x03F0) >> 4){
1038 case 0:
1039 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1040 break;
1041 case 1:
1042 lnk_wdth = PCIE_LNK_X1;
1043 break;
1044 case 2:
1045 lnk_wdth = PCIE_LNK_X2;
1046 break;
1047 case 4:
1048 lnk_wdth = PCIE_LNK_X4;
1049 break;
1050 case 8:
1051 lnk_wdth = PCIE_LNK_X8;
1052 break;
1053 case 12:
1054 lnk_wdth = PCIE_LNK_X12;
1055 break;
1056 case 16:
1057 lnk_wdth = PCIE_LNK_X16;
1058 break;
1059 case 32:
1060 lnk_wdth = PCIE_LNK_X32;
1061 break;
1062 default:
1063 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1064 break;
1065 }
1066
1067 *value = lnk_wdth;
1068 dbg("Current link width = %d\n", lnk_wdth);
1069 DBG_LEAVE_ROUTINE
1070 return retval;
1071 }
1072
1073 static struct hpc_ops pciehp_hpc_ops = {
1074 .power_on_slot = hpc_power_on_slot,
1075 .power_off_slot = hpc_power_off_slot,
1076 .set_attention_status = hpc_set_attention_status,
1077 .get_power_status = hpc_get_power_status,
1078 .get_attention_status = hpc_get_attention_status,
1079 .get_latch_status = hpc_get_latch_status,
1080 .get_adapter_status = hpc_get_adapter_status,
1081 .get_emi_status = hpc_get_emi_status,
1082 .toggle_emi = hpc_toggle_emi,
1083
1084 .get_max_bus_speed = hpc_get_max_lnk_speed,
1085 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1086 .get_max_lnk_width = hpc_get_max_lnk_width,
1087 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1088
1089 .query_power_fault = hpc_query_power_fault,
1090 .green_led_on = hpc_set_green_led_on,
1091 .green_led_off = hpc_set_green_led_off,
1092 .green_led_blink = hpc_set_green_led_blink,
1093
1094 .release_ctlr = hpc_release_ctlr,
1095 .check_lnk_status = hpc_check_lnk_status,
1096 };
1097
1098 #ifdef CONFIG_ACPI
1099 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1100 {
1101 acpi_status status;
1102 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1103 struct pci_dev *pdev = dev;
1104 struct pci_bus *parent;
1105 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1106
1107 /*
1108 * Per PCI firmware specification, we should run the ACPI _OSC
1109 * method to get control of hotplug hardware before using it.
1110 * If an _OSC is missing, we look for an OSHP to do the same thing.
1111 * To handle different BIOS behavior, we look for _OSC and OSHP
1112 * within the scope of the hotplug controller and its parents, upto
1113 * the host bridge under which this controller exists.
1114 */
1115 while (!handle) {
1116 /*
1117 * This hotplug controller was not listed in the ACPI name
1118 * space at all. Try to get acpi handle of parent pci bus.
1119 */
1120 if (!pdev || !pdev->bus->parent)
1121 break;
1122 parent = pdev->bus->parent;
1123 dbg("Could not find %s in acpi namespace, trying parent\n",
1124 pci_name(pdev));
1125 if (!parent->self)
1126 /* Parent must be a host bridge */
1127 handle = acpi_get_pci_rootbridge_handle(
1128 pci_domain_nr(parent),
1129 parent->number);
1130 else
1131 handle = DEVICE_ACPI_HANDLE(
1132 &(parent->self->dev));
1133 pdev = parent->self;
1134 }
1135
1136 while (handle) {
1137 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1138 dbg("Trying to get hotplug control for %s \n",
1139 (char *)string.pointer);
1140 status = pci_osc_control_set(handle,
1141 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1142 if (status == AE_NOT_FOUND)
1143 status = acpi_run_oshp(handle);
1144 if (ACPI_SUCCESS(status)) {
1145 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1146 pci_name(dev), (char *)string.pointer);
1147 kfree(string.pointer);
1148 return 0;
1149 }
1150 if (acpi_root_bridge(handle))
1151 break;
1152 chandle = handle;
1153 status = acpi_get_parent(chandle, &handle);
1154 if (ACPI_FAILURE(status))
1155 break;
1156 }
1157
1158 err("Cannot get control of hotplug hardware for pci %s\n",
1159 pci_name(dev));
1160
1161 kfree(string.pointer);
1162 return -1;
1163 }
1164 #endif
1165
1166
1167
1168 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1169 {
1170 int rc;
1171 u16 temp_word;
1172 u16 cap_reg;
1173 u16 intr_enable = 0;
1174 u32 slot_cap;
1175 int cap_base;
1176 u16 slot_status, slot_ctrl;
1177 struct pci_dev *pdev;
1178
1179 DBG_ENTER_ROUTINE
1180
1181 pdev = dev->port;
1182 ctrl->pci_dev = pdev; /* save pci_dev in context */
1183
1184 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1185 __FUNCTION__, pdev->vendor, pdev->device);
1186
1187 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1188 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1189 goto abort_free_ctlr;
1190 }
1191
1192 ctrl->cap_base = cap_base;
1193
1194 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1195
1196 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1197 if (rc) {
1198 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1199 goto abort_free_ctlr;
1200 }
1201 dbg("%s: CAPREG offset %x cap_reg %x\n",
1202 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1203
1204 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1205 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1206 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1207 goto abort_free_ctlr;
1208 }
1209
1210 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1211 if (rc) {
1212 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1213 goto abort_free_ctlr;
1214 }
1215 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1216 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1217
1218 if (!(slot_cap & HP_CAP)) {
1219 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1220 goto abort_free_ctlr;
1221 }
1222 /* For debugging purpose */
1223 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1224 if (rc) {
1225 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1226 goto abort_free_ctlr;
1227 }
1228 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1229 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1230
1231 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1232 if (rc) {
1233 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1234 goto abort_free_ctlr;
1235 }
1236 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1237 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1238
1239 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1240 if (pci_resource_len(pdev, rc) > 0)
1241 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1242 (unsigned long long)pci_resource_start(pdev, rc),
1243 (unsigned long long)pci_resource_len(pdev, rc));
1244
1245 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1246 pdev->subsystem_vendor, pdev->subsystem_device);
1247
1248 mutex_init(&ctrl->crit_sect);
1249 mutex_init(&ctrl->ctrl_lock);
1250 spin_lock_init(&ctrl->lock);
1251
1252 /* setup wait queue */
1253 init_waitqueue_head(&ctrl->queue);
1254
1255 /* return PCI Controller Info */
1256 ctrl->slot_device_offset = 0;
1257 ctrl->num_slots = 1;
1258 ctrl->first_slot = slot_cap >> 19;
1259 ctrl->ctrlcap = slot_cap & 0x0000007f;
1260
1261 /* Mask Hot-plug Interrupt Enable */
1262 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1263 if (rc) {
1264 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1265 goto abort_free_ctlr;
1266 }
1267
1268 dbg("%s: SLOTCTRL %x value read %x\n",
1269 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1270 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1271
1272 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1273 if (rc) {
1274 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1275 goto abort_free_ctlr;
1276 }
1277
1278 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1279 if (rc) {
1280 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1281 goto abort_free_ctlr;
1282 }
1283
1284 temp_word = 0x1F; /* Clear all events */
1285 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1286 if (rc) {
1287 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1288 goto abort_free_ctlr;
1289 }
1290
1291 if (pciehp_poll_mode) {
1292 /* Install interrupt polling timer. Start with 10 sec delay */
1293 init_timer(&ctrl->poll_timer);
1294 start_int_poll_timer(ctrl, 10);
1295 } else {
1296 /* Installs the interrupt handler */
1297 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1298 MY_NAME, (void *)ctrl);
1299 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1300 __FUNCTION__, ctrl->pci_dev->irq,
1301 atomic_read(&pciehp_num_controllers), rc);
1302 if (rc) {
1303 err("Can't get irq %d for the hotplug controller\n",
1304 ctrl->pci_dev->irq);
1305 goto abort_free_ctlr;
1306 }
1307 }
1308 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1309 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1310
1311 /*
1312 * If this is the first controller to be initialized,
1313 * initialize the pciehp work queue
1314 */
1315 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1316 pciehp_wq = create_singlethread_workqueue("pciehpd");
1317 if (!pciehp_wq) {
1318 rc = -ENOMEM;
1319 goto abort_free_irq;
1320 }
1321 }
1322
1323 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1324 if (rc) {
1325 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1326 goto abort_free_irq;
1327 }
1328
1329 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1330
1331 if (ATTN_BUTTN(slot_cap))
1332 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1333
1334 if (POWER_CTRL(slot_cap))
1335 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1336
1337 if (MRL_SENS(slot_cap))
1338 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1339
1340 temp_word = (temp_word & ~intr_enable) | intr_enable;
1341
1342 if (pciehp_poll_mode) {
1343 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1344 } else {
1345 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1346 }
1347
1348 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1349 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1350 if (rc) {
1351 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1352 goto abort_free_irq;
1353 }
1354 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1355 if (rc) {
1356 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1357 goto abort_disable_intr;
1358 }
1359
1360 temp_word = 0x1F; /* Clear all events */
1361 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1362 if (rc) {
1363 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1364 goto abort_disable_intr;
1365 }
1366
1367 if (pciehp_force) {
1368 dbg("Bypassing BIOS check for pciehp use on %s\n",
1369 pci_name(ctrl->pci_dev));
1370 } else {
1371 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1372 if (rc)
1373 goto abort_disable_intr;
1374 }
1375
1376 ctrl->hpc_ops = &pciehp_hpc_ops;
1377
1378 DBG_LEAVE_ROUTINE
1379 return 0;
1380
1381 /* We end up here for the many possible ways to fail this API. */
1382 abort_disable_intr:
1383 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1384 if (!rc) {
1385 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1386 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1387 }
1388 if (rc)
1389 err("%s : disabling interrupts failed\n", __FUNCTION__);
1390
1391 abort_free_irq:
1392 if (pciehp_poll_mode)
1393 del_timer_sync(&ctrl->poll_timer);
1394 else
1395 free_irq(ctrl->pci_dev->irq, ctrl);
1396
1397 abort_free_ctlr:
1398 DBG_LEAVE_ROUTINE
1399 return -1;
1400 }
Linux kernel - Deliverables
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