drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39
  40 #include "../pci.h"
  41 #include "pciehp.h"
  42
  43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
  44
  45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  46 {
  47         struct pci_dev *dev = ctrl->pci_dev;
  48         return pci_read_config_word(dev, ctrl->cap_base + reg, value);
  49 }
  50
  51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  52 {
  53         struct pci_dev *dev = ctrl->pci_dev;
  54         return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
  55 }
  56
  57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  58 {
  59         struct pci_dev *dev = ctrl->pci_dev;
  60         return pci_write_config_word(dev, ctrl->cap_base + reg, value);
  61 }
  62
  63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
  64 {
  65         struct pci_dev *dev = ctrl->pci_dev;
  66         return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
  67 }
  68
  69 /* Power Control Command */
  70 #define POWER_ON        0
  71 #define POWER_OFF       PCI_EXP_SLTCTL_PCC
  72
  73 static irqreturn_t pcie_isr(int irq, void *dev_id);
  74 static void start_int_poll_timer(struct controller *ctrl, int sec);
  75
  76 /* This is the interrupt polling timeout function. */
  77 static void int_poll_timeout(unsigned long data)
  78 {
  79         struct controller *ctrl = (struct controller *)data;
  80
  81         /* Poll for interrupt events.  regs == NULL => polling */
  82         pcie_isr(0, ctrl);
  83
  84         init_timer(&ctrl->poll_timer);
  85         if (!pciehp_poll_time)
  86                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  87
  88         start_int_poll_timer(ctrl, pciehp_poll_time);
  89 }
  90
  91 /* This function starts the interrupt polling timer. */
  92 static void start_int_poll_timer(struct controller *ctrl, int sec)
  93 {
  94         /* Clamp to sane value */
  95         if ((sec <= 0) || (sec > 60))
  96                 sec = 2;
  97
  98         ctrl->poll_timer.function = &int_poll_timeout;
  99         ctrl->poll_timer.data = (unsigned long)ctrl;
 100         ctrl->poll_timer.expires = jiffies + sec * HZ;
 101         add_timer(&ctrl->poll_timer);
 102 }
 103
 104 static inline int pciehp_request_irq(struct controller *ctrl)
 105 {
 106         int retval, irq = ctrl->pcie->irq;
 107
 108         /* Install interrupt polling timer. Start with 10 sec delay */
 109         if (pciehp_poll_mode) {
 110                 init_timer(&ctrl->poll_timer);
 111                 start_int_poll_timer(ctrl, 10);
 112                 return 0;
 113         }
 114
 115         /* Installs the interrupt handler */
 116         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 117         if (retval)
 118                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
 119                          irq);
 120         return retval;
 121 }
 122
 123 static inline void pciehp_free_irq(struct controller *ctrl)
 124 {
 125         if (pciehp_poll_mode)
 126                 del_timer_sync(&ctrl->poll_timer);
 127         else
 128                 free_irq(ctrl->pcie->irq, ctrl);
 129 }
 130
 131 static int pcie_poll_cmd(struct controller *ctrl)
 132 {
 133         u16 slot_status;
 134         int err, timeout = 1000;
 135
 136         err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 137         if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 138                 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 139                 return 1;
 140         }
 141         while (timeout > 0) {
 142                 msleep(10);
 143                 timeout -= 10;
 144                 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 145                 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 146                         pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 147                         return 1;
 148                 }
 149         }
 150         return 0;       /* timeout */
 151 }
 152
 153 static void pcie_wait_cmd(struct controller *ctrl, int poll)
 154 {
 155         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 156         unsigned long timeout = msecs_to_jiffies(msecs);
 157         int rc;
 158
 159         if (poll)
 160                 rc = pcie_poll_cmd(ctrl);
 161         else
 162                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 163         if (!rc)
 164                 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
 165 }
 166
 167 /**
 168  * pcie_write_cmd - Issue controller command
 169  * @ctrl: controller to which the command is issued
 170  * @cmd:  command value written to slot control register
 171  * @mask: bitmask of slot control register to be modified
 172  */
 173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 174 {
 175         int retval = 0;
 176         u16 slot_status;
 177         u16 slot_ctrl;
 178
 179         mutex_lock(&ctrl->ctrl_lock);
 180
 181         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 182         if (retval) {
 183                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 184                          __func__);
 185                 goto out;
 186         }
 187
 188         if (slot_status & PCI_EXP_SLTSTA_CC) {
 189                 if (!ctrl->no_cmd_complete) {
 190                         /*
 191                          * After 1 sec and CMD_COMPLETED still not set, just
 192                          * proceed forward to issue the next command according
 193                          * to spec. Just print out the error message.
 194                          */
 195                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 196                 } else if (!NO_CMD_CMPL(ctrl)) {
 197                         /*
 198                          * This controller semms to notify of command completed
 199                          * event even though it supports none of power
 200                          * controller, attention led, power led and EMI.
 201                          */
 202                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
 203                                  "wait for command completed event.\n");
 204                         ctrl->no_cmd_complete = 0;
 205                 } else {
 206                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
 207                                  "the controller is broken.\n");
 208                 }
 209         }
 210
 211         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 212         if (retval) {
 213                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 214                 goto out;
 215         }
 216
 217         slot_ctrl &= ~mask;
 218         slot_ctrl |= (cmd & mask);
 219         ctrl->cmd_busy = 1;
 220         smp_mb();
 221         retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
 222         if (retval)
 223                 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
 224
 225         /*
 226          * Wait for command completion.
 227          */
 228         if (!retval && !ctrl->no_cmd_complete) {
 229                 int poll = 0;
 230                 /*
 231                  * if hotplug interrupt is not enabled or command
 232                  * completed interrupt is not enabled, we need to poll
 233                  * command completed event.
 234                  */
 235                 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
 236                     !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
 237                         poll = 1;
 238                 pcie_wait_cmd(ctrl, poll);
 239         }
 240  out:
 241         mutex_unlock(&ctrl->ctrl_lock);
 242         return retval;
 243 }
 244
 245 static inline int check_link_active(struct controller *ctrl)
 246 {
 247         u16 link_status;
 248
 249         if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
 250                 return 0;
 251         return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
 252 }
 253
 254 static void pcie_wait_link_active(struct controller *ctrl)
 255 {
 256         int timeout = 1000;
 257
 258         if (check_link_active(ctrl))
 259                 return;
 260         while (timeout > 0) {
 261                 msleep(10);
 262                 timeout -= 10;
 263                 if (check_link_active(ctrl))
 264                         return;
 265         }
 266         ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
 267 }
 268
 269 static int hpc_check_lnk_status(struct controller *ctrl)
 270 {
 271         u16 lnk_status;
 272         int retval = 0;
 273
 274         /*
 275          * Data Link Layer Link Active Reporting must be capable for
 276          * hot-plug capable downstream port. But old controller might
 277          * not implement it. In this case, we wait for 1000 ms.
 278          */
 279         if (ctrl->link_active_reporting){
 280                 /* Wait for Data Link Layer Link Active bit to be set */
 281                 pcie_wait_link_active(ctrl);
 282                 /*
 283                  * We must wait for 100 ms after the Data Link Layer
 284                  * Link Active bit reads 1b before initiating a
 285                  * configuration access to the hot added device.
 286                  */
 287                 msleep(100);
 288         } else
 289                 msleep(1000);
 290
 291         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 292         if (retval) {
 293                 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
 294                 return retval;
 295         }
 296
 297         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 298         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 299             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 300                 ctrl_err(ctrl, "Link Training Error occurs \n");
 301                 retval = -1;
 302                 return retval;
 303         }
 304
 305         return retval;
 306 }
 307
 308 static int hpc_get_attention_status(struct slot *slot, u8 *status)
 309 {
 310         struct controller *ctrl = slot->ctrl;
 311         u16 slot_ctrl;
 312         u8 atten_led_state;
 313         int retval = 0;
 314
 315         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 316         if (retval) {
 317                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 318                 return retval;
 319         }
 320
 321         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
 322                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
 323
 324         atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
 325
 326         switch (atten_led_state) {
 327         case 0:
 328                 *status = 0xFF; /* Reserved */
 329                 break;
 330         case 1:
 331                 *status = 1;    /* On */
 332                 break;
 333         case 2:
 334                 *status = 2;    /* Blink */
 335                 break;
 336         case 3:
 337                 *status = 0;    /* Off */
 338                 break;
 339         default:
 340                 *status = 0xFF;
 341                 break;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static int hpc_get_power_status(struct slot *slot, u8 *status)
 348 {
 349         struct controller *ctrl = slot->ctrl;
 350         u16 slot_ctrl;
 351         u8 pwr_state;
 352         int     retval = 0;
 353
 354         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 355         if (retval) {
 356                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 357                 return retval;
 358         }
 359         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
 360                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
 361
 362         pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
 363
 364         switch (pwr_state) {
 365         case 0:
 366                 *status = 1;
 367                 break;
 368         case 1:
 369                 *status = 0;
 370                 break;
 371         default:
 372                 *status = 0xFF;
 373                 break;
 374         }
 375
 376         return retval;
 377 }
 378
 379 static int hpc_get_latch_status(struct slot *slot, u8 *status)
 380 {
 381         struct controller *ctrl = slot->ctrl;
 382         u16 slot_status;
 383         int retval;
 384
 385         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 386         if (retval) {
 387                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 388                          __func__);
 389                 return retval;
 390         }
 391         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 392         return 0;
 393 }
 394
 395 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
 396 {
 397         struct controller *ctrl = slot->ctrl;
 398         u16 slot_status;
 399         int retval;
 400
 401         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 402         if (retval) {
 403                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 404                          __func__);
 405                 return retval;
 406         }
 407         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 408         return 0;
 409 }
 410
 411 static int hpc_query_power_fault(struct slot *slot)
 412 {
 413         struct controller *ctrl = slot->ctrl;
 414         u16 slot_status;
 415         int retval;
 416
 417         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 418         if (retval) {
 419                 ctrl_err(ctrl, "Cannot check for power fault\n");
 420                 return retval;
 421         }
 422         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 423 }
 424
 425 static int hpc_get_emi_status(struct slot *slot, u8 *status)
 426 {
 427         struct controller *ctrl = slot->ctrl;
 428         u16 slot_status;
 429         int retval;
 430
 431         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 432         if (retval) {
 433                 ctrl_err(ctrl, "Cannot check EMI status\n");
 434                 return retval;
 435         }
 436         *status = !!(slot_status & PCI_EXP_SLTSTA_EIS);
 437         return retval;
 438 }
 439
 440 static int hpc_toggle_emi(struct slot *slot)
 441 {
 442         u16 slot_cmd;
 443         u16 cmd_mask;
 444         int rc;
 445
 446         slot_cmd = PCI_EXP_SLTCTL_EIC;
 447         cmd_mask = PCI_EXP_SLTCTL_EIC;
 448         rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
 449         slot->last_emi_toggle = get_seconds();
 450
 451         return rc;
 452 }
 453
 454 static int hpc_set_attention_status(struct slot *slot, u8 value)
 455 {
 456         struct controller *ctrl = slot->ctrl;
 457         u16 slot_cmd;
 458         u16 cmd_mask;
 459         int rc;
 460
 461         cmd_mask = PCI_EXP_SLTCTL_AIC;
 462         switch (value) {
 463                 case 0 :        /* turn off */
 464                         slot_cmd = 0x00C0;
 465                         break;
 466                 case 1:         /* turn on */
 467                         slot_cmd = 0x0040;
 468                         break;
 469                 case 2:         /* turn blink */
 470                         slot_cmd = 0x0080;
 471                         break;
 472                 default:
 473                         return -1;
 474         }
 475         rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 476         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 477                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
 478
 479         return rc;
 480 }
 481
 482 static void hpc_set_green_led_on(struct slot *slot)
 483 {
 484         struct controller *ctrl = slot->ctrl;
 485         u16 slot_cmd;
 486         u16 cmd_mask;
 487
 488         slot_cmd = 0x0100;
 489         cmd_mask = PCI_EXP_SLTCTL_PIC;
 490         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 491         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 492                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
 493 }
 494
 495 static void hpc_set_green_led_off(struct slot *slot)
 496 {
 497         struct controller *ctrl = slot->ctrl;
 498         u16 slot_cmd;
 499         u16 cmd_mask;
 500
 501         slot_cmd = 0x0300;
 502         cmd_mask = PCI_EXP_SLTCTL_PIC;
 503         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 504         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 505                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
 506 }
 507
 508 static void hpc_set_green_led_blink(struct slot *slot)
 509 {
 510         struct controller *ctrl = slot->ctrl;
 511         u16 slot_cmd;
 512         u16 cmd_mask;
 513
 514         slot_cmd = 0x0200;
 515         cmd_mask = PCI_EXP_SLTCTL_PIC;
 516         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 517         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 518                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
 519 }
 520
 521 static int hpc_power_on_slot(struct slot * slot)
 522 {
 523         struct controller *ctrl = slot->ctrl;
 524         u16 slot_cmd;
 525         u16 cmd_mask;
 526         u16 slot_status;
 527         int retval = 0;
 528
 529         ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 530
 531         /* Clear sticky power-fault bit from previous power failures */
 532         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 533         if (retval) {
 534                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 535                          __func__);
 536                 return retval;
 537         }
 538         slot_status &= PCI_EXP_SLTSTA_PFD;
 539         if (slot_status) {
 540                 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
 541                 if (retval) {
 542                         ctrl_err(ctrl,
 543                                  "%s: Cannot write to SLOTSTATUS register\n",
 544                                  __func__);
 545                         return retval;
 546                 }
 547         }
 548
 549         slot_cmd = POWER_ON;
 550         cmd_mask = PCI_EXP_SLTCTL_PCC;
 551         /* Enable detection that we turned off at slot power-off time */
 552         if (!pciehp_poll_mode) {
 553                 slot_cmd |= (PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE |
 554                              PCI_EXP_SLTCTL_PDCE);
 555                 cmd_mask |= (PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE |
 556                              PCI_EXP_SLTCTL_PDCE);
 557         }
 558
 559         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 560
 561         if (retval) {
 562                 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
 563                 return -1;
 564         }
 565         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 566                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
 567
 568         return retval;
 569 }
 570
 571 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
 572 {
 573         struct pci_dev *dev = ctrl->pci_dev;
 574         int pos;
 575         u32 reg;
 576
 577         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 578         if (!pos)
 579                 return 0;
 580         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 581         if (reg & PCI_ERR_COR_BAD_DLLP)
 582                 return 0;
 583         reg |= PCI_ERR_COR_BAD_DLLP;
 584         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 585         return 1;
 586 }
 587
 588 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
 589 {
 590         struct pci_dev *dev = ctrl->pci_dev;
 591         u32 reg;
 592         int pos;
 593
 594         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 595         if (!pos)
 596                 return;
 597         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 598         if (!(reg & PCI_ERR_COR_BAD_DLLP))
 599                 return;
 600         reg &= ~PCI_ERR_COR_BAD_DLLP;
 601         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 602 }
 603
 604 static int hpc_power_off_slot(struct slot * slot)
 605 {
 606         struct controller *ctrl = slot->ctrl;
 607         u16 slot_cmd;
 608         u16 cmd_mask;
 609         int retval = 0;
 610         int changed;
 611
 612         ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 613
 614         /*
 615          * Set Bad DLLP Mask bit in Correctable Error Mask
 616          * Register. This is the workaround against Bad DLLP error
 617          * that sometimes happens during turning power off the slot
 618          * which conforms to PCI Express 1.0a spec.
 619          */
 620         changed = pcie_mask_bad_dllp(ctrl);
 621
 622         slot_cmd = POWER_OFF;
 623         cmd_mask = PCI_EXP_SLTCTL_PCC;
 624         /*
 625          * If we get MRL or presence detect interrupts now, the isr
 626          * will notice the sticky power-fault bit too and issue power
 627          * indicator change commands. This will lead to an endless loop
 628          * of command completions, since the power-fault bit remains on
 629          * till the slot is powered on again.
 630          */
 631         if (!pciehp_poll_mode) {
 632                 slot_cmd &= ~(PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE |
 633                               PCI_EXP_SLTCTL_PDCE);
 634                 cmd_mask |= (PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE |
 635                              PCI_EXP_SLTCTL_PDCE);
 636         }
 637
 638         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 639         if (retval) {
 640                 ctrl_err(ctrl, "Write command failed!\n");
 641                 retval = -1;
 642                 goto out;
 643         }
 644         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 645                  __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
 646  out:
 647         if (changed)
 648                 pcie_unmask_bad_dllp(ctrl);
 649
 650         return retval;
 651 }
 652
 653 static irqreturn_t pcie_isr(int irq, void *dev_id)
 654 {
 655         struct controller *ctrl = (struct controller *)dev_id;
 656         u16 detected, intr_loc;
 657         struct slot *p_slot;
 658
 659         /*
 660          * In order to guarantee that all interrupt events are
 661          * serviced, we need to re-inspect Slot Status register after
 662          * clearing what is presumed to be the last pending interrupt.
 663          */
 664         intr_loc = 0;
 665         do {
 666                 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
 667                         ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
 668                                  __func__);
 669                         return IRQ_NONE;
 670                 }
 671
 672                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 673                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 674                              PCI_EXP_SLTSTA_CC);
 675                 intr_loc |= detected;
 676                 if (!intr_loc)
 677                         return IRQ_NONE;
 678                 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, detected)) {
 679                         ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
 680                                  __func__);
 681                         return IRQ_NONE;
 682                 }
 683         } while (detected);
 684
 685         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 686
 687         /* Check Command Complete Interrupt Pending */
 688         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 689                 ctrl->cmd_busy = 0;
 690                 smp_mb();
 691                 wake_up(&ctrl->queue);
 692         }
 693
 694         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 695                 return IRQ_HANDLED;
 696
 697         p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
 698
 699         /* Check MRL Sensor Changed */
 700         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 701                 pciehp_handle_switch_change(p_slot);
 702
 703         /* Check Attention Button Pressed */
 704         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 705                 pciehp_handle_attention_button(p_slot);
 706
 707         /* Check Presence Detect Changed */
 708         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 709                 pciehp_handle_presence_change(p_slot);
 710
 711         /* Check Power Fault Detected */
 712         if (intr_loc & PCI_EXP_SLTSTA_PFD)
 713                 pciehp_handle_power_fault(p_slot);
 714
 715         return IRQ_HANDLED;
 716 }
 717
 718 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 719 {
 720         struct controller *ctrl = slot->ctrl;
 721         enum pcie_link_speed lnk_speed;
 722         u32     lnk_cap;
 723         int retval = 0;
 724
 725         retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
 726         if (retval) {
 727                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 728                 return retval;
 729         }
 730
 731         switch (lnk_cap & 0x000F) {
 732         case 1:
 733                 lnk_speed = PCIE_2PT5GB;
 734                 break;
 735         default:
 736                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 737                 break;
 738         }
 739
 740         *value = lnk_speed;
 741         ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
 742
 743         return retval;
 744 }
 745
 746 static int hpc_get_max_lnk_width(struct slot *slot,
 747                                  enum pcie_link_width *value)
 748 {
 749         struct controller *ctrl = slot->ctrl;
 750         enum pcie_link_width lnk_wdth;
 751         u32     lnk_cap;
 752         int retval = 0;
 753
 754         retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
 755         if (retval) {
 756                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 757                 return retval;
 758         }
 759
 760         switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
 761         case 0:
 762                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 763                 break;
 764         case 1:
 765                 lnk_wdth = PCIE_LNK_X1;
 766                 break;
 767         case 2:
 768                 lnk_wdth = PCIE_LNK_X2;
 769                 break;
 770         case 4:
 771                 lnk_wdth = PCIE_LNK_X4;
 772                 break;
 773         case 8:
 774                 lnk_wdth = PCIE_LNK_X8;
 775                 break;
 776         case 12:
 777                 lnk_wdth = PCIE_LNK_X12;
 778                 break;
 779         case 16:
 780                 lnk_wdth = PCIE_LNK_X16;
 781                 break;
 782         case 32:
 783                 lnk_wdth = PCIE_LNK_X32;
 784                 break;
 785         default:
 786                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 787                 break;
 788         }
 789
 790         *value = lnk_wdth;
 791         ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
 792
 793         return retval;
 794 }
 795
 796 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 797 {
 798         struct controller *ctrl = slot->ctrl;
 799         enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
 800         int retval = 0;
 801         u16 lnk_status;
 802
 803         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 804         if (retval) {
 805                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 806                          __func__);
 807                 return retval;
 808         }
 809
 810         switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
 811         case 1:
 812                 lnk_speed = PCIE_2PT5GB;
 813                 break;
 814         default:
 815                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 816                 break;
 817         }
 818
 819         *value = lnk_speed;
 820         ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
 821
 822         return retval;
 823 }
 824
 825 static int hpc_get_cur_lnk_width(struct slot *slot,
 826                                  enum pcie_link_width *value)
 827 {
 828         struct controller *ctrl = slot->ctrl;
 829         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 830         int retval = 0;
 831         u16 lnk_status;
 832
 833         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 834         if (retval) {
 835                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 836                          __func__);
 837                 return retval;
 838         }
 839
 840         switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
 841         case 0:
 842                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 843                 break;
 844         case 1:
 845                 lnk_wdth = PCIE_LNK_X1;
 846                 break;
 847         case 2:
 848                 lnk_wdth = PCIE_LNK_X2;
 849                 break;
 850         case 4:
 851                 lnk_wdth = PCIE_LNK_X4;
 852                 break;
 853         case 8:
 854                 lnk_wdth = PCIE_LNK_X8;
 855                 break;
 856         case 12:
 857                 lnk_wdth = PCIE_LNK_X12;
 858                 break;
 859         case 16:
 860                 lnk_wdth = PCIE_LNK_X16;
 861                 break;
 862         case 32:
 863                 lnk_wdth = PCIE_LNK_X32;
 864                 break;
 865         default:
 866                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 867                 break;
 868         }
 869
 870         *value = lnk_wdth;
 871         ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
 872
 873         return retval;
 874 }
 875
 876 static void pcie_release_ctrl(struct controller *ctrl);
 877 static struct hpc_ops pciehp_hpc_ops = {
 878         .power_on_slot                  = hpc_power_on_slot,
 879         .power_off_slot                 = hpc_power_off_slot,
 880         .set_attention_status           = hpc_set_attention_status,
 881         .get_power_status               = hpc_get_power_status,
 882         .get_attention_status           = hpc_get_attention_status,
 883         .get_latch_status               = hpc_get_latch_status,
 884         .get_adapter_status             = hpc_get_adapter_status,
 885         .get_emi_status                 = hpc_get_emi_status,
 886         .toggle_emi                     = hpc_toggle_emi,
 887
 888         .get_max_bus_speed              = hpc_get_max_lnk_speed,
 889         .get_cur_bus_speed              = hpc_get_cur_lnk_speed,
 890         .get_max_lnk_width              = hpc_get_max_lnk_width,
 891         .get_cur_lnk_width              = hpc_get_cur_lnk_width,
 892
 893         .query_power_fault              = hpc_query_power_fault,
 894         .green_led_on                   = hpc_set_green_led_on,
 895         .green_led_off                  = hpc_set_green_led_off,
 896         .green_led_blink                = hpc_set_green_led_blink,
 897
 898         .release_ctlr                   = pcie_release_ctrl,
 899         .check_lnk_status               = hpc_check_lnk_status,
 900 };
 901
 902 int pcie_enable_notification(struct controller *ctrl)
 903 {
 904         u16 cmd, mask;
 905
 906         cmd = PCI_EXP_SLTCTL_PDCE;
 907         if (ATTN_BUTTN(ctrl))
 908                 cmd |= PCI_EXP_SLTCTL_ABPE;
 909         if (POWER_CTRL(ctrl))
 910                 cmd |= PCI_EXP_SLTCTL_PFDE;
 911         if (MRL_SENS(ctrl))
 912                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 913         if (!pciehp_poll_mode)
 914                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 915
 916         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 917                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 918                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
 919
 920         if (pcie_write_cmd(ctrl, cmd, mask)) {
 921                 ctrl_err(ctrl, "Cannot enable software notification\n");
 922                 return -1;
 923         }
 924         return 0;
 925 }
 926
 927 static void pcie_disable_notification(struct controller *ctrl)
 928 {
 929         u16 mask;
 930         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 931                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 932                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
 933         if (pcie_write_cmd(ctrl, 0, mask))
 934                 ctrl_warn(ctrl, "Cannot disable software notification\n");
 935 }
 936
 937 static int pcie_init_notification(struct controller *ctrl)
 938 {
 939         if (pciehp_request_irq(ctrl))
 940                 return -1;
 941         if (pcie_enable_notification(ctrl)) {
 942                 pciehp_free_irq(ctrl);
 943                 return -1;
 944         }
 945         return 0;
 946 }
 947
 948 static void pcie_shutdown_notification(struct controller *ctrl)
 949 {
 950         pcie_disable_notification(ctrl);
 951         pciehp_free_irq(ctrl);
 952 }
 953
 954 static int pcie_init_slot(struct controller *ctrl)
 955 {
 956         struct slot *slot;
 957
 958         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 959         if (!slot)
 960                 return -ENOMEM;
 961
 962         slot->hp_slot = 0;
 963         slot->ctrl = ctrl;
 964         slot->bus = ctrl->pci_dev->subordinate->number;
 965         slot->device = ctrl->slot_device_offset + slot->hp_slot;
 966         slot->hpc_ops = ctrl->hpc_ops;
 967         slot->number = ctrl->first_slot;
 968         mutex_init(&slot->lock);
 969         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 970         list_add(&slot->slot_list, &ctrl->slot_list);
 971         return 0;
 972 }
 973
 974 static void pcie_cleanup_slot(struct controller *ctrl)
 975 {
 976         struct slot *slot;
 977         slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
 978         list_del(&slot->slot_list);
 979         cancel_delayed_work(&slot->work);
 980         flush_scheduled_work();
 981         flush_workqueue(pciehp_wq);
 982         kfree(slot);
 983 }
 984
 985 static inline void dbg_ctrl(struct controller *ctrl)
 986 {
 987         int i;
 988         u16 reg16;
 989         struct pci_dev *pdev = ctrl->pci_dev;
 990
 991         if (!pciehp_debug)
 992                 return;
 993
 994         ctrl_info(ctrl, "Hotplug Controller:\n");
 995         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 996                   pci_name(pdev), pdev->irq);
 997         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 998         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 999         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
1000                   pdev->subsystem_device);
1001         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
1002                   pdev->subsystem_vendor);
1003         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n", ctrl->cap_base);
1004         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1005                 if (!pci_resource_len(pdev, i))
1006                         continue;
1007                 ctrl_info(ctrl, "  PCI resource [%d]     : 0x%llx@0x%llx\n",
1008                           i, (unsigned long long)pci_resource_len(pdev, i),
1009                           (unsigned long long)pci_resource_start(pdev, i));
1010         }
1011         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
1012         ctrl_info(ctrl, "  Physical Slot Number : %d\n", ctrl->first_slot);
1013         ctrl_info(ctrl, "  Attention Button     : %3s\n",
1014                   ATTN_BUTTN(ctrl) ? "yes" : "no");
1015         ctrl_info(ctrl, "  Power Controller     : %3s\n",
1016                   POWER_CTRL(ctrl) ? "yes" : "no");
1017         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
1018                   MRL_SENS(ctrl)   ? "yes" : "no");
1019         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
1020                   ATTN_LED(ctrl)   ? "yes" : "no");
1021         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
1022                   PWR_LED(ctrl)    ? "yes" : "no");
1023         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
1024                   HP_SUPR_RM(ctrl) ? "yes" : "no");
1025         ctrl_info(ctrl, "  EMI Present          : %3s\n",
1026                   EMI(ctrl)        ? "yes" : "no");
1027         ctrl_info(ctrl, "  Command Completed    : %3s\n",
1028                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
1029         pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
1030         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
1031         pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
1032         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
1033 }
1034
1035 struct controller *pcie_init(struct pcie_device *dev)
1036 {
1037         struct controller *ctrl;
1038         u32 slot_cap, link_cap;
1039         struct pci_dev *pdev = dev->port;
1040
1041         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1042         if (!ctrl) {
1043                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
1044                 goto abort;
1045         }
1046         INIT_LIST_HEAD(&ctrl->slot_list);
1047
1048         ctrl->pcie = dev;
1049         ctrl->pci_dev = pdev;
1050         ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1051         if (!ctrl->cap_base) {
1052                 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
1053                 goto abort_ctrl;
1054         }
1055         if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
1056                 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
1057                 goto abort_ctrl;
1058         }
1059
1060         ctrl->slot_cap = slot_cap;
1061         ctrl->first_slot = slot_cap >> 19;
1062         ctrl->slot_device_offset = 0;
1063         ctrl->num_slots = 1;
1064         ctrl->hpc_ops = &pciehp_hpc_ops;
1065         mutex_init(&ctrl->crit_sect);
1066         mutex_init(&ctrl->ctrl_lock);
1067         init_waitqueue_head(&ctrl->queue);
1068         dbg_ctrl(ctrl);
1069         /*
1070          * Controller doesn't notify of command completion if the "No
1071          * Command Completed Support" bit is set in Slot Capability
1072          * register or the controller supports none of power
1073          * controller, attention led, power led and EMI.
1074          */
1075         if (NO_CMD_CMPL(ctrl) ||
1076             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1077             ctrl->no_cmd_complete = 1;
1078
1079         /* Check if Data Link Layer Link Active Reporting is implemented */
1080         if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
1081                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1082                 goto abort_ctrl;
1083         }
1084         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
1085                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1086                 ctrl->link_active_reporting = 1;
1087         }
1088
1089         /* Clear all remaining event bits in Slot Status register */
1090         if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
1091                 goto abort_ctrl;
1092
1093         /* Disable sotfware notification */
1094         pcie_disable_notification(ctrl);
1095
1096         /*
1097          * If this is the first controller to be initialized,
1098          * initialize the pciehp work queue
1099          */
1100         if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1101                 pciehp_wq = create_singlethread_workqueue("pciehpd");
1102                 if (!pciehp_wq)
1103                         goto abort_ctrl;
1104         }
1105
1106         ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1107                   pdev->vendor, pdev->device, pdev->subsystem_vendor,
1108                   pdev->subsystem_device);
1109
1110         if (pcie_init_slot(ctrl))
1111                 goto abort_ctrl;
1112
1113         if (pcie_init_notification(ctrl))
1114                 goto abort_slot;
1115
1116         return ctrl;
1117
1118 abort_slot:
1119         pcie_cleanup_slot(ctrl);
1120 abort_ctrl:
1121         kfree(ctrl);
1122 abort:
1123         return NULL;
1124 }
1125
1126 void pcie_release_ctrl(struct controller *ctrl)
1127 {
1128         pcie_shutdown_notification(ctrl);
1129         pcie_cleanup_slot(ctrl);
1130         /*
1131          * If this is the last controller to be released, destroy the
1132          * pciehp work queue
1133          */
1134         if (atomic_dec_and_test(&pciehp_num_controllers))
1135                 destroy_workqueue(pciehp_wq);
1136         kfree(ctrl);
1137 }