drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  45 {
  46         return ctrl->pcie->port;
  47 }
  48
  49 static irqreturn_t pcie_isr(int irq, void *dev_id);
  50 static void start_int_poll_timer(struct controller *ctrl, int sec);
  51
  52 /* This is the interrupt polling timeout function. */
  53 static void int_poll_timeout(unsigned long data)
  54 {
  55         struct controller *ctrl = (struct controller *)data;
  56
  57         /* Poll for interrupt events.  regs == NULL => polling */
  58         pcie_isr(0, ctrl);
  59
  60         init_timer(&ctrl->poll_timer);
  61         if (!pciehp_poll_time)
  62                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  63
  64         start_int_poll_timer(ctrl, pciehp_poll_time);
  65 }
  66
  67 /* This function starts the interrupt polling timer. */
  68 static void start_int_poll_timer(struct controller *ctrl, int sec)
  69 {
  70         /* Clamp to sane value */
  71         if ((sec <= 0) || (sec > 60))
  72                 sec = 2;
  73
  74         ctrl->poll_timer.function = &int_poll_timeout;
  75         ctrl->poll_timer.data = (unsigned long)ctrl;
  76         ctrl->poll_timer.expires = jiffies + sec * HZ;
  77         add_timer(&ctrl->poll_timer);
  78 }
  79
  80 static inline int pciehp_request_irq(struct controller *ctrl)
  81 {
  82         int retval, irq = ctrl->pcie->irq;
  83
  84         /* Install interrupt polling timer. Start with 10 sec delay */
  85         if (pciehp_poll_mode) {
  86                 init_timer(&ctrl->poll_timer);
  87                 start_int_poll_timer(ctrl, 10);
  88                 return 0;
  89         }
  90
  91         /* Installs the interrupt handler */
  92         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
  93         if (retval)
  94                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  95                          irq);
  96         return retval;
  97 }
  98
  99 static inline void pciehp_free_irq(struct controller *ctrl)
 100 {
 101         if (pciehp_poll_mode)
 102                 del_timer_sync(&ctrl->poll_timer);
 103         else
 104                 free_irq(ctrl->pcie->irq, ctrl);
 105 }
 106
 107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
 108 {
 109         struct pci_dev *pdev = ctrl_dev(ctrl);
 110         u16 slot_status;
 111
 112         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 113         if (slot_status & PCI_EXP_SLTSTA_CC) {
 114                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 115                                            PCI_EXP_SLTSTA_CC);
 116                 return 1;
 117         }
 118         while (timeout > 0) {
 119                 msleep(10);
 120                 timeout -= 10;
 121                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 122                 if (slot_status & PCI_EXP_SLTSTA_CC) {
 123                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 124                                                    PCI_EXP_SLTSTA_CC);
 125                         return 1;
 126                 }
 127         }
 128         return 0;       /* timeout */
 129 }
 130
 131 static void pcie_wait_cmd(struct controller *ctrl)
 132 {
 133         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 134         unsigned long duration = msecs_to_jiffies(msecs);
 135         unsigned long cmd_timeout = ctrl->cmd_started + duration;
 136         unsigned long now, timeout;
 137         int rc;
 138
 139         /*
 140          * If the controller does not generate notifications for command
 141          * completions, we never need to wait between writes.
 142          */
 143         if (ctrl->no_cmd_complete)
 144                 return;
 145
 146         if (!ctrl->cmd_busy)
 147                 return;
 148
 149         /*
 150          * Even if the command has already timed out, we want to call
 151          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 152          */
 153         now = jiffies;
 154         if (time_before_eq(cmd_timeout, now))
 155                 timeout = 1;
 156         else
 157                 timeout = cmd_timeout - now;
 158
 159         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 160             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 161                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 162         else
 163                 rc = pcie_poll_cmd(ctrl, timeout);
 164
 165         /*
 166          * Controllers with errata like Intel CF118 don't generate
 167          * completion notifications unless the power/indicator/interlock
 168          * control bits are changed.  On such controllers, we'll emit this
 169          * timeout message when we wait for completion of commands that
 170          * don't change those bits, e.g., commands that merely enable
 171          * interrupts.
 172          */
 173         if (!rc)
 174                 ctrl_info(ctrl, "Timeout on hotplug command %#010x (issued %u msec ago)\n",
 175                           ctrl->slot_ctrl,
 176                           jiffies_to_msecs(now - ctrl->cmd_started));
 177 }
 178
 179 /**
 180  * pcie_write_cmd - Issue controller command
 181  * @ctrl: controller to which the command is issued
 182  * @cmd:  command value written to slot control register
 183  * @mask: bitmask of slot control register to be modified
 184  */
 185 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 186 {
 187         struct pci_dev *pdev = ctrl_dev(ctrl);
 188         u16 slot_status;
 189         u16 slot_ctrl;
 190
 191         mutex_lock(&ctrl->ctrl_lock);
 192
 193         /* Wait for any previous command that might still be in progress */
 194         pcie_wait_cmd(ctrl);
 195
 196         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 197         if (slot_status & PCI_EXP_SLTSTA_CC) {
 198                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 199                                            PCI_EXP_SLTSTA_CC);
 200                 if (!ctrl->no_cmd_complete) {
 201                         /*
 202                          * After 1 sec and CMD_COMPLETED still not set, just
 203                          * proceed forward to issue the next command according
 204                          * to spec. Just print out the error message.
 205                          */
 206                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 207                 } else if (!NO_CMD_CMPL(ctrl)) {
 208                         /*
 209                          * This controller seems to notify of command completed
 210                          * event even though it supports none of power
 211                          * controller, attention led, power led and EMI.
 212                          */
 213                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to wait for command completed event\n");
 214                         ctrl->no_cmd_complete = 0;
 215                 } else {
 216                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe the controller is broken\n");
 217                 }
 218         }
 219
 220         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 221         slot_ctrl &= ~mask;
 222         slot_ctrl |= (cmd & mask);
 223         ctrl->cmd_busy = 1;
 224         smp_mb();
 225         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 226         ctrl->cmd_started = jiffies;
 227         ctrl->slot_ctrl = slot_ctrl;
 228
 229         mutex_unlock(&ctrl->ctrl_lock);
 230 }
 231
 232 bool pciehp_check_link_active(struct controller *ctrl)
 233 {
 234         struct pci_dev *pdev = ctrl_dev(ctrl);
 235         u16 lnk_status;
 236         bool ret;
 237
 238         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 239         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 240
 241         if (ret)
 242                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 243
 244         return ret;
 245 }
 246
 247 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
 248 {
 249         int timeout = 1000;
 250
 251         if (pciehp_check_link_active(ctrl) == active)
 252                 return;
 253         while (timeout > 0) {
 254                 msleep(10);
 255                 timeout -= 10;
 256                 if (pciehp_check_link_active(ctrl) == active)
 257                         return;
 258         }
 259         ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
 260                         active ? "set" : "cleared");
 261 }
 262
 263 static void pcie_wait_link_active(struct controller *ctrl)
 264 {
 265         __pcie_wait_link_active(ctrl, true);
 266 }
 267
 268 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 269 {
 270         u32 l;
 271         int count = 0;
 272         int delay = 1000, step = 20;
 273         bool found = false;
 274
 275         do {
 276                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 277                 count++;
 278
 279                 if (found)
 280                         break;
 281
 282                 msleep(step);
 283                 delay -= step;
 284         } while (delay > 0);
 285
 286         if (count > 1 && pciehp_debug)
 287                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 288                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 289                         PCI_FUNC(devfn), count, step, l);
 290
 291         return found;
 292 }
 293
 294 int pciehp_check_link_status(struct controller *ctrl)
 295 {
 296         struct pci_dev *pdev = ctrl_dev(ctrl);
 297         bool found;
 298         u16 lnk_status;
 299
 300         /*
 301          * Data Link Layer Link Active Reporting must be capable for
 302          * hot-plug capable downstream port. But old controller might
 303          * not implement it. In this case, we wait for 1000 ms.
 304         */
 305         if (ctrl->link_active_reporting)
 306                 pcie_wait_link_active(ctrl);
 307         else
 308                 msleep(1000);
 309
 310         /* wait 100ms before read pci conf, and try in 1s */
 311         msleep(100);
 312         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 313                                         PCI_DEVFN(0, 0));
 314
 315         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 316         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 317         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 318             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 319                 ctrl_err(ctrl, "Link Training Error occurs\n");
 320                 return -1;
 321         }
 322
 323         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 324
 325         if (!found)
 326                 return -1;
 327
 328         return 0;
 329 }
 330
 331 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 332 {
 333         struct pci_dev *pdev = ctrl_dev(ctrl);
 334         u16 lnk_ctrl;
 335
 336         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 337
 338         if (enable)
 339                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 340         else
 341                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 342
 343         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 344         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 345         return 0;
 346 }
 347
 348 static int pciehp_link_enable(struct controller *ctrl)
 349 {
 350         return __pciehp_link_set(ctrl, true);
 351 }
 352
 353 void pciehp_get_attention_status(struct slot *slot, u8 *status)
 354 {
 355         struct controller *ctrl = slot->ctrl;
 356         struct pci_dev *pdev = ctrl_dev(ctrl);
 357         u16 slot_ctrl;
 358
 359         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 360         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 361                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 362
 363         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 364         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 365                 *status = 1;    /* On */
 366                 break;
 367         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 368                 *status = 2;    /* Blink */
 369                 break;
 370         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 371                 *status = 0;    /* Off */
 372                 break;
 373         default:
 374                 *status = 0xFF;
 375                 break;
 376         }
 377 }
 378
 379 void pciehp_get_power_status(struct slot *slot, u8 *status)
 380 {
 381         struct controller *ctrl = slot->ctrl;
 382         struct pci_dev *pdev = ctrl_dev(ctrl);
 383         u16 slot_ctrl;
 384
 385         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 386         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 387                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 388
 389         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 390         case PCI_EXP_SLTCTL_PWR_ON:
 391                 *status = 1;    /* On */
 392                 break;
 393         case PCI_EXP_SLTCTL_PWR_OFF:
 394                 *status = 0;    /* Off */
 395                 break;
 396         default:
 397                 *status = 0xFF;
 398                 break;
 399         }
 400 }
 401
 402 void pciehp_get_latch_status(struct slot *slot, u8 *status)
 403 {
 404         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 405         u16 slot_status;
 406
 407         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 408         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 409 }
 410
 411 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
 412 {
 413         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 414         u16 slot_status;
 415
 416         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 417         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 418 }
 419
 420 int pciehp_query_power_fault(struct slot *slot)
 421 {
 422         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 423         u16 slot_status;
 424
 425         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 426         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 427 }
 428
 429 void pciehp_set_attention_status(struct slot *slot, u8 value)
 430 {
 431         struct controller *ctrl = slot->ctrl;
 432         u16 slot_cmd;
 433
 434         if (!ATTN_LED(ctrl))
 435                 return;
 436
 437         switch (value) {
 438         case 0:         /* turn off */
 439                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 440                 break;
 441         case 1:         /* turn on */
 442                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 443                 break;
 444         case 2:         /* turn blink */
 445                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 446                 break;
 447         default:
 448                 return;
 449         }
 450         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 451                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 452         pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 453 }
 454
 455 void pciehp_green_led_on(struct slot *slot)
 456 {
 457         struct controller *ctrl = slot->ctrl;
 458
 459         if (!PWR_LED(ctrl))
 460                 return;
 461
 462         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
 463         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 464                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 465                  PCI_EXP_SLTCTL_PWR_IND_ON);
 466 }
 467
 468 void pciehp_green_led_off(struct slot *slot)
 469 {
 470         struct controller *ctrl = slot->ctrl;
 471
 472         if (!PWR_LED(ctrl))
 473                 return;
 474
 475         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
 476         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 477                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 478                  PCI_EXP_SLTCTL_PWR_IND_OFF);
 479 }
 480
 481 void pciehp_green_led_blink(struct slot *slot)
 482 {
 483         struct controller *ctrl = slot->ctrl;
 484
 485         if (!PWR_LED(ctrl))
 486                 return;
 487
 488         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
 489         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 490                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 491                  PCI_EXP_SLTCTL_PWR_IND_BLINK);
 492 }
 493
 494 int pciehp_power_on_slot(struct slot *slot)
 495 {
 496         struct controller *ctrl = slot->ctrl;
 497         struct pci_dev *pdev = ctrl_dev(ctrl);
 498         u16 slot_status;
 499         int retval;
 500
 501         /* Clear sticky power-fault bit from previous power failures */
 502         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 503         if (slot_status & PCI_EXP_SLTSTA_PFD)
 504                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 505                                            PCI_EXP_SLTSTA_PFD);
 506         ctrl->power_fault_detected = 0;
 507
 508         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 509         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 510                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 511                  PCI_EXP_SLTCTL_PWR_ON);
 512
 513         retval = pciehp_link_enable(ctrl);
 514         if (retval)
 515                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 516
 517         return retval;
 518 }
 519
 520 void pciehp_power_off_slot(struct slot *slot)
 521 {
 522         struct controller *ctrl = slot->ctrl;
 523
 524         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 525         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 526                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 527                  PCI_EXP_SLTCTL_PWR_OFF);
 528 }
 529
 530 static irqreturn_t pcie_isr(int irq, void *dev_id)
 531 {
 532         struct controller *ctrl = (struct controller *)dev_id;
 533         struct pci_dev *pdev = ctrl_dev(ctrl);
 534         struct slot *slot = ctrl->slot;
 535         u16 detected, intr_loc;
 536
 537         /*
 538          * In order to guarantee that all interrupt events are
 539          * serviced, we need to re-inspect Slot Status register after
 540          * clearing what is presumed to be the last pending interrupt.
 541          */
 542         intr_loc = 0;
 543         do {
 544                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
 545
 546                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 547                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 548                              PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 549                 detected &= ~intr_loc;
 550                 intr_loc |= detected;
 551                 if (!intr_loc)
 552                         return IRQ_NONE;
 553                 if (detected)
 554                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 555                                                    intr_loc);
 556         } while (detected);
 557
 558         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 559
 560         /* Check Command Complete Interrupt Pending */
 561         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 562                 ctrl->cmd_busy = 0;
 563                 smp_mb();
 564                 wake_up(&ctrl->queue);
 565         }
 566
 567         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 568                 return IRQ_HANDLED;
 569
 570         /* Check MRL Sensor Changed */
 571         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 572                 pciehp_handle_switch_change(slot);
 573
 574         /* Check Attention Button Pressed */
 575         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 576                 pciehp_handle_attention_button(slot);
 577
 578         /* Check Presence Detect Changed */
 579         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 580                 pciehp_handle_presence_change(slot);
 581
 582         /* Check Power Fault Detected */
 583         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 584                 ctrl->power_fault_detected = 1;
 585                 pciehp_handle_power_fault(slot);
 586         }
 587
 588         if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
 589                 pciehp_handle_linkstate_change(slot);
 590
 591         return IRQ_HANDLED;
 592 }
 593
 594 void pcie_enable_notification(struct controller *ctrl)
 595 {
 596         u16 cmd, mask;
 597
 598         /*
 599          * TBD: Power fault detected software notification support.
 600          *
 601          * Power fault detected software notification is not enabled
 602          * now, because it caused power fault detected interrupt storm
 603          * on some machines. On those machines, power fault detected
 604          * bit in the slot status register was set again immediately
 605          * when it is cleared in the interrupt service routine, and
 606          * next power fault detected interrupt was notified again.
 607          */
 608
 609         /*
 610          * Always enable link events: thus link-up and link-down shall
 611          * always be treated as hotplug and unplug respectively. Enable
 612          * presence detect only if Attention Button is not present.
 613          */
 614         cmd = PCI_EXP_SLTCTL_DLLSCE;
 615         if (ATTN_BUTTN(ctrl))
 616                 cmd |= PCI_EXP_SLTCTL_ABPE;
 617         else
 618                 cmd |= PCI_EXP_SLTCTL_PDCE;
 619         if (MRL_SENS(ctrl))
 620                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 621         if (!pciehp_poll_mode)
 622                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 623
 624         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 625                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 626                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 627                 PCI_EXP_SLTCTL_DLLSCE);
 628
 629         pcie_write_cmd(ctrl, cmd, mask);
 630 }
 631
 632 static void pcie_disable_notification(struct controller *ctrl)
 633 {
 634         u16 mask;
 635
 636         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 637                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 638                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 639                 PCI_EXP_SLTCTL_DLLSCE);
 640         pcie_write_cmd(ctrl, 0, mask);
 641 }
 642
 643 /*
 644  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 645  * bus reset of the bridge, but at the same time we want to ensure that it is
 646  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 647  * disable link state notification and presence detection change notification
 648  * momentarily, if we see that they could interfere. Also, clear any spurious
 649  * events after.
 650  */
 651 int pciehp_reset_slot(struct slot *slot, int probe)
 652 {
 653         struct controller *ctrl = slot->ctrl;
 654         struct pci_dev *pdev = ctrl_dev(ctrl);
 655         u16 stat_mask = 0, ctrl_mask = 0;
 656
 657         if (probe)
 658                 return 0;
 659
 660         if (!ATTN_BUTTN(ctrl)) {
 661                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 662                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 663         }
 664         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 665         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 666
 667         pcie_write_cmd(ctrl, 0, ctrl_mask);
 668         if (pciehp_poll_mode)
 669                 del_timer_sync(&ctrl->poll_timer);
 670
 671         pci_reset_bridge_secondary_bus(ctrl->pcie->port);
 672
 673         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 674         pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
 675         if (pciehp_poll_mode)
 676                 int_poll_timeout(ctrl->poll_timer.data);
 677
 678         return 0;
 679 }
 680
 681 int pcie_init_notification(struct controller *ctrl)
 682 {
 683         if (pciehp_request_irq(ctrl))
 684                 return -1;
 685         pcie_enable_notification(ctrl);
 686         ctrl->notification_enabled = 1;
 687         return 0;
 688 }
 689
 690 static void pcie_shutdown_notification(struct controller *ctrl)
 691 {
 692         if (ctrl->notification_enabled) {
 693                 pcie_disable_notification(ctrl);
 694                 pciehp_free_irq(ctrl);
 695                 ctrl->notification_enabled = 0;
 696         }
 697 }
 698
 699 static int pcie_init_slot(struct controller *ctrl)
 700 {
 701         struct slot *slot;
 702
 703         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 704         if (!slot)
 705                 return -ENOMEM;
 706
 707         slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
 708         if (!slot->wq)
 709                 goto abort;
 710
 711         slot->ctrl = ctrl;
 712         mutex_init(&slot->lock);
 713         mutex_init(&slot->hotplug_lock);
 714         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 715         ctrl->slot = slot;
 716         return 0;
 717 abort:
 718         kfree(slot);
 719         return -ENOMEM;
 720 }
 721
 722 static void pcie_cleanup_slot(struct controller *ctrl)
 723 {
 724         struct slot *slot = ctrl->slot;
 725         cancel_delayed_work(&slot->work);
 726         destroy_workqueue(slot->wq);
 727         kfree(slot);
 728 }
 729
 730 static inline void dbg_ctrl(struct controller *ctrl)
 731 {
 732         int i;
 733         u16 reg16;
 734         struct pci_dev *pdev = ctrl->pcie->port;
 735
 736         if (!pciehp_debug)
 737                 return;
 738
 739         ctrl_info(ctrl, "Hotplug Controller:\n");
 740         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 741                   pci_name(pdev), pdev->irq);
 742         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 743         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 744         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
 745                   pdev->subsystem_device);
 746         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
 747                   pdev->subsystem_vendor);
 748         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
 749                   pci_pcie_cap(pdev));
 750         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 751                 if (!pci_resource_len(pdev, i))
 752                         continue;
 753                 ctrl_info(ctrl, "  PCI resource [%d]     : %pR\n",
 754                           i, &pdev->resource[i]);
 755         }
 756         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 757         ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
 758         ctrl_info(ctrl, "  Attention Button     : %3s\n",
 759                   ATTN_BUTTN(ctrl) ? "yes" : "no");
 760         ctrl_info(ctrl, "  Power Controller     : %3s\n",
 761                   POWER_CTRL(ctrl) ? "yes" : "no");
 762         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
 763                   MRL_SENS(ctrl)   ? "yes" : "no");
 764         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
 765                   ATTN_LED(ctrl)   ? "yes" : "no");
 766         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
 767                   PWR_LED(ctrl)    ? "yes" : "no");
 768         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
 769                   HP_SUPR_RM(ctrl) ? "yes" : "no");
 770         ctrl_info(ctrl, "  EMI Present          : %3s\n",
 771                   EMI(ctrl)        ? "yes" : "no");
 772         ctrl_info(ctrl, "  Command Completed    : %3s\n",
 773                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
 774         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 775         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 776         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 777         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 778 }
 779
 780 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 781
 782 struct controller *pcie_init(struct pcie_device *dev)
 783 {
 784         struct controller *ctrl;
 785         u32 slot_cap, link_cap;
 786         struct pci_dev *pdev = dev->port;
 787
 788         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 789         if (!ctrl) {
 790                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 791                 goto abort;
 792         }
 793         ctrl->pcie = dev;
 794         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 795         ctrl->slot_cap = slot_cap;
 796         mutex_init(&ctrl->ctrl_lock);
 797         init_waitqueue_head(&ctrl->queue);
 798         dbg_ctrl(ctrl);
 799         /*
 800          * Controller doesn't notify of command completion if the "No
 801          * Command Completed Support" bit is set in Slot Capability
 802          * register or the controller supports none of power
 803          * controller, attention led, power led and EMI.
 804          */
 805         if (NO_CMD_CMPL(ctrl) ||
 806             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
 807                 ctrl->no_cmd_complete = 1;
 808
 809         /* Check if Data Link Layer Link Active Reporting is implemented */
 810         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 811         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
 812                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
 813                 ctrl->link_active_reporting = 1;
 814         }
 815
 816         /* Clear all remaining event bits in Slot Status register */
 817         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 818                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 819                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 820                 PCI_EXP_SLTSTA_CC);
 821
 822         /* Disable software notification */
 823         pcie_disable_notification(ctrl);
 824
 825         ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
 826                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 827                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 828                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 829                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 830                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 831                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 832                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 833                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 834                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
 835
 836         if (pcie_init_slot(ctrl))
 837                 goto abort_ctrl;
 838
 839         return ctrl;
 840
 841 abort_ctrl:
 842         kfree(ctrl);
 843 abort:
 844         return NULL;
 845 }
 846
 847 void pciehp_release_ctrl(struct controller *ctrl)
 848 {
 849         pcie_shutdown_notification(ctrl);
 850         pcie_cleanup_slot(ctrl);
 851         kfree(ctrl);
 852 }