1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/jiffies.h>
7 #include <asm/io_apic.h>
10 #include <linux/intel-iommu.h>
11 #include "intr_remapping.h"
12 #include <acpi/acpi.h>
14 static struct ioapic_scope ir_ioapic
[MAX_IO_APICS
];
15 static int ir_ioapic_num
;
16 int intr_remapping_enabled
;
19 struct intel_iommu
*iommu
;
25 #ifdef CONFIG_GENERIC_HARDIRQS
26 static struct irq_2_iommu
*get_one_free_irq_2_iommu(int cpu
)
28 struct irq_2_iommu
*iommu
;
31 node
= cpu_to_node(cpu
);
33 iommu
= kzalloc_node(sizeof(*iommu
), GFP_ATOMIC
, node
);
34 printk(KERN_DEBUG
"alloc irq_2_iommu on cpu %d node %d\n", cpu
, node
);
39 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
41 struct irq_desc
*desc
;
43 desc
= irq_to_desc(irq
);
45 if (WARN_ON_ONCE(!desc
))
48 return desc
->irq_2_iommu
;
51 static struct irq_2_iommu
*irq_2_iommu_alloc_cpu(unsigned int irq
, int cpu
)
53 struct irq_desc
*desc
;
54 struct irq_2_iommu
*irq_iommu
;
57 * alloc irq desc if not allocated already.
59 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
61 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
65 irq_iommu
= desc
->irq_2_iommu
;
68 desc
->irq_2_iommu
= get_one_free_irq_2_iommu(cpu
);
70 return desc
->irq_2_iommu
;
73 static struct irq_2_iommu
*irq_2_iommu_alloc(unsigned int irq
)
75 return irq_2_iommu_alloc_cpu(irq
, boot_cpu_id
);
78 #else /* !CONFIG_SPARSE_IRQ */
80 static struct irq_2_iommu irq_2_iommuX
[NR_IRQS
];
82 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
85 return &irq_2_iommuX
[irq
];
89 static struct irq_2_iommu
*irq_2_iommu_alloc(unsigned int irq
)
91 return irq_2_iommu(irq
);
95 static DEFINE_SPINLOCK(irq_2_ir_lock
);
97 static struct irq_2_iommu
*valid_irq_2_iommu(unsigned int irq
)
99 struct irq_2_iommu
*irq_iommu
;
101 irq_iommu
= irq_2_iommu(irq
);
106 if (!irq_iommu
->iommu
)
112 int irq_remapped(int irq
)
114 return valid_irq_2_iommu(irq
) != NULL
;
117 int get_irte(int irq
, struct irte
*entry
)
120 struct irq_2_iommu
*irq_iommu
;
126 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
127 irq_iommu
= valid_irq_2_iommu(irq
);
129 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
133 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
134 *entry
= *(irq_iommu
->iommu
->ir_table
->base
+ index
);
136 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
140 int alloc_irte(struct intel_iommu
*iommu
, int irq
, u16 count
)
142 struct ir_table
*table
= iommu
->ir_table
;
143 struct irq_2_iommu
*irq_iommu
;
144 u16 index
, start_index
;
145 unsigned int mask
= 0;
152 #ifndef CONFIG_SPARSE_IRQ
153 /* protect irq_2_iommu_alloc later */
159 * start the IRTE search from index 0.
161 index
= start_index
= 0;
164 count
= __roundup_pow_of_two(count
);
168 if (mask
> ecap_max_handle_mask(iommu
->ecap
)) {
170 "Requested mask %x exceeds the max invalidation handle"
171 " mask value %Lx\n", mask
,
172 ecap_max_handle_mask(iommu
->ecap
));
176 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
178 for (i
= index
; i
< index
+ count
; i
++)
179 if (table
->base
[i
].present
)
181 /* empty index found */
182 if (i
== index
+ count
)
185 index
= (index
+ count
) % INTR_REMAP_TABLE_ENTRIES
;
187 if (index
== start_index
) {
188 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
189 printk(KERN_ERR
"can't allocate an IRTE\n");
194 for (i
= index
; i
< index
+ count
; i
++)
195 table
->base
[i
].present
= 1;
197 irq_iommu
= irq_2_iommu_alloc(irq
);
199 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
200 printk(KERN_ERR
"can't allocate irq_2_iommu\n");
204 irq_iommu
->iommu
= iommu
;
205 irq_iommu
->irte_index
= index
;
206 irq_iommu
->sub_handle
= 0;
207 irq_iommu
->irte_mask
= mask
;
209 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
214 static int qi_flush_iec(struct intel_iommu
*iommu
, int index
, int mask
)
218 desc
.low
= QI_IEC_IIDEX(index
) | QI_IEC_TYPE
| QI_IEC_IM(mask
)
222 return qi_submit_sync(&desc
, iommu
);
225 int map_irq_to_irte_handle(int irq
, u16
*sub_handle
)
228 struct irq_2_iommu
*irq_iommu
;
231 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
232 irq_iommu
= valid_irq_2_iommu(irq
);
234 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
238 *sub_handle
= irq_iommu
->sub_handle
;
239 index
= irq_iommu
->irte_index
;
240 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
244 int set_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
, u16 subhandle
)
246 struct irq_2_iommu
*irq_iommu
;
249 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
251 irq_iommu
= irq_2_iommu_alloc(irq
);
254 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
255 printk(KERN_ERR
"can't allocate irq_2_iommu\n");
259 irq_iommu
->iommu
= iommu
;
260 irq_iommu
->irte_index
= index
;
261 irq_iommu
->sub_handle
= subhandle
;
262 irq_iommu
->irte_mask
= 0;
264 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
269 int clear_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
)
271 struct irq_2_iommu
*irq_iommu
;
274 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
275 irq_iommu
= valid_irq_2_iommu(irq
);
277 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
281 irq_iommu
->iommu
= NULL
;
282 irq_iommu
->irte_index
= 0;
283 irq_iommu
->sub_handle
= 0;
284 irq_2_iommu(irq
)->irte_mask
= 0;
286 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
291 int modify_irte(int irq
, struct irte
*irte_modified
)
296 struct intel_iommu
*iommu
;
297 struct irq_2_iommu
*irq_iommu
;
300 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
301 irq_iommu
= valid_irq_2_iommu(irq
);
303 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
307 iommu
= irq_iommu
->iommu
;
309 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
310 irte
= &iommu
->ir_table
->base
[index
];
312 set_64bit((unsigned long *)irte
, irte_modified
->low
);
313 __iommu_flush_cache(iommu
, irte
, sizeof(*irte
));
315 rc
= qi_flush_iec(iommu
, index
, 0);
316 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
321 int flush_irte(int irq
)
325 struct intel_iommu
*iommu
;
326 struct irq_2_iommu
*irq_iommu
;
329 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
330 irq_iommu
= valid_irq_2_iommu(irq
);
332 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
336 iommu
= irq_iommu
->iommu
;
338 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
340 rc
= qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
341 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
346 struct intel_iommu
*map_ioapic_to_ir(int apic
)
350 for (i
= 0; i
< MAX_IO_APICS
; i
++)
351 if (ir_ioapic
[i
].id
== apic
)
352 return ir_ioapic
[i
].iommu
;
356 struct intel_iommu
*map_dev_to_ir(struct pci_dev
*dev
)
358 struct dmar_drhd_unit
*drhd
;
360 drhd
= dmar_find_matched_drhd_unit(dev
);
367 int free_irte(int irq
)
372 struct intel_iommu
*iommu
;
373 struct irq_2_iommu
*irq_iommu
;
376 spin_lock_irqsave(&irq_2_ir_lock
, flags
);
377 irq_iommu
= valid_irq_2_iommu(irq
);
379 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
383 iommu
= irq_iommu
->iommu
;
385 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
386 irte
= &iommu
->ir_table
->base
[index
];
388 if (!irq_iommu
->sub_handle
) {
389 for (i
= 0; i
< (1 << irq_iommu
->irte_mask
); i
++)
390 set_64bit((unsigned long *)(irte
+ i
), 0);
391 rc
= qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
394 irq_iommu
->iommu
= NULL
;
395 irq_iommu
->irte_index
= 0;
396 irq_iommu
->sub_handle
= 0;
397 irq_iommu
->irte_mask
= 0;
399 spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
404 static void iommu_set_intr_remapping(struct intel_iommu
*iommu
, int mode
)
410 addr
= virt_to_phys((void *)iommu
->ir_table
->base
);
412 spin_lock_irqsave(&iommu
->register_lock
, flags
);
414 dmar_writeq(iommu
->reg
+ DMAR_IRTA_REG
,
415 (addr
) | IR_X2APIC_MODE(mode
) | INTR_REMAP_TABLE_REG_SIZE
);
417 /* Set interrupt-remapping table pointer */
418 iommu
->gcmd
|= DMA_GCMD_SIRTP
;
419 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
421 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
422 readl
, (sts
& DMA_GSTS_IRTPS
), sts
);
423 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
426 spin_lock_irqsave(&iommu
->register_lock
, flags
);
428 /* enable comaptiblity format interrupt pass through */
429 iommu
->gcmd
|= DMA_GCMD_CFI
;
430 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
432 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
433 readl
, (sts
& DMA_GSTS_CFIS
), sts
);
435 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
439 * global invalidation of interrupt entry cache before enabling
440 * interrupt-remapping.
442 qi_global_iec(iommu
);
444 spin_lock_irqsave(&iommu
->register_lock
, flags
);
446 /* Enable interrupt-remapping */
447 iommu
->gcmd
|= DMA_GCMD_IRE
;
448 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
450 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
451 readl
, (sts
& DMA_GSTS_IRES
), sts
);
453 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
457 static int setup_intr_remapping(struct intel_iommu
*iommu
, int mode
)
459 struct ir_table
*ir_table
;
462 ir_table
= iommu
->ir_table
= kzalloc(sizeof(struct ir_table
),
465 if (!iommu
->ir_table
)
468 pages
= alloc_pages(GFP_ATOMIC
| __GFP_ZERO
, INTR_REMAP_PAGE_ORDER
);
471 printk(KERN_ERR
"failed to allocate pages of order %d\n",
472 INTR_REMAP_PAGE_ORDER
);
473 kfree(iommu
->ir_table
);
477 ir_table
->base
= page_address(pages
);
479 iommu_set_intr_remapping(iommu
, mode
);
484 * Disable Interrupt Remapping.
486 static void iommu_disable_intr_remapping(struct intel_iommu
*iommu
)
491 if (!ecap_ir_support(iommu
->ecap
))
495 * global invalidation of interrupt entry cache before disabling
496 * interrupt-remapping.
498 qi_global_iec(iommu
);
500 spin_lock_irqsave(&iommu
->register_lock
, flags
);
502 sts
= dmar_readq(iommu
->reg
+ DMAR_GSTS_REG
);
503 if (!(sts
& DMA_GSTS_IRES
))
506 iommu
->gcmd
&= ~DMA_GCMD_IRE
;
507 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
509 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
510 readl
, !(sts
& DMA_GSTS_IRES
), sts
);
513 spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
516 int __init
enable_intr_remapping(int eim
)
518 struct dmar_drhd_unit
*drhd
;
521 for_each_drhd_unit(drhd
) {
522 struct intel_iommu
*iommu
= drhd
->iommu
;
525 * If the queued invalidation is already initialized,
526 * shouldn't disable it.
532 * Clear previous faults.
534 dmar_fault(-1, iommu
);
537 * Disable intr remapping and queued invalidation, if already
538 * enabled prior to OS handover.
540 iommu_disable_intr_remapping(iommu
);
542 dmar_disable_qi(iommu
);
546 * check for the Interrupt-remapping support
548 for_each_drhd_unit(drhd
) {
549 struct intel_iommu
*iommu
= drhd
->iommu
;
551 if (!ecap_ir_support(iommu
->ecap
))
554 if (eim
&& !ecap_eim_support(iommu
->ecap
)) {
555 printk(KERN_INFO
"DRHD %Lx: EIM not supported by DRHD, "
556 " ecap %Lx\n", drhd
->reg_base_addr
, iommu
->ecap
);
562 * Enable queued invalidation for all the DRHD's.
564 for_each_drhd_unit(drhd
) {
566 struct intel_iommu
*iommu
= drhd
->iommu
;
567 ret
= dmar_enable_qi(iommu
);
570 printk(KERN_ERR
"DRHD %Lx: failed to enable queued, "
571 " invalidation, ecap %Lx, ret %d\n",
572 drhd
->reg_base_addr
, iommu
->ecap
, ret
);
578 * Setup Interrupt-remapping for all the DRHD's now.
580 for_each_drhd_unit(drhd
) {
581 struct intel_iommu
*iommu
= drhd
->iommu
;
583 if (!ecap_ir_support(iommu
->ecap
))
586 if (setup_intr_remapping(iommu
, eim
))
595 intr_remapping_enabled
= 1;
601 * handle error condition gracefully here!
606 static int ir_parse_ioapic_scope(struct acpi_dmar_header
*header
,
607 struct intel_iommu
*iommu
)
609 struct acpi_dmar_hardware_unit
*drhd
;
610 struct acpi_dmar_device_scope
*scope
;
613 drhd
= (struct acpi_dmar_hardware_unit
*)header
;
615 start
= (void *)(drhd
+ 1);
616 end
= ((void *)drhd
) + header
->length
;
618 while (start
< end
) {
620 if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_IOAPIC
) {
621 if (ir_ioapic_num
== MAX_IO_APICS
) {
622 printk(KERN_WARNING
"Exceeded Max IO APICS\n");
626 printk(KERN_INFO
"IOAPIC id %d under DRHD base"
627 " 0x%Lx\n", scope
->enumeration_id
,
630 ir_ioapic
[ir_ioapic_num
].iommu
= iommu
;
631 ir_ioapic
[ir_ioapic_num
].id
= scope
->enumeration_id
;
634 start
+= scope
->length
;
641 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
644 int __init
parse_ioapics_under_ir(void)
646 struct dmar_drhd_unit
*drhd
;
647 int ir_supported
= 0;
649 for_each_drhd_unit(drhd
) {
650 struct intel_iommu
*iommu
= drhd
->iommu
;
652 if (ecap_ir_support(iommu
->ecap
)) {
653 if (ir_parse_ioapic_scope(drhd
->hdr
, iommu
))
660 if (ir_supported
&& ir_ioapic_num
!= nr_ioapics
) {
662 "Not all IO-APIC's listed under remapping hardware\n");
669 void disable_intr_remapping(void)
671 struct dmar_drhd_unit
*drhd
;
672 struct intel_iommu
*iommu
= NULL
;
675 * Disable Interrupt-remapping for all the DRHD's now.
677 for_each_iommu(iommu
, drhd
) {
678 if (!ecap_ir_support(iommu
->ecap
))
681 iommu_disable_intr_remapping(iommu
);
685 int reenable_intr_remapping(int eim
)
687 struct dmar_drhd_unit
*drhd
;
689 struct intel_iommu
*iommu
= NULL
;
691 for_each_iommu(iommu
, drhd
)
693 dmar_reenable_qi(iommu
);
696 * Setup Interrupt-remapping for all the DRHD's now.
698 for_each_iommu(iommu
, drhd
) {
699 if (!ecap_ir_support(iommu
->ecap
))
702 /* Set up interrupt remapping for iommu.*/
703 iommu_set_intr_remapping(iommu
, eim
);
714 * handle error condition gracefully here!