drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/jiffies.h>
   5 #include <linux/pci.h>
   6 #include <linux/irq.h>
   7 #include <asm/io_apic.h>
   8 #include <asm/smp.h>
   9 #include <asm/cpu.h>
  10 #include <linux/intel-iommu.h>
  11 #include "intr_remapping.h"
  12 #include <acpi/acpi.h>
  13
  14 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  15 static int ir_ioapic_num;
  16 int intr_remapping_enabled;
  17
  18 static int disable_intremap;
  19 static __init int setup_nointremap(char *str)
  20 {
  21         disable_intremap = 1;
  22         return 0;
  23 }
  24 early_param("nointremap", setup_nointremap);
  25
  26 struct irq_2_iommu {
  27         struct intel_iommu *iommu;
  28         u16 irte_index;
  29         u16 sub_handle;
  30         u8  irte_mask;
  31 };
  32
  33 #ifdef CONFIG_GENERIC_HARDIRQS
  34 static struct irq_2_iommu *get_one_free_irq_2_iommu(int node)
  35 {
  36         struct irq_2_iommu *iommu;
  37
  38         iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
  39         printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node);
  40
  41         return iommu;
  42 }
  43
  44 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  45 {
  46         struct irq_desc *desc;
  47
  48         desc = irq_to_desc(irq);
  49
  50         if (WARN_ON_ONCE(!desc))
  51                 return NULL;
  52
  53         return desc->irq_2_iommu;
  54 }
  55
  56 static struct irq_2_iommu *irq_2_iommu_alloc_node(unsigned int irq, int node)
  57 {
  58         struct irq_desc *desc;
  59         struct irq_2_iommu *irq_iommu;
  60
  61         /*
  62          * alloc irq desc if not allocated already.
  63          */
  64         desc = irq_to_desc_alloc_node(irq, node);
  65         if (!desc) {
  66                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  67                 return NULL;
  68         }
  69
  70         irq_iommu = desc->irq_2_iommu;
  71
  72         if (!irq_iommu)
  73                 desc->irq_2_iommu = get_one_free_irq_2_iommu(node);
  74
  75         return desc->irq_2_iommu;
  76 }
  77
  78 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  79 {
  80         return irq_2_iommu_alloc_node(irq, cpu_to_node(boot_cpu_id));
  81 }
  82
  83 #else /* !CONFIG_SPARSE_IRQ */
  84
  85 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  86
  87 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  88 {
  89         if (irq < nr_irqs)
  90                 return &irq_2_iommuX[irq];
  91
  92         return NULL;
  93 }
  94 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  95 {
  96         return irq_2_iommu(irq);
  97 }
  98 #endif
  99
 100 static DEFINE_SPINLOCK(irq_2_ir_lock);
 101
 102 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
 103 {
 104         struct irq_2_iommu *irq_iommu;
 105
 106         irq_iommu = irq_2_iommu(irq);
 107
 108         if (!irq_iommu)
 109                 return NULL;
 110
 111         if (!irq_iommu->iommu)
 112                 return NULL;
 113
 114         return irq_iommu;
 115 }
 116
 117 int irq_remapped(int irq)
 118 {
 119         return valid_irq_2_iommu(irq) != NULL;
 120 }
 121
 122 int get_irte(int irq, struct irte *entry)
 123 {
 124         int index;
 125         struct irq_2_iommu *irq_iommu;
 126         unsigned long flags;
 127
 128         if (!entry)
 129                 return -1;
 130
 131         spin_lock_irqsave(&irq_2_ir_lock, flags);
 132         irq_iommu = valid_irq_2_iommu(irq);
 133         if (!irq_iommu) {
 134                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 135                 return -1;
 136         }
 137
 138         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 139         *entry = *(irq_iommu->iommu->ir_table->base + index);
 140
 141         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 142         return 0;
 143 }
 144
 145 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 146 {
 147         struct ir_table *table = iommu->ir_table;
 148         struct irq_2_iommu *irq_iommu;
 149         u16 index, start_index;
 150         unsigned int mask = 0;
 151         unsigned long flags;
 152         int i;
 153
 154         if (!count)
 155                 return -1;
 156
 157 #ifndef CONFIG_SPARSE_IRQ
 158         /* protect irq_2_iommu_alloc later */
 159         if (irq >= nr_irqs)
 160                 return -1;
 161 #endif
 162
 163         /*
 164          * start the IRTE search from index 0.
 165          */
 166         index = start_index = 0;
 167
 168         if (count > 1) {
 169                 count = __roundup_pow_of_two(count);
 170                 mask = ilog2(count);
 171         }
 172
 173         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 174                 printk(KERN_ERR
 175                        "Requested mask %x exceeds the max invalidation handle"
 176                        " mask value %Lx\n", mask,
 177                        ecap_max_handle_mask(iommu->ecap));
 178                 return -1;
 179         }
 180
 181         spin_lock_irqsave(&irq_2_ir_lock, flags);
 182         do {
 183                 for (i = index; i < index + count; i++)
 184                         if  (table->base[i].present)
 185                                 break;
 186                 /* empty index found */
 187                 if (i == index + count)
 188                         break;
 189
 190                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 191
 192                 if (index == start_index) {
 193                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 194                         printk(KERN_ERR "can't allocate an IRTE\n");
 195                         return -1;
 196                 }
 197         } while (1);
 198
 199         for (i = index; i < index + count; i++)
 200                 table->base[i].present = 1;
 201
 202         irq_iommu = irq_2_iommu_alloc(irq);
 203         if (!irq_iommu) {
 204                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 205                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 206                 return -1;
 207         }
 208
 209         irq_iommu->iommu = iommu;
 210         irq_iommu->irte_index =  index;
 211         irq_iommu->sub_handle = 0;
 212         irq_iommu->irte_mask = mask;
 213
 214         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 215
 216         return index;
 217 }
 218
 219 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 220 {
 221         struct qi_desc desc;
 222
 223         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 224                    | QI_IEC_SELECTIVE;
 225         desc.high = 0;
 226
 227         return qi_submit_sync(&desc, iommu);
 228 }
 229
 230 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 231 {
 232         int index;
 233         struct irq_2_iommu *irq_iommu;
 234         unsigned long flags;
 235
 236         spin_lock_irqsave(&irq_2_ir_lock, flags);
 237         irq_iommu = valid_irq_2_iommu(irq);
 238         if (!irq_iommu) {
 239                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 240                 return -1;
 241         }
 242
 243         *sub_handle = irq_iommu->sub_handle;
 244         index = irq_iommu->irte_index;
 245         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 246         return index;
 247 }
 248
 249 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 250 {
 251         struct irq_2_iommu *irq_iommu;
 252         unsigned long flags;
 253
 254         spin_lock_irqsave(&irq_2_ir_lock, flags);
 255
 256         irq_iommu = irq_2_iommu_alloc(irq);
 257
 258         if (!irq_iommu) {
 259                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 260                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 261                 return -1;
 262         }
 263
 264         irq_iommu->iommu = iommu;
 265         irq_iommu->irte_index = index;
 266         irq_iommu->sub_handle = subhandle;
 267         irq_iommu->irte_mask = 0;
 268
 269         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 270
 271         return 0;
 272 }
 273
 274 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 275 {
 276         struct irq_2_iommu *irq_iommu;
 277         unsigned long flags;
 278
 279         spin_lock_irqsave(&irq_2_ir_lock, flags);
 280         irq_iommu = valid_irq_2_iommu(irq);
 281         if (!irq_iommu) {
 282                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 283                 return -1;
 284         }
 285
 286         irq_iommu->iommu = NULL;
 287         irq_iommu->irte_index = 0;
 288         irq_iommu->sub_handle = 0;
 289         irq_2_iommu(irq)->irte_mask = 0;
 290
 291         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 292
 293         return 0;
 294 }
 295
 296 int modify_irte(int irq, struct irte *irte_modified)
 297 {
 298         int rc;
 299         int index;
 300         struct irte *irte;
 301         struct intel_iommu *iommu;
 302         struct irq_2_iommu *irq_iommu;
 303         unsigned long flags;
 304
 305         spin_lock_irqsave(&irq_2_ir_lock, flags);
 306         irq_iommu = valid_irq_2_iommu(irq);
 307         if (!irq_iommu) {
 308                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 309                 return -1;
 310         }
 311
 312         iommu = irq_iommu->iommu;
 313
 314         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 315         irte = &iommu->ir_table->base[index];
 316
 317         set_64bit((unsigned long *)irte, irte_modified->low);
 318         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 319
 320         rc = qi_flush_iec(iommu, index, 0);
 321         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 322
 323         return rc;
 324 }
 325
 326 int flush_irte(int irq)
 327 {
 328         int rc;
 329         int index;
 330         struct intel_iommu *iommu;
 331         struct irq_2_iommu *irq_iommu;
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&irq_2_ir_lock, flags);
 335         irq_iommu = valid_irq_2_iommu(irq);
 336         if (!irq_iommu) {
 337                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 338                 return -1;
 339         }
 340
 341         iommu = irq_iommu->iommu;
 342
 343         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 344
 345         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 346         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 347
 348         return rc;
 349 }
 350
 351 struct intel_iommu *map_ioapic_to_ir(int apic)
 352 {
 353         int i;
 354
 355         for (i = 0; i < MAX_IO_APICS; i++)
 356                 if (ir_ioapic[i].id == apic)
 357                         return ir_ioapic[i].iommu;
 358         return NULL;
 359 }
 360
 361 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 362 {
 363         struct dmar_drhd_unit *drhd;
 364
 365         drhd = dmar_find_matched_drhd_unit(dev);
 366         if (!drhd)
 367                 return NULL;
 368
 369         return drhd->iommu;
 370 }
 371
 372 int free_irte(int irq)
 373 {
 374         int rc = 0;
 375         int index, i;
 376         struct irte *irte;
 377         struct intel_iommu *iommu;
 378         struct irq_2_iommu *irq_iommu;
 379         unsigned long flags;
 380
 381         spin_lock_irqsave(&irq_2_ir_lock, flags);
 382         irq_iommu = valid_irq_2_iommu(irq);
 383         if (!irq_iommu) {
 384                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 385                 return -1;
 386         }
 387
 388         iommu = irq_iommu->iommu;
 389
 390         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 391         irte = &iommu->ir_table->base[index];
 392
 393         if (!irq_iommu->sub_handle) {
 394                 for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
 395                         set_64bit((unsigned long *)(irte + i), 0);
 396                 rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 397         }
 398
 399         irq_iommu->iommu = NULL;
 400         irq_iommu->irte_index = 0;
 401         irq_iommu->sub_handle = 0;
 402         irq_iommu->irte_mask = 0;
 403
 404         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 405
 406         return rc;
 407 }
 408
 409 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 410 {
 411         u64 addr;
 412         u32 cmd, sts;
 413         unsigned long flags;
 414
 415         addr = virt_to_phys((void *)iommu->ir_table->base);
 416
 417         spin_lock_irqsave(&iommu->register_lock, flags);
 418
 419         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 420                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 421
 422         /* Set interrupt-remapping table pointer */
 423         cmd = iommu->gcmd | DMA_GCMD_SIRTP;
 424         iommu->gcmd |= DMA_GCMD_SIRTP;
 425         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 426
 427         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 428                       readl, (sts & DMA_GSTS_IRTPS), sts);
 429         spin_unlock_irqrestore(&iommu->register_lock, flags);
 430
 431         /*
 432          * global invalidation of interrupt entry cache before enabling
 433          * interrupt-remapping.
 434          */
 435         qi_global_iec(iommu);
 436
 437         spin_lock_irqsave(&iommu->register_lock, flags);
 438
 439         /* Enable interrupt-remapping */
 440         cmd = iommu->gcmd | DMA_GCMD_IRE;
 441         iommu->gcmd |= DMA_GCMD_IRE;
 442         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 443
 444         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 445                       readl, (sts & DMA_GSTS_IRES), sts);
 446
 447         spin_unlock_irqrestore(&iommu->register_lock, flags);
 448 }
 449
 450
 451 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 452 {
 453         struct ir_table *ir_table;
 454         struct page *pages;
 455
 456         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 457                                              GFP_ATOMIC);
 458
 459         if (!iommu->ir_table)
 460                 return -ENOMEM;
 461
 462         pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
 463
 464         if (!pages) {
 465                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 466                        INTR_REMAP_PAGE_ORDER);
 467                 kfree(iommu->ir_table);
 468                 return -ENOMEM;
 469         }
 470
 471         ir_table->base = page_address(pages);
 472
 473         iommu_set_intr_remapping(iommu, mode);
 474         return 0;
 475 }
 476
 477 /*
 478  * Disable Interrupt Remapping.
 479  */
 480 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
 481 {
 482         unsigned long flags;
 483         u32 sts;
 484
 485         if (!ecap_ir_support(iommu->ecap))
 486                 return;
 487
 488         /*
 489          * global invalidation of interrupt entry cache before disabling
 490          * interrupt-remapping.
 491          */
 492         qi_global_iec(iommu);
 493
 494         spin_lock_irqsave(&iommu->register_lock, flags);
 495
 496         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 497         if (!(sts & DMA_GSTS_IRES))
 498                 goto end;
 499
 500         iommu->gcmd &= ~DMA_GCMD_IRE;
 501         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 502
 503         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 504                       readl, !(sts & DMA_GSTS_IRES), sts);
 505
 506 end:
 507         spin_unlock_irqrestore(&iommu->register_lock, flags);
 508 }
 509
 510 int __init intr_remapping_supported(void)
 511 {
 512         struct dmar_drhd_unit *drhd;
 513
 514         if (disable_intremap)
 515                 return 0;
 516
 517         for_each_drhd_unit(drhd) {
 518                 struct intel_iommu *iommu = drhd->iommu;
 519
 520                 if (!ecap_ir_support(iommu->ecap))
 521                         return 0;
 522         }
 523
 524         return 1;
 525 }
 526
 527 int __init enable_intr_remapping(int eim)
 528 {
 529         struct dmar_drhd_unit *drhd;
 530         int setup = 0;
 531
 532         for_each_drhd_unit(drhd) {
 533                 struct intel_iommu *iommu = drhd->iommu;
 534
 535                 /*
 536                  * If the queued invalidation is already initialized,
 537                  * shouldn't disable it.
 538                  */
 539                 if (iommu->qi)
 540                         continue;
 541
 542                 /*
 543                  * Clear previous faults.
 544                  */
 545                 dmar_fault(-1, iommu);
 546
 547                 /*
 548                  * Disable intr remapping and queued invalidation, if already
 549                  * enabled prior to OS handover.
 550                  */
 551                 iommu_disable_intr_remapping(iommu);
 552
 553                 dmar_disable_qi(iommu);
 554         }
 555
 556         /*
 557          * check for the Interrupt-remapping support
 558          */
 559         for_each_drhd_unit(drhd) {
 560                 struct intel_iommu *iommu = drhd->iommu;
 561
 562                 if (!ecap_ir_support(iommu->ecap))
 563                         continue;
 564
 565                 if (eim && !ecap_eim_support(iommu->ecap)) {
 566                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 567                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 568                         return -1;
 569                 }
 570         }
 571
 572         /*
 573          * Enable queued invalidation for all the DRHD's.
 574          */
 575         for_each_drhd_unit(drhd) {
 576                 int ret;
 577                 struct intel_iommu *iommu = drhd->iommu;
 578                 ret = dmar_enable_qi(iommu);
 579
 580                 if (ret) {
 581                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 582                                " invalidation, ecap %Lx, ret %d\n",
 583                                drhd->reg_base_addr, iommu->ecap, ret);
 584                         return -1;
 585                 }
 586         }
 587
 588         /*
 589          * Setup Interrupt-remapping for all the DRHD's now.
 590          */
 591         for_each_drhd_unit(drhd) {
 592                 struct intel_iommu *iommu = drhd->iommu;
 593
 594                 if (!ecap_ir_support(iommu->ecap))
 595                         continue;
 596
 597                 if (setup_intr_remapping(iommu, eim))
 598                         goto error;
 599
 600                 setup = 1;
 601         }
 602
 603         if (!setup)
 604                 goto error;
 605
 606         intr_remapping_enabled = 1;
 607
 608         return 0;
 609
 610 error:
 611         /*
 612          * handle error condition gracefully here!
 613          */
 614         return -1;
 615 }
 616
 617 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
 618                                  struct intel_iommu *iommu)
 619 {
 620         struct acpi_dmar_hardware_unit *drhd;
 621         struct acpi_dmar_device_scope *scope;
 622         void *start, *end;
 623
 624         drhd = (struct acpi_dmar_hardware_unit *)header;
 625
 626         start = (void *)(drhd + 1);
 627         end = ((void *)drhd) + header->length;
 628
 629         while (start < end) {
 630                 scope = start;
 631                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 632                         if (ir_ioapic_num == MAX_IO_APICS) {
 633                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 634                                 return -1;
 635                         }
 636
 637                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
 638                                " 0x%Lx\n", scope->enumeration_id,
 639                                drhd->address);
 640
 641                         ir_ioapic[ir_ioapic_num].iommu = iommu;
 642                         ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
 643                         ir_ioapic_num++;
 644                 }
 645                 start += scope->length;
 646         }
 647
 648         return 0;
 649 }
 650
 651 /*
 652  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 653  * hardware unit.
 654  */
 655 int __init parse_ioapics_under_ir(void)
 656 {
 657         struct dmar_drhd_unit *drhd;
 658         int ir_supported = 0;
 659
 660         for_each_drhd_unit(drhd) {
 661                 struct intel_iommu *iommu = drhd->iommu;
 662
 663                 if (ecap_ir_support(iommu->ecap)) {
 664                         if (ir_parse_ioapic_scope(drhd->hdr, iommu))
 665                                 return -1;
 666
 667                         ir_supported = 1;
 668                 }
 669         }
 670
 671         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 672                 printk(KERN_WARNING
 673                        "Not all IO-APIC's listed under remapping hardware\n");
 674                 return -1;
 675         }
 676
 677         return ir_supported;
 678 }
 679
 680 void disable_intr_remapping(void)
 681 {
 682         struct dmar_drhd_unit *drhd;
 683         struct intel_iommu *iommu = NULL;
 684
 685         /*
 686          * Disable Interrupt-remapping for all the DRHD's now.
 687          */
 688         for_each_iommu(iommu, drhd) {
 689                 if (!ecap_ir_support(iommu->ecap))
 690                         continue;
 691
 692                 iommu_disable_intr_remapping(iommu);
 693         }
 694 }
 695
 696 int reenable_intr_remapping(int eim)
 697 {
 698         struct dmar_drhd_unit *drhd;
 699         int setup = 0;
 700         struct intel_iommu *iommu = NULL;
 701
 702         for_each_iommu(iommu, drhd)
 703                 if (iommu->qi)
 704                         dmar_reenable_qi(iommu);
 705
 706         /*
 707          * Setup Interrupt-remapping for all the DRHD's now.
 708          */
 709         for_each_iommu(iommu, drhd) {
 710                 if (!ecap_ir_support(iommu->ecap))
 711                         continue;
 712
 713                 /* Set up interrupt remapping for iommu.*/
 714                 iommu_set_intr_remapping(iommu, eim);
 715                 setup = 1;
 716         }
 717
 718         if (!setup)
 719                 goto error;
 720
 721         return 0;
 722
 723 error:
 724         /*
 725          * handle error condition gracefully here!
 726          */
 727         return -1;
 728 }
 729