3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
25 static int pci_msi_enable
= 1;
27 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
32 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
34 struct msi_chip
*chip
= dev
->bus
->msi
;
37 if (!chip
|| !chip
->setup_irq
)
40 err
= chip
->setup_irq(chip
, dev
, desc
);
44 irq_set_chip_data(desc
->irq
, chip
);
49 void __weak
arch_teardown_msi_irq(unsigned int irq
)
51 struct msi_chip
*chip
= irq_get_chip_data(irq
);
53 if (!chip
|| !chip
->teardown_irq
)
56 chip
->teardown_irq(chip
, irq
);
59 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
61 struct msi_desc
*entry
;
65 * If an architecture wants to support multiple MSI, it needs to
66 * override arch_setup_msi_irqs()
68 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
71 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
72 ret
= arch_setup_msi_irq(dev
, entry
);
83 * We have a default implementation available as a separate non-weak
84 * function, as it is used by the Xen x86 PCI code
86 void default_teardown_msi_irqs(struct pci_dev
*dev
)
88 struct msi_desc
*entry
;
90 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
95 nvec
= entry
->nvec_used
;
97 nvec
= 1 << entry
->msi_attrib
.multiple
;
98 for (i
= 0; i
< nvec
; i
++)
99 arch_teardown_msi_irq(entry
->irq
+ i
);
103 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
105 return default_teardown_msi_irqs(dev
);
108 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
110 struct msi_desc
*entry
;
113 if (dev
->msix_enabled
) {
114 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
115 if (irq
== entry
->irq
)
118 } else if (dev
->msi_enabled
) {
119 entry
= irq_get_msi_desc(irq
);
123 __write_msi_msg(entry
, &entry
->msg
);
126 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
128 return default_restore_msi_irqs(dev
);
131 static void msi_set_enable(struct pci_dev
*dev
, int enable
)
135 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
136 control
&= ~PCI_MSI_FLAGS_ENABLE
;
138 control
|= PCI_MSI_FLAGS_ENABLE
;
139 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
142 static void msix_clear_and_set_ctrl(struct pci_dev
*dev
, u16 clear
, u16 set
)
146 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
149 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, ctrl
);
152 static inline __attribute_const__ u32
msi_mask(unsigned x
)
154 /* Don't shift by >= width of type */
157 return (1 << (1 << x
)) - 1;
161 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
162 * mask all MSI interrupts by clearing the MSI enable bit does not work
163 * reliably as devices without an INTx disable bit will then generate a
164 * level IRQ which will never be cleared.
166 u32
default_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
168 u32 mask_bits
= desc
->masked
;
170 if (!desc
->msi_attrib
.maskbit
)
175 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
180 __weak u32
arch_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
182 return default_msi_mask_irq(desc
, mask
, flag
);
185 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
187 desc
->masked
= arch_msi_mask_irq(desc
, mask
, flag
);
191 * This internal function does not flush PCI writes to the device.
192 * All users must ensure that they read from the device before either
193 * assuming that the device state is up to date, or returning out of this
194 * file. This saves a few milliseconds when initialising devices with lots
195 * of MSI-X interrupts.
197 u32
default_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
199 u32 mask_bits
= desc
->masked
;
200 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
201 PCI_MSIX_ENTRY_VECTOR_CTRL
;
202 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
204 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
205 writel(mask_bits
, desc
->mask_base
+ offset
);
210 __weak u32
arch_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
212 return default_msix_mask_irq(desc
, flag
);
215 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
217 desc
->masked
= arch_msix_mask_irq(desc
, flag
);
220 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
222 struct msi_desc
*desc
= irq_data_get_msi(data
);
224 if (desc
->msi_attrib
.is_msix
) {
225 msix_mask_irq(desc
, flag
);
226 readl(desc
->mask_base
); /* Flush write to device */
228 unsigned offset
= data
->irq
- desc
->irq
;
229 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
233 void mask_msi_irq(struct irq_data
*data
)
235 msi_set_mask_bit(data
, 1);
238 void unmask_msi_irq(struct irq_data
*data
)
240 msi_set_mask_bit(data
, 0);
243 void default_restore_msi_irqs(struct pci_dev
*dev
)
245 struct msi_desc
*entry
;
247 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
248 default_restore_msi_irq(dev
, entry
->irq
);
252 void __read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
254 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
256 if (entry
->msi_attrib
.is_msix
) {
257 void __iomem
*base
= entry
->mask_base
+
258 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
260 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
261 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
262 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
264 struct pci_dev
*dev
= entry
->dev
;
265 int pos
= dev
->msi_cap
;
268 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
270 if (entry
->msi_attrib
.is_64
) {
271 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
273 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
276 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
282 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
284 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
286 __read_msi_msg(entry
, msg
);
289 void __get_cached_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
291 /* Assert that the cache is valid, assuming that
292 * valid messages are not all-zeroes. */
293 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
299 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
301 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
303 __get_cached_msi_msg(entry
, msg
);
306 void __write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
308 if (entry
->dev
->current_state
!= PCI_D0
) {
309 /* Don't touch the hardware now */
310 } else if (entry
->msi_attrib
.is_msix
) {
312 base
= entry
->mask_base
+
313 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
315 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
316 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
317 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
319 struct pci_dev
*dev
= entry
->dev
;
320 int pos
= dev
->msi_cap
;
323 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
324 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
325 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
326 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
328 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
330 if (entry
->msi_attrib
.is_64
) {
331 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
333 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
336 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
343 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
345 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
347 __write_msi_msg(entry
, msg
);
350 static void free_msi_irqs(struct pci_dev
*dev
)
352 struct msi_desc
*entry
, *tmp
;
353 struct attribute
**msi_attrs
;
354 struct device_attribute
*dev_attr
;
357 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
361 if (entry
->nvec_used
)
362 nvec
= entry
->nvec_used
;
364 nvec
= 1 << entry
->msi_attrib
.multiple
;
365 for (i
= 0; i
< nvec
; i
++)
366 BUG_ON(irq_has_action(entry
->irq
+ i
));
369 arch_teardown_msi_irqs(dev
);
371 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
372 if (entry
->msi_attrib
.is_msix
) {
373 if (list_is_last(&entry
->list
, &dev
->msi_list
))
374 iounmap(entry
->mask_base
);
377 list_del(&entry
->list
);
381 if (dev
->msi_irq_groups
) {
382 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
383 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
384 while (msi_attrs
[count
]) {
385 dev_attr
= container_of(msi_attrs
[count
],
386 struct device_attribute
, attr
);
387 kfree(dev_attr
->attr
.name
);
392 kfree(dev
->msi_irq_groups
[0]);
393 kfree(dev
->msi_irq_groups
);
394 dev
->msi_irq_groups
= NULL
;
398 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
400 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
404 INIT_LIST_HEAD(&desc
->list
);
410 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
412 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
413 pci_intx(dev
, enable
);
416 static void __pci_restore_msi_state(struct pci_dev
*dev
)
419 struct msi_desc
*entry
;
421 if (!dev
->msi_enabled
)
424 entry
= irq_get_msi_desc(dev
->irq
);
426 pci_intx_for_msi(dev
, 0);
427 msi_set_enable(dev
, 0);
428 arch_restore_msi_irqs(dev
);
430 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
431 msi_mask_irq(entry
, msi_mask(entry
->msi_attrib
.multi_cap
),
433 control
&= ~PCI_MSI_FLAGS_QSIZE
;
434 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
435 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
438 static void __pci_restore_msix_state(struct pci_dev
*dev
)
440 struct msi_desc
*entry
;
442 if (!dev
->msix_enabled
)
444 BUG_ON(list_empty(&dev
->msi_list
));
446 /* route the table */
447 pci_intx_for_msi(dev
, 0);
448 msix_clear_and_set_ctrl(dev
, 0,
449 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
451 arch_restore_msi_irqs(dev
);
452 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
453 msix_mask_irq(entry
, entry
->masked
);
456 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
459 void pci_restore_msi_state(struct pci_dev
*dev
)
461 __pci_restore_msi_state(dev
);
462 __pci_restore_msix_state(dev
);
464 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
466 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
469 struct msi_desc
*entry
;
473 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
477 entry
= irq_get_msi_desc(irq
);
479 return sprintf(buf
, "%s\n",
480 entry
->msi_attrib
.is_msix
? "msix" : "msi");
485 static int populate_msi_sysfs(struct pci_dev
*pdev
)
487 struct attribute
**msi_attrs
;
488 struct attribute
*msi_attr
;
489 struct device_attribute
*msi_dev_attr
;
490 struct attribute_group
*msi_irq_group
;
491 const struct attribute_group
**msi_irq_groups
;
492 struct msi_desc
*entry
;
497 /* Determine how many msi entries we have */
498 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
504 /* Dynamically create the MSI attributes for the PCI device */
505 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
508 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
509 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
512 msi_attrs
[count
] = &msi_dev_attr
->attr
;
514 sysfs_attr_init(&msi_dev_attr
->attr
);
515 msi_dev_attr
->attr
.name
= kasprintf(GFP_KERNEL
, "%d",
517 if (!msi_dev_attr
->attr
.name
)
519 msi_dev_attr
->attr
.mode
= S_IRUGO
;
520 msi_dev_attr
->show
= msi_mode_show
;
524 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
527 msi_irq_group
->name
= "msi_irqs";
528 msi_irq_group
->attrs
= msi_attrs
;
530 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
532 goto error_irq_group
;
533 msi_irq_groups
[0] = msi_irq_group
;
535 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
537 goto error_irq_groups
;
538 pdev
->msi_irq_groups
= msi_irq_groups
;
543 kfree(msi_irq_groups
);
545 kfree(msi_irq_group
);
548 msi_attr
= msi_attrs
[count
];
550 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
551 kfree(msi_attr
->name
);
554 msi_attr
= msi_attrs
[count
];
560 static struct msi_desc
*msi_setup_entry(struct pci_dev
*dev
)
563 struct msi_desc
*entry
;
565 /* MSI Entry Initialization */
566 entry
= alloc_msi_entry(dev
);
570 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
572 entry
->msi_attrib
.is_msix
= 0;
573 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
574 entry
->msi_attrib
.entry_nr
= 0;
575 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
576 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
577 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
579 if (control
& PCI_MSI_FLAGS_64BIT
)
580 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
582 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
584 /* Save the initial mask status */
585 if (entry
->msi_attrib
.maskbit
)
586 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
592 * msi_capability_init - configure device's MSI capability structure
593 * @dev: pointer to the pci_dev data structure of MSI device function
594 * @nvec: number of interrupts to allocate
596 * Setup the MSI capability structure of the device with the requested
597 * number of interrupts. A return value of zero indicates the successful
598 * setup of an entry with the new MSI irq. A negative return value indicates
599 * an error, and a positive return value indicates the number of interrupts
600 * which could have been allocated.
602 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
604 struct msi_desc
*entry
;
608 msi_set_enable(dev
, 0); /* Disable MSI during set up */
610 entry
= msi_setup_entry(dev
);
614 /* All MSIs are unmasked by default, Mask them all */
615 mask
= msi_mask(entry
->msi_attrib
.multi_cap
);
616 msi_mask_irq(entry
, mask
, mask
);
618 list_add_tail(&entry
->list
, &dev
->msi_list
);
620 /* Configure MSI capability structure */
621 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
623 msi_mask_irq(entry
, mask
, ~mask
);
628 ret
= populate_msi_sysfs(dev
);
630 msi_mask_irq(entry
, mask
, ~mask
);
635 /* Set MSI enabled bits */
636 pci_intx_for_msi(dev
, 0);
637 msi_set_enable(dev
, 1);
638 dev
->msi_enabled
= 1;
640 dev
->irq
= entry
->irq
;
644 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
646 resource_size_t phys_addr
;
650 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
652 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
653 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
654 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
656 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
659 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
660 struct msix_entry
*entries
, int nvec
)
662 struct msi_desc
*entry
;
665 for (i
= 0; i
< nvec
; i
++) {
666 entry
= alloc_msi_entry(dev
);
672 /* No enough memory. Don't try again */
676 entry
->msi_attrib
.is_msix
= 1;
677 entry
->msi_attrib
.is_64
= 1;
678 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
679 entry
->msi_attrib
.default_irq
= dev
->irq
;
680 entry
->mask_base
= base
;
682 list_add_tail(&entry
->list
, &dev
->msi_list
);
688 static void msix_program_entries(struct pci_dev
*dev
,
689 struct msix_entry
*entries
)
691 struct msi_desc
*entry
;
694 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
695 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
696 PCI_MSIX_ENTRY_VECTOR_CTRL
;
698 entries
[i
].vector
= entry
->irq
;
699 irq_set_msi_desc(entry
->irq
, entry
);
700 entry
->masked
= readl(entry
->mask_base
+ offset
);
701 msix_mask_irq(entry
, 1);
707 * msix_capability_init - configure device's MSI-X capability
708 * @dev: pointer to the pci_dev data structure of MSI-X device function
709 * @entries: pointer to an array of struct msix_entry entries
710 * @nvec: number of @entries
712 * Setup the MSI-X capability structure of device function with a
713 * single MSI-X irq. A return of zero indicates the successful setup of
714 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
716 static int msix_capability_init(struct pci_dev
*dev
,
717 struct msix_entry
*entries
, int nvec
)
723 /* Ensure MSI-X is disabled while it is set up */
724 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
726 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
727 /* Request & Map MSI-X table region */
728 base
= msix_map_region(dev
, msix_table_size(control
));
732 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
736 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
741 * Some devices require MSI-X to be enabled before we can touch the
742 * MSI-X registers. We need to mask all the vectors to prevent
743 * interrupts coming in before they're fully set up.
745 msix_clear_and_set_ctrl(dev
, 0,
746 PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
);
748 msix_program_entries(dev
, entries
);
750 ret
= populate_msi_sysfs(dev
);
754 /* Set MSI-X enabled bits and unmask the function */
755 pci_intx_for_msi(dev
, 0);
756 dev
->msix_enabled
= 1;
758 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
765 * If we had some success, report the number of irqs
766 * we succeeded in setting up.
768 struct msi_desc
*entry
;
771 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
786 * pci_msi_supported - check whether MSI may be enabled on a device
787 * @dev: pointer to the pci_dev data structure of MSI device function
788 * @nvec: how many MSIs have been requested ?
790 * Look at global flags, the device itself, and its parent buses
791 * to determine if MSI/-X are supported for the device. If MSI/-X is
792 * supported return 1, else return 0.
794 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
798 /* MSI must be globally enabled and supported by the device */
802 if (!dev
|| dev
->no_msi
|| dev
->current_state
!= PCI_D0
)
806 * You can't ask to have 0 or less MSIs configured.
808 * b) the list manipulation code assumes nvec >= 1.
814 * Any bridge which does NOT route MSI transactions from its
815 * secondary bus to its primary bus must set NO_MSI flag on
816 * the secondary pci_bus.
817 * We expect only arch-specific PCI host bus controller driver
818 * or quirks for specific PCI bridges to be setting NO_MSI.
820 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
821 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
828 * pci_msi_vec_count - Return the number of MSI vectors a device can send
829 * @dev: device to report about
831 * This function returns the number of MSI vectors a device requested via
832 * Multiple Message Capable register. It returns a negative errno if the
833 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
834 * and returns a power of two, up to a maximum of 2^5 (32), according to the
837 int pci_msi_vec_count(struct pci_dev
*dev
)
845 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
846 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
850 EXPORT_SYMBOL(pci_msi_vec_count
);
852 void pci_msi_shutdown(struct pci_dev
*dev
)
854 struct msi_desc
*desc
;
857 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
860 BUG_ON(list_empty(&dev
->msi_list
));
861 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
863 msi_set_enable(dev
, 0);
864 pci_intx_for_msi(dev
, 1);
865 dev
->msi_enabled
= 0;
867 /* Return the device with MSI unmasked as initial states */
868 mask
= msi_mask(desc
->msi_attrib
.multi_cap
);
869 /* Keep cached state to be restored */
870 arch_msi_mask_irq(desc
, mask
, ~mask
);
872 /* Restore dev->irq to its default pin-assertion irq */
873 dev
->irq
= desc
->msi_attrib
.default_irq
;
876 void pci_disable_msi(struct pci_dev
*dev
)
878 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
881 pci_msi_shutdown(dev
);
884 EXPORT_SYMBOL(pci_disable_msi
);
887 * pci_msix_vec_count - return the number of device's MSI-X table entries
888 * @dev: pointer to the pci_dev data structure of MSI-X device function
889 * This function returns the number of device's MSI-X table entries and
890 * therefore the number of MSI-X vectors device is capable of sending.
891 * It returns a negative errno if the device is not capable of sending MSI-X
894 int pci_msix_vec_count(struct pci_dev
*dev
)
901 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
902 return msix_table_size(control
);
904 EXPORT_SYMBOL(pci_msix_vec_count
);
907 * pci_enable_msix - configure device's MSI-X capability structure
908 * @dev: pointer to the pci_dev data structure of MSI-X device function
909 * @entries: pointer to an array of MSI-X entries
910 * @nvec: number of MSI-X irqs requested for allocation by device driver
912 * Setup the MSI-X capability structure of device function with the number
913 * of requested irqs upon its software driver call to request for
914 * MSI-X mode enabled on its hardware device function. A return of zero
915 * indicates the successful configuration of MSI-X capability structure
916 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
917 * Or a return of > 0 indicates that driver request is exceeding the number
918 * of irqs or MSI-X vectors available. Driver should use the returned value to
919 * re-send its request.
921 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
926 if (!pci_msi_supported(dev
, nvec
))
932 nr_entries
= pci_msix_vec_count(dev
);
935 if (nvec
> nr_entries
)
938 /* Check for any invalid entries */
939 for (i
= 0; i
< nvec
; i
++) {
940 if (entries
[i
].entry
>= nr_entries
)
941 return -EINVAL
; /* invalid entry */
942 for (j
= i
+ 1; j
< nvec
; j
++) {
943 if (entries
[i
].entry
== entries
[j
].entry
)
944 return -EINVAL
; /* duplicate entry */
947 WARN_ON(!!dev
->msix_enabled
);
949 /* Check whether driver already requested for MSI irq */
950 if (dev
->msi_enabled
) {
951 dev_info(&dev
->dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
954 return msix_capability_init(dev
, entries
, nvec
);
956 EXPORT_SYMBOL(pci_enable_msix
);
958 void pci_msix_shutdown(struct pci_dev
*dev
)
960 struct msi_desc
*entry
;
962 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
965 /* Return the device with MSI-X masked as initial states */
966 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
967 /* Keep cached states to be restored */
968 arch_msix_mask_irq(entry
, 1);
971 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
972 pci_intx_for_msi(dev
, 1);
973 dev
->msix_enabled
= 0;
976 void pci_disable_msix(struct pci_dev
*dev
)
978 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
981 pci_msix_shutdown(dev
);
984 EXPORT_SYMBOL(pci_disable_msix
);
986 void pci_no_msi(void)
992 * pci_msi_enabled - is MSI enabled?
994 * Returns true if MSI has not been disabled by the command-line option
997 int pci_msi_enabled(void)
999 return pci_msi_enable
;
1001 EXPORT_SYMBOL(pci_msi_enabled
);
1003 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
1005 INIT_LIST_HEAD(&dev
->msi_list
);
1007 /* Disable the msi hardware to avoid screaming interrupts
1008 * during boot. This is the power on reset default so
1009 * usually this should be a noop.
1011 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1013 msi_set_enable(dev
, 0);
1015 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1017 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1021 * pci_enable_msi_range - configure device's MSI capability structure
1022 * @dev: device to configure
1023 * @minvec: minimal number of interrupts to configure
1024 * @maxvec: maximum number of interrupts to configure
1026 * This function tries to allocate a maximum possible number of interrupts in a
1027 * range between @minvec and @maxvec. It returns a negative errno if an error
1028 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1029 * and updates the @dev's irq member to the lowest new interrupt number;
1030 * the other interrupt numbers allocated to this device are consecutive.
1032 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
)
1037 if (!pci_msi_supported(dev
, minvec
))
1040 WARN_ON(!!dev
->msi_enabled
);
1042 /* Check whether driver already requested MSI-X irqs */
1043 if (dev
->msix_enabled
) {
1045 "can't enable MSI (MSI-X already enabled)\n");
1049 if (maxvec
< minvec
)
1052 nvec
= pci_msi_vec_count(dev
);
1055 else if (nvec
< minvec
)
1057 else if (nvec
> maxvec
)
1061 rc
= msi_capability_init(dev
, nvec
);
1064 } else if (rc
> 0) {
1073 EXPORT_SYMBOL(pci_enable_msi_range
);
1076 * pci_enable_msix_range - configure device's MSI-X capability structure
1077 * @dev: pointer to the pci_dev data structure of MSI-X device function
1078 * @entries: pointer to an array of MSI-X entries
1079 * @minvec: minimum number of MSI-X irqs requested
1080 * @maxvec: maximum number of MSI-X irqs requested
1082 * Setup the MSI-X capability structure of device function with a maximum
1083 * possible number of interrupts in the range between @minvec and @maxvec
1084 * upon its software driver call to request for MSI-X mode enabled on its
1085 * hardware device function. It returns a negative errno if an error occurs.
1086 * If it succeeds, it returns the actual number of interrupts allocated and
1087 * indicates the successful configuration of MSI-X capability structure
1088 * with new allocated MSI-X interrupts.
1090 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1091 int minvec
, int maxvec
)
1096 if (maxvec
< minvec
)
1100 rc
= pci_enable_msix(dev
, entries
, nvec
);
1103 } else if (rc
> 0) {
1112 EXPORT_SYMBOL(pci_enable_msix_range
);