3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/irqdomain.h>
26 static int pci_msi_enable
= 1;
27 int pci_msi_ignore_mask
;
29 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
31 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
32 static struct irq_domain
*pci_msi_default_domain
;
33 static DEFINE_MUTEX(pci_msi_domain_lock
);
35 struct irq_domain
* __weak
arch_get_pci_msi_domain(struct pci_dev
*dev
)
37 return pci_msi_default_domain
;
40 static struct irq_domain
*pci_msi_get_domain(struct pci_dev
*dev
)
42 struct irq_domain
*domain
= NULL
;
45 domain
= dev
->bus
->msi
->domain
;
47 domain
= arch_get_pci_msi_domain(dev
);
52 static int pci_msi_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
54 struct irq_domain
*domain
;
56 domain
= pci_msi_get_domain(dev
);
58 return pci_msi_domain_alloc_irqs(domain
, dev
, nvec
, type
);
60 return arch_setup_msi_irqs(dev
, nvec
, type
);
63 static void pci_msi_teardown_msi_irqs(struct pci_dev
*dev
)
65 struct irq_domain
*domain
;
67 domain
= pci_msi_get_domain(dev
);
69 pci_msi_domain_free_irqs(domain
, dev
);
71 arch_teardown_msi_irqs(dev
);
74 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
75 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
80 struct msi_controller
* __weak
pcibios_msi_controller(struct pci_dev
*dev
)
85 static struct msi_controller
*pci_msi_controller(struct pci_dev
*dev
)
87 struct msi_controller
*msi_ctrl
= dev
->bus
->msi
;
92 return pcibios_msi_controller(dev
);
95 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
97 struct msi_controller
*chip
= pci_msi_controller(dev
);
100 if (!chip
|| !chip
->setup_irq
)
103 err
= chip
->setup_irq(chip
, dev
, desc
);
107 irq_set_chip_data(desc
->irq
, chip
);
112 void __weak
arch_teardown_msi_irq(unsigned int irq
)
114 struct msi_controller
*chip
= irq_get_chip_data(irq
);
116 if (!chip
|| !chip
->teardown_irq
)
119 chip
->teardown_irq(chip
, irq
);
122 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
124 struct msi_desc
*entry
;
128 * If an architecture wants to support multiple MSI, it needs to
129 * override arch_setup_msi_irqs()
131 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
134 for_each_pci_msi_entry(entry
, dev
) {
135 ret
= arch_setup_msi_irq(dev
, entry
);
146 * We have a default implementation available as a separate non-weak
147 * function, as it is used by the Xen x86 PCI code
149 void default_teardown_msi_irqs(struct pci_dev
*dev
)
152 struct msi_desc
*entry
;
154 for_each_pci_msi_entry(entry
, dev
)
156 for (i
= 0; i
< entry
->nvec_used
; i
++)
157 arch_teardown_msi_irq(entry
->irq
+ i
);
160 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
162 return default_teardown_msi_irqs(dev
);
165 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
167 struct msi_desc
*entry
;
170 if (dev
->msix_enabled
) {
171 for_each_pci_msi_entry(entry
, dev
) {
172 if (irq
== entry
->irq
)
175 } else if (dev
->msi_enabled
) {
176 entry
= irq_get_msi_desc(irq
);
180 __pci_write_msi_msg(entry
, &entry
->msg
);
183 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
185 return default_restore_msi_irqs(dev
);
188 static inline __attribute_const__ u32
msi_mask(unsigned x
)
190 /* Don't shift by >= width of type */
193 return (1 << (1 << x
)) - 1;
197 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
198 * mask all MSI interrupts by clearing the MSI enable bit does not work
199 * reliably as devices without an INTx disable bit will then generate a
200 * level IRQ which will never be cleared.
202 u32
__pci_msi_desc_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
204 u32 mask_bits
= desc
->masked
;
206 if (pci_msi_ignore_mask
|| !desc
->msi_attrib
.maskbit
)
211 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
216 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
218 desc
->masked
= __pci_msi_desc_mask_irq(desc
, mask
, flag
);
222 * This internal function does not flush PCI writes to the device.
223 * All users must ensure that they read from the device before either
224 * assuming that the device state is up to date, or returning out of this
225 * file. This saves a few milliseconds when initialising devices with lots
226 * of MSI-X interrupts.
228 u32
__pci_msix_desc_mask_irq(struct msi_desc
*desc
, u32 flag
)
230 u32 mask_bits
= desc
->masked
;
231 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
232 PCI_MSIX_ENTRY_VECTOR_CTRL
;
234 if (pci_msi_ignore_mask
)
237 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
239 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
240 writel(mask_bits
, desc
->mask_base
+ offset
);
245 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
247 desc
->masked
= __pci_msix_desc_mask_irq(desc
, flag
);
250 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
252 struct msi_desc
*desc
= irq_data_get_msi_desc(data
);
254 if (desc
->msi_attrib
.is_msix
) {
255 msix_mask_irq(desc
, flag
);
256 readl(desc
->mask_base
); /* Flush write to device */
258 unsigned offset
= data
->irq
- desc
->irq
;
259 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
264 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
265 * @data: pointer to irqdata associated to that interrupt
267 void pci_msi_mask_irq(struct irq_data
*data
)
269 msi_set_mask_bit(data
, 1);
273 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
274 * @data: pointer to irqdata associated to that interrupt
276 void pci_msi_unmask_irq(struct irq_data
*data
)
278 msi_set_mask_bit(data
, 0);
281 void default_restore_msi_irqs(struct pci_dev
*dev
)
283 struct msi_desc
*entry
;
285 for_each_pci_msi_entry(entry
, dev
)
286 default_restore_msi_irq(dev
, entry
->irq
);
289 void __pci_read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
291 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
293 if (entry
->msi_attrib
.is_msix
) {
294 void __iomem
*base
= entry
->mask_base
+
295 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
297 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
298 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
299 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
301 struct pci_dev
*dev
= entry
->dev
;
302 int pos
= dev
->msi_cap
;
305 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
307 if (entry
->msi_attrib
.is_64
) {
308 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
310 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
313 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
319 void __pci_write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
321 if (entry
->dev
->current_state
!= PCI_D0
) {
322 /* Don't touch the hardware now */
323 } else if (entry
->msi_attrib
.is_msix
) {
325 base
= entry
->mask_base
+
326 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
328 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
329 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
330 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
332 struct pci_dev
*dev
= entry
->dev
;
333 int pos
= dev
->msi_cap
;
336 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
337 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
338 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
339 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
341 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
343 if (entry
->msi_attrib
.is_64
) {
344 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
346 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
349 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
356 void pci_write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
358 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
360 __pci_write_msi_msg(entry
, msg
);
362 EXPORT_SYMBOL_GPL(pci_write_msi_msg
);
364 static void free_msi_irqs(struct pci_dev
*dev
)
366 struct list_head
*msi_list
= dev_to_msi_list(&dev
->dev
);
367 struct msi_desc
*entry
, *tmp
;
368 struct attribute
**msi_attrs
;
369 struct device_attribute
*dev_attr
;
372 for_each_pci_msi_entry(entry
, dev
)
374 for (i
= 0; i
< entry
->nvec_used
; i
++)
375 BUG_ON(irq_has_action(entry
->irq
+ i
));
377 pci_msi_teardown_msi_irqs(dev
);
379 list_for_each_entry_safe(entry
, tmp
, msi_list
, list
) {
380 if (entry
->msi_attrib
.is_msix
) {
381 if (list_is_last(&entry
->list
, msi_list
))
382 iounmap(entry
->mask_base
);
385 list_del(&entry
->list
);
389 if (dev
->msi_irq_groups
) {
390 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
391 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
392 while (msi_attrs
[count
]) {
393 dev_attr
= container_of(msi_attrs
[count
],
394 struct device_attribute
, attr
);
395 kfree(dev_attr
->attr
.name
);
400 kfree(dev
->msi_irq_groups
[0]);
401 kfree(dev
->msi_irq_groups
);
402 dev
->msi_irq_groups
= NULL
;
406 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
408 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
412 INIT_LIST_HEAD(&desc
->list
);
418 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
420 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
421 pci_intx(dev
, enable
);
424 static void __pci_restore_msi_state(struct pci_dev
*dev
)
427 struct msi_desc
*entry
;
429 if (!dev
->msi_enabled
)
432 entry
= irq_get_msi_desc(dev
->irq
);
434 pci_intx_for_msi(dev
, 0);
435 pci_msi_set_enable(dev
, 0);
436 arch_restore_msi_irqs(dev
);
438 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
439 msi_mask_irq(entry
, msi_mask(entry
->msi_attrib
.multi_cap
),
441 control
&= ~PCI_MSI_FLAGS_QSIZE
;
442 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
443 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
446 static void __pci_restore_msix_state(struct pci_dev
*dev
)
448 struct msi_desc
*entry
;
450 if (!dev
->msix_enabled
)
452 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
454 /* route the table */
455 pci_intx_for_msi(dev
, 0);
456 pci_msix_clear_and_set_ctrl(dev
, 0,
457 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
459 arch_restore_msi_irqs(dev
);
460 for_each_pci_msi_entry(entry
, dev
)
461 msix_mask_irq(entry
, entry
->masked
);
463 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
466 void pci_restore_msi_state(struct pci_dev
*dev
)
468 __pci_restore_msi_state(dev
);
469 __pci_restore_msix_state(dev
);
471 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
473 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
476 struct msi_desc
*entry
;
480 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
484 entry
= irq_get_msi_desc(irq
);
486 return sprintf(buf
, "%s\n",
487 entry
->msi_attrib
.is_msix
? "msix" : "msi");
492 static int populate_msi_sysfs(struct pci_dev
*pdev
)
494 struct attribute
**msi_attrs
;
495 struct attribute
*msi_attr
;
496 struct device_attribute
*msi_dev_attr
;
497 struct attribute_group
*msi_irq_group
;
498 const struct attribute_group
**msi_irq_groups
;
499 struct msi_desc
*entry
;
504 /* Determine how many msi entries we have */
505 for_each_pci_msi_entry(entry
, pdev
)
510 /* Dynamically create the MSI attributes for the PCI device */
511 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
514 for_each_pci_msi_entry(entry
, pdev
) {
515 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
518 msi_attrs
[count
] = &msi_dev_attr
->attr
;
520 sysfs_attr_init(&msi_dev_attr
->attr
);
521 msi_dev_attr
->attr
.name
= kasprintf(GFP_KERNEL
, "%d",
523 if (!msi_dev_attr
->attr
.name
)
525 msi_dev_attr
->attr
.mode
= S_IRUGO
;
526 msi_dev_attr
->show
= msi_mode_show
;
530 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
533 msi_irq_group
->name
= "msi_irqs";
534 msi_irq_group
->attrs
= msi_attrs
;
536 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
538 goto error_irq_group
;
539 msi_irq_groups
[0] = msi_irq_group
;
541 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
543 goto error_irq_groups
;
544 pdev
->msi_irq_groups
= msi_irq_groups
;
549 kfree(msi_irq_groups
);
551 kfree(msi_irq_group
);
554 msi_attr
= msi_attrs
[count
];
556 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
557 kfree(msi_attr
->name
);
560 msi_attr
= msi_attrs
[count
];
566 static struct msi_desc
*msi_setup_entry(struct pci_dev
*dev
, int nvec
)
569 struct msi_desc
*entry
;
571 /* MSI Entry Initialization */
572 entry
= alloc_msi_entry(dev
);
576 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
578 entry
->msi_attrib
.is_msix
= 0;
579 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
580 entry
->msi_attrib
.entry_nr
= 0;
581 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
582 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
583 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
584 entry
->msi_attrib
.multiple
= ilog2(__roundup_pow_of_two(nvec
));
585 entry
->nvec_used
= nvec
;
587 if (control
& PCI_MSI_FLAGS_64BIT
)
588 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
590 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
592 /* Save the initial mask status */
593 if (entry
->msi_attrib
.maskbit
)
594 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
599 static int msi_verify_entries(struct pci_dev
*dev
)
601 struct msi_desc
*entry
;
603 for_each_pci_msi_entry(entry
, dev
) {
604 if (!dev
->no_64bit_msi
|| !entry
->msg
.address_hi
)
606 dev_err(&dev
->dev
, "Device has broken 64-bit MSI but arch"
607 " tried to assign one above 4G\n");
614 * msi_capability_init - configure device's MSI capability structure
615 * @dev: pointer to the pci_dev data structure of MSI device function
616 * @nvec: number of interrupts to allocate
618 * Setup the MSI capability structure of the device with the requested
619 * number of interrupts. A return value of zero indicates the successful
620 * setup of an entry with the new MSI irq. A negative return value indicates
621 * an error, and a positive return value indicates the number of interrupts
622 * which could have been allocated.
624 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
626 struct msi_desc
*entry
;
630 pci_msi_set_enable(dev
, 0); /* Disable MSI during set up */
632 entry
= msi_setup_entry(dev
, nvec
);
636 /* All MSIs are unmasked by default, Mask them all */
637 mask
= msi_mask(entry
->msi_attrib
.multi_cap
);
638 msi_mask_irq(entry
, mask
, mask
);
640 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
642 /* Configure MSI capability structure */
643 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
645 msi_mask_irq(entry
, mask
, ~mask
);
650 ret
= msi_verify_entries(dev
);
652 msi_mask_irq(entry
, mask
, ~mask
);
657 ret
= populate_msi_sysfs(dev
);
659 msi_mask_irq(entry
, mask
, ~mask
);
664 /* Set MSI enabled bits */
665 pci_intx_for_msi(dev
, 0);
666 pci_msi_set_enable(dev
, 1);
667 dev
->msi_enabled
= 1;
669 dev
->irq
= entry
->irq
;
673 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
675 resource_size_t phys_addr
;
680 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
682 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
683 flags
= pci_resource_flags(dev
, bir
);
684 if (!flags
|| (flags
& IORESOURCE_UNSET
))
687 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
688 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
690 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
693 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
694 struct msix_entry
*entries
, int nvec
)
696 struct msi_desc
*entry
;
699 for (i
= 0; i
< nvec
; i
++) {
700 entry
= alloc_msi_entry(dev
);
706 /* No enough memory. Don't try again */
710 entry
->msi_attrib
.is_msix
= 1;
711 entry
->msi_attrib
.is_64
= 1;
712 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
713 entry
->msi_attrib
.default_irq
= dev
->irq
;
714 entry
->mask_base
= base
;
715 entry
->nvec_used
= 1;
717 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
723 static void msix_program_entries(struct pci_dev
*dev
,
724 struct msix_entry
*entries
)
726 struct msi_desc
*entry
;
729 for_each_pci_msi_entry(entry
, dev
) {
730 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
731 PCI_MSIX_ENTRY_VECTOR_CTRL
;
733 entries
[i
].vector
= entry
->irq
;
734 entry
->masked
= readl(entry
->mask_base
+ offset
);
735 msix_mask_irq(entry
, 1);
741 * msix_capability_init - configure device's MSI-X capability
742 * @dev: pointer to the pci_dev data structure of MSI-X device function
743 * @entries: pointer to an array of struct msix_entry entries
744 * @nvec: number of @entries
746 * Setup the MSI-X capability structure of device function with a
747 * single MSI-X irq. A return of zero indicates the successful setup of
748 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
750 static int msix_capability_init(struct pci_dev
*dev
,
751 struct msix_entry
*entries
, int nvec
)
757 /* Ensure MSI-X is disabled while it is set up */
758 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
760 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
761 /* Request & Map MSI-X table region */
762 base
= msix_map_region(dev
, msix_table_size(control
));
766 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
770 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
774 /* Check if all MSI entries honor device restrictions */
775 ret
= msi_verify_entries(dev
);
780 * Some devices require MSI-X to be enabled before we can touch the
781 * MSI-X registers. We need to mask all the vectors to prevent
782 * interrupts coming in before they're fully set up.
784 pci_msix_clear_and_set_ctrl(dev
, 0,
785 PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
);
787 msix_program_entries(dev
, entries
);
789 ret
= populate_msi_sysfs(dev
);
793 /* Set MSI-X enabled bits and unmask the function */
794 pci_intx_for_msi(dev
, 0);
795 dev
->msix_enabled
= 1;
797 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
804 * If we had some success, report the number of irqs
805 * we succeeded in setting up.
807 struct msi_desc
*entry
;
810 for_each_pci_msi_entry(entry
, dev
) {
825 * pci_msi_supported - check whether MSI may be enabled on a device
826 * @dev: pointer to the pci_dev data structure of MSI device function
827 * @nvec: how many MSIs have been requested ?
829 * Look at global flags, the device itself, and its parent buses
830 * to determine if MSI/-X are supported for the device. If MSI/-X is
831 * supported return 1, else return 0.
833 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
837 /* MSI must be globally enabled and supported by the device */
841 if (!dev
|| dev
->no_msi
|| dev
->current_state
!= PCI_D0
)
845 * You can't ask to have 0 or less MSIs configured.
847 * b) the list manipulation code assumes nvec >= 1.
853 * Any bridge which does NOT route MSI transactions from its
854 * secondary bus to its primary bus must set NO_MSI flag on
855 * the secondary pci_bus.
856 * We expect only arch-specific PCI host bus controller driver
857 * or quirks for specific PCI bridges to be setting NO_MSI.
859 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
860 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
867 * pci_msi_vec_count - Return the number of MSI vectors a device can send
868 * @dev: device to report about
870 * This function returns the number of MSI vectors a device requested via
871 * Multiple Message Capable register. It returns a negative errno if the
872 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
873 * and returns a power of two, up to a maximum of 2^5 (32), according to the
876 int pci_msi_vec_count(struct pci_dev
*dev
)
884 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
885 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
889 EXPORT_SYMBOL(pci_msi_vec_count
);
891 void pci_msi_shutdown(struct pci_dev
*dev
)
893 struct msi_desc
*desc
;
896 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
899 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
900 desc
= first_msi_entry(dev
);
902 pci_msi_set_enable(dev
, 0);
903 pci_intx_for_msi(dev
, 1);
904 dev
->msi_enabled
= 0;
906 /* Return the device with MSI unmasked as initial states */
907 mask
= msi_mask(desc
->msi_attrib
.multi_cap
);
908 /* Keep cached state to be restored */
909 __pci_msi_desc_mask_irq(desc
, mask
, ~mask
);
911 /* Restore dev->irq to its default pin-assertion irq */
912 dev
->irq
= desc
->msi_attrib
.default_irq
;
915 void pci_disable_msi(struct pci_dev
*dev
)
917 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
920 pci_msi_shutdown(dev
);
923 EXPORT_SYMBOL(pci_disable_msi
);
926 * pci_msix_vec_count - return the number of device's MSI-X table entries
927 * @dev: pointer to the pci_dev data structure of MSI-X device function
928 * This function returns the number of device's MSI-X table entries and
929 * therefore the number of MSI-X vectors device is capable of sending.
930 * It returns a negative errno if the device is not capable of sending MSI-X
933 int pci_msix_vec_count(struct pci_dev
*dev
)
940 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
941 return msix_table_size(control
);
943 EXPORT_SYMBOL(pci_msix_vec_count
);
946 * pci_enable_msix - configure device's MSI-X capability structure
947 * @dev: pointer to the pci_dev data structure of MSI-X device function
948 * @entries: pointer to an array of MSI-X entries
949 * @nvec: number of MSI-X irqs requested for allocation by device driver
951 * Setup the MSI-X capability structure of device function with the number
952 * of requested irqs upon its software driver call to request for
953 * MSI-X mode enabled on its hardware device function. A return of zero
954 * indicates the successful configuration of MSI-X capability structure
955 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
956 * Or a return of > 0 indicates that driver request is exceeding the number
957 * of irqs or MSI-X vectors available. Driver should use the returned value to
958 * re-send its request.
960 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
965 if (!pci_msi_supported(dev
, nvec
))
971 nr_entries
= pci_msix_vec_count(dev
);
974 if (nvec
> nr_entries
)
977 /* Check for any invalid entries */
978 for (i
= 0; i
< nvec
; i
++) {
979 if (entries
[i
].entry
>= nr_entries
)
980 return -EINVAL
; /* invalid entry */
981 for (j
= i
+ 1; j
< nvec
; j
++) {
982 if (entries
[i
].entry
== entries
[j
].entry
)
983 return -EINVAL
; /* duplicate entry */
986 WARN_ON(!!dev
->msix_enabled
);
988 /* Check whether driver already requested for MSI irq */
989 if (dev
->msi_enabled
) {
990 dev_info(&dev
->dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
993 return msix_capability_init(dev
, entries
, nvec
);
995 EXPORT_SYMBOL(pci_enable_msix
);
997 void pci_msix_shutdown(struct pci_dev
*dev
)
999 struct msi_desc
*entry
;
1001 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1004 /* Return the device with MSI-X masked as initial states */
1005 for_each_pci_msi_entry(entry
, dev
) {
1006 /* Keep cached states to be restored */
1007 __pci_msix_desc_mask_irq(entry
, 1);
1010 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1011 pci_intx_for_msi(dev
, 1);
1012 dev
->msix_enabled
= 0;
1015 void pci_disable_msix(struct pci_dev
*dev
)
1017 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1020 pci_msix_shutdown(dev
);
1023 EXPORT_SYMBOL(pci_disable_msix
);
1025 void pci_no_msi(void)
1031 * pci_msi_enabled - is MSI enabled?
1033 * Returns true if MSI has not been disabled by the command-line option
1036 int pci_msi_enabled(void)
1038 return pci_msi_enable
;
1040 EXPORT_SYMBOL(pci_msi_enabled
);
1042 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
1044 INIT_LIST_HEAD(&dev
->msi_list
);
1048 * pci_enable_msi_range - configure device's MSI capability structure
1049 * @dev: device to configure
1050 * @minvec: minimal number of interrupts to configure
1051 * @maxvec: maximum number of interrupts to configure
1053 * This function tries to allocate a maximum possible number of interrupts in a
1054 * range between @minvec and @maxvec. It returns a negative errno if an error
1055 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1056 * and updates the @dev's irq member to the lowest new interrupt number;
1057 * the other interrupt numbers allocated to this device are consecutive.
1059 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
)
1064 if (!pci_msi_supported(dev
, minvec
))
1067 WARN_ON(!!dev
->msi_enabled
);
1069 /* Check whether driver already requested MSI-X irqs */
1070 if (dev
->msix_enabled
) {
1072 "can't enable MSI (MSI-X already enabled)\n");
1076 if (maxvec
< minvec
)
1079 nvec
= pci_msi_vec_count(dev
);
1082 else if (nvec
< minvec
)
1084 else if (nvec
> maxvec
)
1088 rc
= msi_capability_init(dev
, nvec
);
1091 } else if (rc
> 0) {
1100 EXPORT_SYMBOL(pci_enable_msi_range
);
1103 * pci_enable_msix_range - configure device's MSI-X capability structure
1104 * @dev: pointer to the pci_dev data structure of MSI-X device function
1105 * @entries: pointer to an array of MSI-X entries
1106 * @minvec: minimum number of MSI-X irqs requested
1107 * @maxvec: maximum number of MSI-X irqs requested
1109 * Setup the MSI-X capability structure of device function with a maximum
1110 * possible number of interrupts in the range between @minvec and @maxvec
1111 * upon its software driver call to request for MSI-X mode enabled on its
1112 * hardware device function. It returns a negative errno if an error occurs.
1113 * If it succeeds, it returns the actual number of interrupts allocated and
1114 * indicates the successful configuration of MSI-X capability structure
1115 * with new allocated MSI-X interrupts.
1117 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1118 int minvec
, int maxvec
)
1123 if (maxvec
< minvec
)
1127 rc
= pci_enable_msix(dev
, entries
, nvec
);
1130 } else if (rc
> 0) {
1139 EXPORT_SYMBOL(pci_enable_msix_range
);
1141 void *msi_desc_to_pci_sysdata(struct msi_desc
*desc
)
1143 struct pci_dev
*dev
= msi_desc_to_pci_dev(desc
);
1145 return dev
->bus
->sysdata
;
1147 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata
);
1149 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1151 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1152 * @irq_data: Pointer to interrupt data of the MSI interrupt
1153 * @msg: Pointer to the message
1155 void pci_msi_domain_write_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
1157 struct msi_desc
*desc
= irq_data_get_msi_desc(irq_data
);
1160 * For MSI-X desc->irq is always equal to irq_data->irq. For
1161 * MSI only the first interrupt of MULTI MSI passes the test.
1163 if (desc
->irq
== irq_data
->irq
)
1164 __pci_write_msi_msg(desc
, msg
);
1168 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1169 * @dev: Pointer to the PCI device
1170 * @desc: Pointer to the msi descriptor
1172 * The ID number is only used within the irqdomain.
1174 irq_hw_number_t
pci_msi_domain_calc_hwirq(struct pci_dev
*dev
,
1175 struct msi_desc
*desc
)
1177 return (irq_hw_number_t
)desc
->msi_attrib
.entry_nr
|
1178 PCI_DEVID(dev
->bus
->number
, dev
->devfn
) << 11 |
1179 (pci_domain_nr(dev
->bus
) & 0xFFFFFFFF) << 27;
1182 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc
*desc
)
1184 return !desc
->msi_attrib
.is_msix
&& desc
->nvec_used
> 1;
1188 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1189 * @domain: The interrupt domain to check
1190 * @info: The domain info for verification
1191 * @dev: The device to check
1194 * 0 if the functionality is supported
1195 * 1 if Multi MSI is requested, but the domain does not support it
1196 * -ENOTSUPP otherwise
1198 int pci_msi_domain_check_cap(struct irq_domain
*domain
,
1199 struct msi_domain_info
*info
, struct device
*dev
)
1201 struct msi_desc
*desc
= first_pci_msi_entry(to_pci_dev(dev
));
1203 /* Special handling to support pci_enable_msi_range() */
1204 if (pci_msi_desc_is_multi_msi(desc
) &&
1205 !(info
->flags
& MSI_FLAG_MULTI_PCI_MSI
))
1207 else if (desc
->msi_attrib
.is_msix
&& !(info
->flags
& MSI_FLAG_PCI_MSIX
))
1213 static int pci_msi_domain_handle_error(struct irq_domain
*domain
,
1214 struct msi_desc
*desc
, int error
)
1216 /* Special handling to support pci_enable_msi_range() */
1217 if (pci_msi_desc_is_multi_msi(desc
) && error
== -ENOSPC
)
1223 #ifdef GENERIC_MSI_DOMAIN_OPS
1224 static void pci_msi_domain_set_desc(msi_alloc_info_t
*arg
,
1225 struct msi_desc
*desc
)
1228 arg
->hwirq
= pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc
),
1232 #define pci_msi_domain_set_desc NULL
1235 static struct msi_domain_ops pci_msi_domain_ops_default
= {
1236 .set_desc
= pci_msi_domain_set_desc
,
1237 .msi_check
= pci_msi_domain_check_cap
,
1238 .handle_error
= pci_msi_domain_handle_error
,
1241 static void pci_msi_domain_update_dom_ops(struct msi_domain_info
*info
)
1243 struct msi_domain_ops
*ops
= info
->ops
;
1246 info
->ops
= &pci_msi_domain_ops_default
;
1248 if (ops
->set_desc
== NULL
)
1249 ops
->set_desc
= pci_msi_domain_set_desc
;
1250 if (ops
->msi_check
== NULL
)
1251 ops
->msi_check
= pci_msi_domain_check_cap
;
1252 if (ops
->handle_error
== NULL
)
1253 ops
->handle_error
= pci_msi_domain_handle_error
;
1257 static void pci_msi_domain_update_chip_ops(struct msi_domain_info
*info
)
1259 struct irq_chip
*chip
= info
->chip
;
1262 if (!chip
->irq_write_msi_msg
)
1263 chip
->irq_write_msi_msg
= pci_msi_domain_write_msg
;
1267 * pci_msi_create_irq_domain - Creat a MSI interrupt domain
1268 * @node: Optional device-tree node of the interrupt controller
1269 * @info: MSI domain info
1270 * @parent: Parent irq domain
1272 * Updates the domain and chip ops and creates a MSI interrupt domain.
1275 * A domain pointer or NULL in case of failure.
1277 struct irq_domain
*pci_msi_create_irq_domain(struct device_node
*node
,
1278 struct msi_domain_info
*info
,
1279 struct irq_domain
*parent
)
1281 if (info
->flags
& MSI_FLAG_USE_DEF_DOM_OPS
)
1282 pci_msi_domain_update_dom_ops(info
);
1283 if (info
->flags
& MSI_FLAG_USE_DEF_CHIP_OPS
)
1284 pci_msi_domain_update_chip_ops(info
);
1286 return msi_create_irq_domain(node
, info
, parent
);
1290 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1291 * @domain: The interrupt domain to allocate from
1292 * @dev: The device for which to allocate
1293 * @nvec: The number of interrupts to allocate
1294 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1297 * A virtual interrupt number or an error code in case of failure
1299 int pci_msi_domain_alloc_irqs(struct irq_domain
*domain
, struct pci_dev
*dev
,
1302 return msi_domain_alloc_irqs(domain
, &dev
->dev
, nvec
);
1306 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1307 * @domain: The interrupt domain
1308 * @dev: The device for which to free interrupts
1310 void pci_msi_domain_free_irqs(struct irq_domain
*domain
, struct pci_dev
*dev
)
1312 msi_domain_free_irqs(domain
, &dev
->dev
);
1316 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1317 * @node: Optional device-tree node of the interrupt controller
1318 * @info: MSI domain info
1319 * @parent: Parent irq domain
1321 * Returns: A domain pointer or NULL in case of failure. If successful
1322 * the default PCI/MSI irqdomain pointer is updated.
1324 struct irq_domain
*pci_msi_create_default_irq_domain(struct device_node
*node
,
1325 struct msi_domain_info
*info
, struct irq_domain
*parent
)
1327 struct irq_domain
*domain
;
1329 mutex_lock(&pci_msi_domain_lock
);
1330 if (pci_msi_default_domain
) {
1331 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1334 domain
= pci_msi_create_irq_domain(node
, info
, parent
);
1335 pci_msi_default_domain
= domain
;
1337 mutex_unlock(&pci_msi_domain_lock
);
1341 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */