3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
25 static int pci_msi_enable
= 1;
26 int pci_msi_ignore_mask
;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 struct msi_controller
* __weak
pcibios_msi_controller(struct pci_dev
*dev
)
38 static struct msi_controller
*pci_msi_controller(struct pci_dev
*dev
)
40 struct msi_controller
*msi_ctrl
= dev
->bus
->msi
;
45 return pcibios_msi_controller(dev
);
48 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
50 struct msi_controller
*chip
= pci_msi_controller(dev
);
53 if (!chip
|| !chip
->setup_irq
)
56 err
= chip
->setup_irq(chip
, dev
, desc
);
60 irq_set_chip_data(desc
->irq
, chip
);
65 void __weak
arch_teardown_msi_irq(unsigned int irq
)
67 struct msi_controller
*chip
= irq_get_chip_data(irq
);
69 if (!chip
|| !chip
->teardown_irq
)
72 chip
->teardown_irq(chip
, irq
);
75 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
77 struct msi_desc
*entry
;
81 * If an architecture wants to support multiple MSI, it needs to
82 * override arch_setup_msi_irqs()
84 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
87 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
88 ret
= arch_setup_msi_irq(dev
, entry
);
99 * We have a default implementation available as a separate non-weak
100 * function, as it is used by the Xen x86 PCI code
102 void default_teardown_msi_irqs(struct pci_dev
*dev
)
104 struct msi_desc
*entry
;
106 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
110 if (entry
->nvec_used
)
111 nvec
= entry
->nvec_used
;
113 nvec
= 1 << entry
->msi_attrib
.multiple
;
114 for (i
= 0; i
< nvec
; i
++)
115 arch_teardown_msi_irq(entry
->irq
+ i
);
119 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
121 return default_teardown_msi_irqs(dev
);
124 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
126 struct msi_desc
*entry
;
129 if (dev
->msix_enabled
) {
130 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
131 if (irq
== entry
->irq
)
134 } else if (dev
->msi_enabled
) {
135 entry
= irq_get_msi_desc(irq
);
139 __write_msi_msg(entry
, &entry
->msg
);
142 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
144 return default_restore_msi_irqs(dev
);
147 static void msi_set_enable(struct pci_dev
*dev
, int enable
)
151 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
152 control
&= ~PCI_MSI_FLAGS_ENABLE
;
154 control
|= PCI_MSI_FLAGS_ENABLE
;
155 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
158 static void msix_clear_and_set_ctrl(struct pci_dev
*dev
, u16 clear
, u16 set
)
162 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
165 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, ctrl
);
168 static inline __attribute_const__ u32
msi_mask(unsigned x
)
170 /* Don't shift by >= width of type */
173 return (1 << (1 << x
)) - 1;
177 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
178 * mask all MSI interrupts by clearing the MSI enable bit does not work
179 * reliably as devices without an INTx disable bit will then generate a
180 * level IRQ which will never be cleared.
182 u32
__msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
184 u32 mask_bits
= desc
->masked
;
186 if (pci_msi_ignore_mask
|| !desc
->msi_attrib
.maskbit
)
191 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
196 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
198 desc
->masked
= __msi_mask_irq(desc
, mask
, flag
);
202 * This internal function does not flush PCI writes to the device.
203 * All users must ensure that they read from the device before either
204 * assuming that the device state is up to date, or returning out of this
205 * file. This saves a few milliseconds when initialising devices with lots
206 * of MSI-X interrupts.
208 u32
__msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
210 u32 mask_bits
= desc
->masked
;
211 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
212 PCI_MSIX_ENTRY_VECTOR_CTRL
;
214 if (pci_msi_ignore_mask
)
217 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
219 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
220 writel(mask_bits
, desc
->mask_base
+ offset
);
225 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
227 desc
->masked
= __msix_mask_irq(desc
, flag
);
230 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
232 struct msi_desc
*desc
= irq_data_get_msi(data
);
234 if (desc
->msi_attrib
.is_msix
) {
235 msix_mask_irq(desc
, flag
);
236 readl(desc
->mask_base
); /* Flush write to device */
238 unsigned offset
= data
->irq
- desc
->irq
;
239 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
243 void mask_msi_irq(struct irq_data
*data
)
245 msi_set_mask_bit(data
, 1);
248 void unmask_msi_irq(struct irq_data
*data
)
250 msi_set_mask_bit(data
, 0);
253 void default_restore_msi_irqs(struct pci_dev
*dev
)
255 struct msi_desc
*entry
;
257 list_for_each_entry(entry
, &dev
->msi_list
, list
)
258 default_restore_msi_irq(dev
, entry
->irq
);
261 void __read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
263 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
265 if (entry
->msi_attrib
.is_msix
) {
266 void __iomem
*base
= entry
->mask_base
+
267 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
269 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
270 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
271 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
273 struct pci_dev
*dev
= entry
->dev
;
274 int pos
= dev
->msi_cap
;
277 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
279 if (entry
->msi_attrib
.is_64
) {
280 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
282 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
285 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
291 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
293 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
295 __read_msi_msg(entry
, msg
);
298 void __get_cached_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
300 /* Assert that the cache is valid, assuming that
301 * valid messages are not all-zeroes. */
302 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
308 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
310 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
312 __get_cached_msi_msg(entry
, msg
);
314 EXPORT_SYMBOL_GPL(get_cached_msi_msg
);
316 void __write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
318 if (entry
->dev
->current_state
!= PCI_D0
) {
319 /* Don't touch the hardware now */
320 } else if (entry
->msi_attrib
.is_msix
) {
322 base
= entry
->mask_base
+
323 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
325 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
326 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
327 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
329 struct pci_dev
*dev
= entry
->dev
;
330 int pos
= dev
->msi_cap
;
333 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
334 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
335 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
336 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
338 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
340 if (entry
->msi_attrib
.is_64
) {
341 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
343 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
346 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
353 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
355 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
357 __write_msi_msg(entry
, msg
);
359 EXPORT_SYMBOL_GPL(write_msi_msg
);
361 static void free_msi_irqs(struct pci_dev
*dev
)
363 struct msi_desc
*entry
, *tmp
;
364 struct attribute
**msi_attrs
;
365 struct device_attribute
*dev_attr
;
368 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
372 if (entry
->nvec_used
)
373 nvec
= entry
->nvec_used
;
375 nvec
= 1 << entry
->msi_attrib
.multiple
;
376 for (i
= 0; i
< nvec
; i
++)
377 BUG_ON(irq_has_action(entry
->irq
+ i
));
380 arch_teardown_msi_irqs(dev
);
382 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
383 if (entry
->msi_attrib
.is_msix
) {
384 if (list_is_last(&entry
->list
, &dev
->msi_list
))
385 iounmap(entry
->mask_base
);
388 list_del(&entry
->list
);
392 if (dev
->msi_irq_groups
) {
393 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
394 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
395 while (msi_attrs
[count
]) {
396 dev_attr
= container_of(msi_attrs
[count
],
397 struct device_attribute
, attr
);
398 kfree(dev_attr
->attr
.name
);
403 kfree(dev
->msi_irq_groups
[0]);
404 kfree(dev
->msi_irq_groups
);
405 dev
->msi_irq_groups
= NULL
;
409 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
411 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
415 INIT_LIST_HEAD(&desc
->list
);
421 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
423 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
424 pci_intx(dev
, enable
);
427 static void __pci_restore_msi_state(struct pci_dev
*dev
)
430 struct msi_desc
*entry
;
432 if (!dev
->msi_enabled
)
435 entry
= irq_get_msi_desc(dev
->irq
);
437 pci_intx_for_msi(dev
, 0);
438 msi_set_enable(dev
, 0);
439 arch_restore_msi_irqs(dev
);
441 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
442 msi_mask_irq(entry
, msi_mask(entry
->msi_attrib
.multi_cap
),
444 control
&= ~PCI_MSI_FLAGS_QSIZE
;
445 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
446 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
449 static void __pci_restore_msix_state(struct pci_dev
*dev
)
451 struct msi_desc
*entry
;
453 if (!dev
->msix_enabled
)
455 BUG_ON(list_empty(&dev
->msi_list
));
457 /* route the table */
458 pci_intx_for_msi(dev
, 0);
459 msix_clear_and_set_ctrl(dev
, 0,
460 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
462 arch_restore_msi_irqs(dev
);
463 list_for_each_entry(entry
, &dev
->msi_list
, list
)
464 msix_mask_irq(entry
, entry
->masked
);
466 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
469 void pci_restore_msi_state(struct pci_dev
*dev
)
471 __pci_restore_msi_state(dev
);
472 __pci_restore_msix_state(dev
);
474 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
476 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
479 struct msi_desc
*entry
;
483 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
487 entry
= irq_get_msi_desc(irq
);
489 return sprintf(buf
, "%s\n",
490 entry
->msi_attrib
.is_msix
? "msix" : "msi");
495 static int populate_msi_sysfs(struct pci_dev
*pdev
)
497 struct attribute
**msi_attrs
;
498 struct attribute
*msi_attr
;
499 struct device_attribute
*msi_dev_attr
;
500 struct attribute_group
*msi_irq_group
;
501 const struct attribute_group
**msi_irq_groups
;
502 struct msi_desc
*entry
;
507 /* Determine how many msi entries we have */
508 list_for_each_entry(entry
, &pdev
->msi_list
, list
)
513 /* Dynamically create the MSI attributes for the PCI device */
514 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
517 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
518 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
521 msi_attrs
[count
] = &msi_dev_attr
->attr
;
523 sysfs_attr_init(&msi_dev_attr
->attr
);
524 msi_dev_attr
->attr
.name
= kasprintf(GFP_KERNEL
, "%d",
526 if (!msi_dev_attr
->attr
.name
)
528 msi_dev_attr
->attr
.mode
= S_IRUGO
;
529 msi_dev_attr
->show
= msi_mode_show
;
533 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
536 msi_irq_group
->name
= "msi_irqs";
537 msi_irq_group
->attrs
= msi_attrs
;
539 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
541 goto error_irq_group
;
542 msi_irq_groups
[0] = msi_irq_group
;
544 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
546 goto error_irq_groups
;
547 pdev
->msi_irq_groups
= msi_irq_groups
;
552 kfree(msi_irq_groups
);
554 kfree(msi_irq_group
);
557 msi_attr
= msi_attrs
[count
];
559 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
560 kfree(msi_attr
->name
);
563 msi_attr
= msi_attrs
[count
];
569 static struct msi_desc
*msi_setup_entry(struct pci_dev
*dev
)
572 struct msi_desc
*entry
;
574 /* MSI Entry Initialization */
575 entry
= alloc_msi_entry(dev
);
579 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
581 entry
->msi_attrib
.is_msix
= 0;
582 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
583 entry
->msi_attrib
.entry_nr
= 0;
584 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
585 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
586 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
588 if (control
& PCI_MSI_FLAGS_64BIT
)
589 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
591 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
593 /* Save the initial mask status */
594 if (entry
->msi_attrib
.maskbit
)
595 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
601 * msi_capability_init - configure device's MSI capability structure
602 * @dev: pointer to the pci_dev data structure of MSI device function
603 * @nvec: number of interrupts to allocate
605 * Setup the MSI capability structure of the device with the requested
606 * number of interrupts. A return value of zero indicates the successful
607 * setup of an entry with the new MSI irq. A negative return value indicates
608 * an error, and a positive return value indicates the number of interrupts
609 * which could have been allocated.
611 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
613 struct msi_desc
*entry
;
617 msi_set_enable(dev
, 0); /* Disable MSI during set up */
619 entry
= msi_setup_entry(dev
);
623 /* All MSIs are unmasked by default, Mask them all */
624 mask
= msi_mask(entry
->msi_attrib
.multi_cap
);
625 msi_mask_irq(entry
, mask
, mask
);
627 list_add_tail(&entry
->list
, &dev
->msi_list
);
629 /* Configure MSI capability structure */
630 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
632 msi_mask_irq(entry
, mask
, ~mask
);
637 ret
= populate_msi_sysfs(dev
);
639 msi_mask_irq(entry
, mask
, ~mask
);
644 /* Set MSI enabled bits */
645 pci_intx_for_msi(dev
, 0);
646 msi_set_enable(dev
, 1);
647 dev
->msi_enabled
= 1;
649 dev
->irq
= entry
->irq
;
653 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
655 resource_size_t phys_addr
;
659 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
661 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
662 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
663 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
665 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
668 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
669 struct msix_entry
*entries
, int nvec
)
671 struct msi_desc
*entry
;
674 for (i
= 0; i
< nvec
; i
++) {
675 entry
= alloc_msi_entry(dev
);
681 /* No enough memory. Don't try again */
685 entry
->msi_attrib
.is_msix
= 1;
686 entry
->msi_attrib
.is_64
= 1;
687 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
688 entry
->msi_attrib
.default_irq
= dev
->irq
;
689 entry
->mask_base
= base
;
691 list_add_tail(&entry
->list
, &dev
->msi_list
);
697 static void msix_program_entries(struct pci_dev
*dev
,
698 struct msix_entry
*entries
)
700 struct msi_desc
*entry
;
703 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
704 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
705 PCI_MSIX_ENTRY_VECTOR_CTRL
;
707 entries
[i
].vector
= entry
->irq
;
708 irq_set_msi_desc(entry
->irq
, entry
);
709 entry
->masked
= readl(entry
->mask_base
+ offset
);
710 msix_mask_irq(entry
, 1);
716 * msix_capability_init - configure device's MSI-X capability
717 * @dev: pointer to the pci_dev data structure of MSI-X device function
718 * @entries: pointer to an array of struct msix_entry entries
719 * @nvec: number of @entries
721 * Setup the MSI-X capability structure of device function with a
722 * single MSI-X irq. A return of zero indicates the successful setup of
723 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
725 static int msix_capability_init(struct pci_dev
*dev
,
726 struct msix_entry
*entries
, int nvec
)
732 /* Ensure MSI-X is disabled while it is set up */
733 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
735 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
736 /* Request & Map MSI-X table region */
737 base
= msix_map_region(dev
, msix_table_size(control
));
741 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
745 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
750 * Some devices require MSI-X to be enabled before we can touch the
751 * MSI-X registers. We need to mask all the vectors to prevent
752 * interrupts coming in before they're fully set up.
754 msix_clear_and_set_ctrl(dev
, 0,
755 PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
);
757 msix_program_entries(dev
, entries
);
759 ret
= populate_msi_sysfs(dev
);
763 /* Set MSI-X enabled bits and unmask the function */
764 pci_intx_for_msi(dev
, 0);
765 dev
->msix_enabled
= 1;
767 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
774 * If we had some success, report the number of irqs
775 * we succeeded in setting up.
777 struct msi_desc
*entry
;
780 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
795 * pci_msi_supported - check whether MSI may be enabled on a device
796 * @dev: pointer to the pci_dev data structure of MSI device function
797 * @nvec: how many MSIs have been requested ?
799 * Look at global flags, the device itself, and its parent buses
800 * to determine if MSI/-X are supported for the device. If MSI/-X is
801 * supported return 1, else return 0.
803 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
807 /* MSI must be globally enabled and supported by the device */
811 if (!dev
|| dev
->no_msi
|| dev
->current_state
!= PCI_D0
)
815 * You can't ask to have 0 or less MSIs configured.
817 * b) the list manipulation code assumes nvec >= 1.
823 * Any bridge which does NOT route MSI transactions from its
824 * secondary bus to its primary bus must set NO_MSI flag on
825 * the secondary pci_bus.
826 * We expect only arch-specific PCI host bus controller driver
827 * or quirks for specific PCI bridges to be setting NO_MSI.
829 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
830 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
837 * pci_msi_vec_count - Return the number of MSI vectors a device can send
838 * @dev: device to report about
840 * This function returns the number of MSI vectors a device requested via
841 * Multiple Message Capable register. It returns a negative errno if the
842 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
843 * and returns a power of two, up to a maximum of 2^5 (32), according to the
846 int pci_msi_vec_count(struct pci_dev
*dev
)
854 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
855 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
859 EXPORT_SYMBOL(pci_msi_vec_count
);
861 void pci_msi_shutdown(struct pci_dev
*dev
)
863 struct msi_desc
*desc
;
866 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
869 BUG_ON(list_empty(&dev
->msi_list
));
870 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
872 msi_set_enable(dev
, 0);
873 pci_intx_for_msi(dev
, 1);
874 dev
->msi_enabled
= 0;
876 /* Return the device with MSI unmasked as initial states */
877 mask
= msi_mask(desc
->msi_attrib
.multi_cap
);
878 /* Keep cached state to be restored */
879 __msi_mask_irq(desc
, mask
, ~mask
);
881 /* Restore dev->irq to its default pin-assertion irq */
882 dev
->irq
= desc
->msi_attrib
.default_irq
;
885 void pci_disable_msi(struct pci_dev
*dev
)
887 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
890 pci_msi_shutdown(dev
);
893 EXPORT_SYMBOL(pci_disable_msi
);
896 * pci_msix_vec_count - return the number of device's MSI-X table entries
897 * @dev: pointer to the pci_dev data structure of MSI-X device function
898 * This function returns the number of device's MSI-X table entries and
899 * therefore the number of MSI-X vectors device is capable of sending.
900 * It returns a negative errno if the device is not capable of sending MSI-X
903 int pci_msix_vec_count(struct pci_dev
*dev
)
910 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
911 return msix_table_size(control
);
913 EXPORT_SYMBOL(pci_msix_vec_count
);
916 * pci_enable_msix - configure device's MSI-X capability structure
917 * @dev: pointer to the pci_dev data structure of MSI-X device function
918 * @entries: pointer to an array of MSI-X entries
919 * @nvec: number of MSI-X irqs requested for allocation by device driver
921 * Setup the MSI-X capability structure of device function with the number
922 * of requested irqs upon its software driver call to request for
923 * MSI-X mode enabled on its hardware device function. A return of zero
924 * indicates the successful configuration of MSI-X capability structure
925 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
926 * Or a return of > 0 indicates that driver request is exceeding the number
927 * of irqs or MSI-X vectors available. Driver should use the returned value to
928 * re-send its request.
930 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
935 if (!pci_msi_supported(dev
, nvec
))
941 nr_entries
= pci_msix_vec_count(dev
);
944 if (nvec
> nr_entries
)
947 /* Check for any invalid entries */
948 for (i
= 0; i
< nvec
; i
++) {
949 if (entries
[i
].entry
>= nr_entries
)
950 return -EINVAL
; /* invalid entry */
951 for (j
= i
+ 1; j
< nvec
; j
++) {
952 if (entries
[i
].entry
== entries
[j
].entry
)
953 return -EINVAL
; /* duplicate entry */
956 WARN_ON(!!dev
->msix_enabled
);
958 /* Check whether driver already requested for MSI irq */
959 if (dev
->msi_enabled
) {
960 dev_info(&dev
->dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
963 return msix_capability_init(dev
, entries
, nvec
);
965 EXPORT_SYMBOL(pci_enable_msix
);
967 void pci_msix_shutdown(struct pci_dev
*dev
)
969 struct msi_desc
*entry
;
971 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
974 /* Return the device with MSI-X masked as initial states */
975 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
976 /* Keep cached states to be restored */
977 __msix_mask_irq(entry
, 1);
980 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
981 pci_intx_for_msi(dev
, 1);
982 dev
->msix_enabled
= 0;
985 void pci_disable_msix(struct pci_dev
*dev
)
987 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
990 pci_msix_shutdown(dev
);
993 EXPORT_SYMBOL(pci_disable_msix
);
995 void pci_no_msi(void)
1001 * pci_msi_enabled - is MSI enabled?
1003 * Returns true if MSI has not been disabled by the command-line option
1006 int pci_msi_enabled(void)
1008 return pci_msi_enable
;
1010 EXPORT_SYMBOL(pci_msi_enabled
);
1012 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
1014 INIT_LIST_HEAD(&dev
->msi_list
);
1016 /* Disable the msi hardware to avoid screaming interrupts
1017 * during boot. This is the power on reset default so
1018 * usually this should be a noop.
1020 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1022 msi_set_enable(dev
, 0);
1024 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1026 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1030 * pci_enable_msi_range - configure device's MSI capability structure
1031 * @dev: device to configure
1032 * @minvec: minimal number of interrupts to configure
1033 * @maxvec: maximum number of interrupts to configure
1035 * This function tries to allocate a maximum possible number of interrupts in a
1036 * range between @minvec and @maxvec. It returns a negative errno if an error
1037 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1038 * and updates the @dev's irq member to the lowest new interrupt number;
1039 * the other interrupt numbers allocated to this device are consecutive.
1041 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
)
1046 if (!pci_msi_supported(dev
, minvec
))
1049 WARN_ON(!!dev
->msi_enabled
);
1051 /* Check whether driver already requested MSI-X irqs */
1052 if (dev
->msix_enabled
) {
1054 "can't enable MSI (MSI-X already enabled)\n");
1058 if (maxvec
< minvec
)
1061 nvec
= pci_msi_vec_count(dev
);
1064 else if (nvec
< minvec
)
1066 else if (nvec
> maxvec
)
1070 rc
= msi_capability_init(dev
, nvec
);
1073 } else if (rc
> 0) {
1082 EXPORT_SYMBOL(pci_enable_msi_range
);
1085 * pci_enable_msix_range - configure device's MSI-X capability structure
1086 * @dev: pointer to the pci_dev data structure of MSI-X device function
1087 * @entries: pointer to an array of MSI-X entries
1088 * @minvec: minimum number of MSI-X irqs requested
1089 * @maxvec: maximum number of MSI-X irqs requested
1091 * Setup the MSI-X capability structure of device function with a maximum
1092 * possible number of interrupts in the range between @minvec and @maxvec
1093 * upon its software driver call to request for MSI-X mode enabled on its
1094 * hardware device function. It returns a negative errno if an error occurs.
1095 * If it succeeds, it returns the actual number of interrupts allocated and
1096 * indicates the successful configuration of MSI-X capability structure
1097 * with new allocated MSI-X interrupts.
1099 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1100 int minvec
, int maxvec
)
1105 if (maxvec
< minvec
)
1109 rc
= pci_enable_msix(dev
, entries
, nvec
);
1112 } else if (rc
> 0) {
1121 EXPORT_SYMBOL(pci_enable_msix_range
);