3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
26 static int pci_msi_enable
= 1;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
35 struct msi_chip
*chip
= dev
->bus
->msi
;
38 if (!chip
|| !chip
->setup_irq
)
41 err
= chip
->setup_irq(chip
, dev
, desc
);
45 irq_set_chip_data(desc
->irq
, chip
);
50 void __weak
arch_teardown_msi_irq(unsigned int irq
)
52 struct msi_chip
*chip
= irq_get_chip_data(irq
);
54 if (!chip
|| !chip
->teardown_irq
)
57 chip
->teardown_irq(chip
, irq
);
60 int __weak
arch_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
62 struct msi_chip
*chip
= dev
->bus
->msi
;
64 if (!chip
|| !chip
->check_device
)
67 return chip
->check_device(chip
, dev
, nvec
, type
);
70 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
72 struct msi_desc
*entry
;
76 * If an architecture wants to support multiple MSI, it needs to
77 * override arch_setup_msi_irqs()
79 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
82 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
83 ret
= arch_setup_msi_irq(dev
, entry
);
94 * We have a default implementation available as a separate non-weak
95 * function, as it is used by the Xen x86 PCI code
97 void default_teardown_msi_irqs(struct pci_dev
*dev
)
99 struct msi_desc
*entry
;
101 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
105 if (entry
->nvec_used
)
106 nvec
= entry
->nvec_used
;
108 nvec
= 1 << entry
->msi_attrib
.multiple
;
109 for (i
= 0; i
< nvec
; i
++)
110 arch_teardown_msi_irq(entry
->irq
+ i
);
114 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
116 return default_teardown_msi_irqs(dev
);
119 void default_restore_msi_irqs(struct pci_dev
*dev
, int irq
)
121 struct msi_desc
*entry
;
124 if (dev
->msix_enabled
) {
125 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
126 if (irq
== entry
->irq
)
129 } else if (dev
->msi_enabled
) {
130 entry
= irq_get_msi_desc(irq
);
134 write_msi_msg(irq
, &entry
->msg
);
137 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
, int irq
)
139 return default_restore_msi_irqs(dev
, irq
);
142 static void msi_set_enable(struct pci_dev
*dev
, int enable
)
146 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
147 control
&= ~PCI_MSI_FLAGS_ENABLE
;
149 control
|= PCI_MSI_FLAGS_ENABLE
;
150 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
153 static void msix_set_enable(struct pci_dev
*dev
, int enable
)
157 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
158 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
160 control
|= PCI_MSIX_FLAGS_ENABLE
;
161 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
164 static inline __attribute_const__ u32
msi_mask(unsigned x
)
166 /* Don't shift by >= width of type */
169 return (1 << (1 << x
)) - 1;
172 static inline __attribute_const__ u32
msi_capable_mask(u16 control
)
174 return msi_mask((control
>> 1) & 7);
177 static inline __attribute_const__ u32
msi_enabled_mask(u16 control
)
179 return msi_mask((control
>> 4) & 7);
183 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
184 * mask all MSI interrupts by clearing the MSI enable bit does not work
185 * reliably as devices without an INTx disable bit will then generate a
186 * level IRQ which will never be cleared.
188 u32
default_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
190 u32 mask_bits
= desc
->masked
;
192 if (!desc
->msi_attrib
.maskbit
)
197 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
202 __weak u32
arch_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
204 return default_msi_mask_irq(desc
, mask
, flag
);
207 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
209 desc
->masked
= arch_msi_mask_irq(desc
, mask
, flag
);
213 * This internal function does not flush PCI writes to the device.
214 * All users must ensure that they read from the device before either
215 * assuming that the device state is up to date, or returning out of this
216 * file. This saves a few milliseconds when initialising devices with lots
217 * of MSI-X interrupts.
219 u32
default_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
221 u32 mask_bits
= desc
->masked
;
222 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
223 PCI_MSIX_ENTRY_VECTOR_CTRL
;
224 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
226 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
227 writel(mask_bits
, desc
->mask_base
+ offset
);
232 __weak u32
arch_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
234 return default_msix_mask_irq(desc
, flag
);
237 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
239 desc
->masked
= arch_msix_mask_irq(desc
, flag
);
242 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
244 struct msi_desc
*desc
= irq_data_get_msi(data
);
246 if (desc
->msi_attrib
.is_msix
) {
247 msix_mask_irq(desc
, flag
);
248 readl(desc
->mask_base
); /* Flush write to device */
250 unsigned offset
= data
->irq
- desc
->dev
->irq
;
251 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
255 void mask_msi_irq(struct irq_data
*data
)
257 msi_set_mask_bit(data
, 1);
260 void unmask_msi_irq(struct irq_data
*data
)
262 msi_set_mask_bit(data
, 0);
265 void __read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
267 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
269 if (entry
->msi_attrib
.is_msix
) {
270 void __iomem
*base
= entry
->mask_base
+
271 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
273 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
274 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
275 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
277 struct pci_dev
*dev
= entry
->dev
;
278 int pos
= dev
->msi_cap
;
281 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
283 if (entry
->msi_attrib
.is_64
) {
284 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
286 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
289 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
295 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
297 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
299 __read_msi_msg(entry
, msg
);
302 void __get_cached_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
304 /* Assert that the cache is valid, assuming that
305 * valid messages are not all-zeroes. */
306 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
312 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
314 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
316 __get_cached_msi_msg(entry
, msg
);
319 void __write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
321 if (entry
->dev
->current_state
!= PCI_D0
) {
322 /* Don't touch the hardware now */
323 } else if (entry
->msi_attrib
.is_msix
) {
325 base
= entry
->mask_base
+
326 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
328 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
329 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
330 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
332 struct pci_dev
*dev
= entry
->dev
;
333 int pos
= dev
->msi_cap
;
336 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
337 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
338 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
339 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
341 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
343 if (entry
->msi_attrib
.is_64
) {
344 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
346 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
349 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
356 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
358 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
360 __write_msi_msg(entry
, msg
);
363 static void free_msi_irqs(struct pci_dev
*dev
)
365 struct msi_desc
*entry
, *tmp
;
366 struct attribute
**msi_attrs
;
367 struct device_attribute
*dev_attr
;
370 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
374 if (entry
->nvec_used
)
375 nvec
= entry
->nvec_used
;
377 nvec
= 1 << entry
->msi_attrib
.multiple
;
378 for (i
= 0; i
< nvec
; i
++)
379 BUG_ON(irq_has_action(entry
->irq
+ i
));
382 arch_teardown_msi_irqs(dev
);
384 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
385 if (entry
->msi_attrib
.is_msix
) {
386 if (list_is_last(&entry
->list
, &dev
->msi_list
))
387 iounmap(entry
->mask_base
);
391 * Its possible that we get into this path
392 * When populate_msi_sysfs fails, which means the entries
393 * were not registered with sysfs. In that case don't
396 if (entry
->kobj
.parent
) {
397 kobject_del(&entry
->kobj
);
398 kobject_put(&entry
->kobj
);
401 list_del(&entry
->list
);
405 if (dev
->msi_irq_groups
) {
406 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
407 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
408 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
409 dev_attr
= container_of(msi_attrs
[count
],
410 struct device_attribute
, attr
);
411 kfree(dev_attr
->attr
.name
);
416 kfree(dev
->msi_irq_groups
[0]);
417 kfree(dev
->msi_irq_groups
);
418 dev
->msi_irq_groups
= NULL
;
422 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
424 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
428 INIT_LIST_HEAD(&desc
->list
);
434 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
436 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
437 pci_intx(dev
, enable
);
440 static void __pci_restore_msi_state(struct pci_dev
*dev
)
443 struct msi_desc
*entry
;
445 if (!dev
->msi_enabled
)
448 entry
= irq_get_msi_desc(dev
->irq
);
450 pci_intx_for_msi(dev
, 0);
451 msi_set_enable(dev
, 0);
452 arch_restore_msi_irqs(dev
, dev
->irq
);
454 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
455 msi_mask_irq(entry
, msi_capable_mask(control
), entry
->masked
);
456 control
&= ~PCI_MSI_FLAGS_QSIZE
;
457 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
458 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
461 static void __pci_restore_msix_state(struct pci_dev
*dev
)
463 struct msi_desc
*entry
;
466 if (!dev
->msix_enabled
)
468 BUG_ON(list_empty(&dev
->msi_list
));
469 entry
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
470 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
472 /* route the table */
473 pci_intx_for_msi(dev
, 0);
474 control
|= PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
;
475 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
477 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
478 arch_restore_msi_irqs(dev
, entry
->irq
);
479 msix_mask_irq(entry
, entry
->masked
);
482 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
483 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
486 void pci_restore_msi_state(struct pci_dev
*dev
)
488 __pci_restore_msi_state(dev
);
489 __pci_restore_msix_state(dev
);
491 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
493 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
496 struct pci_dev
*pdev
= to_pci_dev(dev
);
497 struct msi_desc
*entry
;
501 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
505 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
506 if (entry
->irq
== irq
) {
507 return sprintf(buf
, "%s\n",
508 entry
->msi_attrib
.is_msix
? "msix" : "msi");
514 static int populate_msi_sysfs(struct pci_dev
*pdev
)
516 struct attribute
**msi_attrs
;
517 struct attribute
*msi_attr
;
518 struct device_attribute
*msi_dev_attr
;
519 struct attribute_group
*msi_irq_group
;
520 const struct attribute_group
**msi_irq_groups
;
521 struct msi_desc
*entry
;
526 /* Determine how many msi entries we have */
527 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
533 /* Dynamically create the MSI attributes for the PCI device */
534 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
537 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
538 char *name
= kmalloc(20, GFP_KERNEL
);
539 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
542 sprintf(name
, "%d", entry
->irq
);
543 sysfs_attr_init(&msi_dev_attr
->attr
);
544 msi_dev_attr
->attr
.name
= name
;
545 msi_dev_attr
->attr
.mode
= S_IRUGO
;
546 msi_dev_attr
->show
= msi_mode_show
;
547 msi_attrs
[count
] = &msi_dev_attr
->attr
;
551 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
554 msi_irq_group
->name
= "msi_irqs";
555 msi_irq_group
->attrs
= msi_attrs
;
557 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
559 goto error_irq_group
;
560 msi_irq_groups
[0] = msi_irq_group
;
562 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
564 goto error_irq_groups
;
565 pdev
->msi_irq_groups
= msi_irq_groups
;
570 kfree(msi_irq_groups
);
572 kfree(msi_irq_group
);
575 msi_attr
= msi_attrs
[count
];
577 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
578 kfree(msi_attr
->name
);
581 msi_attr
= msi_attrs
[count
];
587 * msi_capability_init - configure device's MSI capability structure
588 * @dev: pointer to the pci_dev data structure of MSI device function
589 * @nvec: number of interrupts to allocate
591 * Setup the MSI capability structure of the device with the requested
592 * number of interrupts. A return value of zero indicates the successful
593 * setup of an entry with the new MSI irq. A negative return value indicates
594 * an error, and a positive return value indicates the number of interrupts
595 * which could have been allocated.
597 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
599 struct msi_desc
*entry
;
604 msi_set_enable(dev
, 0); /* Disable MSI during set up */
606 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
607 /* MSI Entry Initialization */
608 entry
= alloc_msi_entry(dev
);
612 entry
->msi_attrib
.is_msix
= 0;
613 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
614 entry
->msi_attrib
.entry_nr
= 0;
615 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
616 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
617 entry
->msi_attrib
.pos
= dev
->msi_cap
;
619 if (control
& PCI_MSI_FLAGS_64BIT
)
620 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
622 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
623 /* All MSIs are unmasked by default, Mask them all */
624 if (entry
->msi_attrib
.maskbit
)
625 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
626 mask
= msi_capable_mask(control
);
627 msi_mask_irq(entry
, mask
, mask
);
629 list_add_tail(&entry
->list
, &dev
->msi_list
);
631 /* Configure MSI capability structure */
632 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
634 msi_mask_irq(entry
, mask
, ~mask
);
639 ret
= populate_msi_sysfs(dev
);
641 msi_mask_irq(entry
, mask
, ~mask
);
646 /* Set MSI enabled bits */
647 pci_intx_for_msi(dev
, 0);
648 msi_set_enable(dev
, 1);
649 dev
->msi_enabled
= 1;
651 dev
->irq
= entry
->irq
;
655 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
657 resource_size_t phys_addr
;
661 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
663 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
664 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
665 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
667 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
670 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
671 struct msix_entry
*entries
, int nvec
)
673 struct msi_desc
*entry
;
676 for (i
= 0; i
< nvec
; i
++) {
677 entry
= alloc_msi_entry(dev
);
683 /* No enough memory. Don't try again */
687 entry
->msi_attrib
.is_msix
= 1;
688 entry
->msi_attrib
.is_64
= 1;
689 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
690 entry
->msi_attrib
.default_irq
= dev
->irq
;
691 entry
->msi_attrib
.pos
= dev
->msix_cap
;
692 entry
->mask_base
= base
;
694 list_add_tail(&entry
->list
, &dev
->msi_list
);
700 static void msix_program_entries(struct pci_dev
*dev
,
701 struct msix_entry
*entries
)
703 struct msi_desc
*entry
;
706 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
707 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
708 PCI_MSIX_ENTRY_VECTOR_CTRL
;
710 entries
[i
].vector
= entry
->irq
;
711 irq_set_msi_desc(entry
->irq
, entry
);
712 entry
->masked
= readl(entry
->mask_base
+ offset
);
713 msix_mask_irq(entry
, 1);
719 * msix_capability_init - configure device's MSI-X capability
720 * @dev: pointer to the pci_dev data structure of MSI-X device function
721 * @entries: pointer to an array of struct msix_entry entries
722 * @nvec: number of @entries
724 * Setup the MSI-X capability structure of device function with a
725 * single MSI-X irq. A return of zero indicates the successful setup of
726 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
728 static int msix_capability_init(struct pci_dev
*dev
,
729 struct msix_entry
*entries
, int nvec
)
735 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
737 /* Ensure MSI-X is disabled while it is set up */
738 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
739 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
741 /* Request & Map MSI-X table region */
742 base
= msix_map_region(dev
, msix_table_size(control
));
746 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
750 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
755 * Some devices require MSI-X to be enabled before we can touch the
756 * MSI-X registers. We need to mask all the vectors to prevent
757 * interrupts coming in before they're fully set up.
759 control
|= PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
;
760 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
762 msix_program_entries(dev
, entries
);
764 ret
= populate_msi_sysfs(dev
);
770 /* Set MSI-X enabled bits and unmask the function */
771 pci_intx_for_msi(dev
, 0);
772 dev
->msix_enabled
= 1;
774 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
775 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
782 * If we had some success, report the number of irqs
783 * we succeeded in setting up.
785 struct msi_desc
*entry
;
788 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
802 * pci_msi_check_device - check whether MSI may be enabled on a device
803 * @dev: pointer to the pci_dev data structure of MSI device function
804 * @nvec: how many MSIs have been requested ?
805 * @type: are we checking for MSI or MSI-X ?
807 * Look at global flags, the device itself, and its parent buses
808 * to determine if MSI/-X are supported for the device. If MSI/-X is
809 * supported return 0, else return an error code.
811 static int pci_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
816 /* MSI must be globally enabled and supported by the device */
817 if (!pci_msi_enable
|| !dev
|| dev
->no_msi
)
821 * You can't ask to have 0 or less MSIs configured.
823 * b) the list manipulation code assumes nvec >= 1.
829 * Any bridge which does NOT route MSI transactions from its
830 * secondary bus to its primary bus must set NO_MSI flag on
831 * the secondary pci_bus.
832 * We expect only arch-specific PCI host bus controller driver
833 * or quirks for specific PCI bridges to be setting NO_MSI.
835 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
836 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
839 ret
= arch_msi_check_device(dev
, nvec
, type
);
847 * pci_enable_msi_block - configure device's MSI capability structure
848 * @dev: device to configure
849 * @nvec: number of interrupts to configure
851 * Allocate IRQs for a device with the MSI capability.
852 * This function returns a negative errno if an error occurs. If it
853 * is unable to allocate the number of interrupts requested, it returns
854 * the number of interrupts it might be able to allocate. If it successfully
855 * allocates at least the number of interrupts requested, it returns 0 and
856 * updates the @dev's irq member to the lowest new interrupt number; the
857 * other interrupt numbers allocated to this device are consecutive.
859 int pci_enable_msi_block(struct pci_dev
*dev
, unsigned int nvec
)
864 if (!dev
->msi_cap
|| dev
->current_state
!= PCI_D0
)
867 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
868 maxvec
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
872 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSI
);
876 WARN_ON(!!dev
->msi_enabled
);
878 /* Check whether driver already requested MSI-X irqs */
879 if (dev
->msix_enabled
) {
880 dev_info(&dev
->dev
, "can't enable MSI "
881 "(MSI-X already enabled)\n");
885 status
= msi_capability_init(dev
, nvec
);
888 EXPORT_SYMBOL(pci_enable_msi_block
);
890 int pci_enable_msi_block_auto(struct pci_dev
*dev
, unsigned int *maxvec
)
895 if (!dev
->msi_cap
|| dev
->current_state
!= PCI_D0
)
898 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
899 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
906 ret
= pci_enable_msi_block(dev
, nvec
);
913 EXPORT_SYMBOL(pci_enable_msi_block_auto
);
915 void pci_msi_shutdown(struct pci_dev
*dev
)
917 struct msi_desc
*desc
;
921 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
924 BUG_ON(list_empty(&dev
->msi_list
));
925 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
927 msi_set_enable(dev
, 0);
928 pci_intx_for_msi(dev
, 1);
929 dev
->msi_enabled
= 0;
931 /* Return the device with MSI unmasked as initial states */
932 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &ctrl
);
933 mask
= msi_capable_mask(ctrl
);
934 /* Keep cached state to be restored */
935 arch_msi_mask_irq(desc
, mask
, ~mask
);
937 /* Restore dev->irq to its default pin-assertion irq */
938 dev
->irq
= desc
->msi_attrib
.default_irq
;
941 void pci_disable_msi(struct pci_dev
*dev
)
943 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
946 pci_msi_shutdown(dev
);
949 EXPORT_SYMBOL(pci_disable_msi
);
952 * pci_msix_table_size - return the number of device's MSI-X table entries
953 * @dev: pointer to the pci_dev data structure of MSI-X device function
955 int pci_msix_table_size(struct pci_dev
*dev
)
962 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
963 return msix_table_size(control
);
967 * pci_enable_msix - configure device's MSI-X capability structure
968 * @dev: pointer to the pci_dev data structure of MSI-X device function
969 * @entries: pointer to an array of MSI-X entries
970 * @nvec: number of MSI-X irqs requested for allocation by device driver
972 * Setup the MSI-X capability structure of device function with the number
973 * of requested irqs upon its software driver call to request for
974 * MSI-X mode enabled on its hardware device function. A return of zero
975 * indicates the successful configuration of MSI-X capability structure
976 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
977 * Or a return of > 0 indicates that driver request is exceeding the number
978 * of irqs or MSI-X vectors available. Driver should use the returned value to
979 * re-send its request.
981 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
983 int status
, nr_entries
;
986 if (!entries
|| !dev
->msix_cap
|| dev
->current_state
!= PCI_D0
)
989 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSIX
);
993 nr_entries
= pci_msix_table_size(dev
);
994 if (nvec
> nr_entries
)
997 /* Check for any invalid entries */
998 for (i
= 0; i
< nvec
; i
++) {
999 if (entries
[i
].entry
>= nr_entries
)
1000 return -EINVAL
; /* invalid entry */
1001 for (j
= i
+ 1; j
< nvec
; j
++) {
1002 if (entries
[i
].entry
== entries
[j
].entry
)
1003 return -EINVAL
; /* duplicate entry */
1006 WARN_ON(!!dev
->msix_enabled
);
1008 /* Check whether driver already requested for MSI irq */
1009 if (dev
->msi_enabled
) {
1010 dev_info(&dev
->dev
, "can't enable MSI-X "
1011 "(MSI IRQ already assigned)\n");
1014 status
= msix_capability_init(dev
, entries
, nvec
);
1017 EXPORT_SYMBOL(pci_enable_msix
);
1019 void pci_msix_shutdown(struct pci_dev
*dev
)
1021 struct msi_desc
*entry
;
1023 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1026 /* Return the device with MSI-X masked as initial states */
1027 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
1028 /* Keep cached states to be restored */
1029 arch_msix_mask_irq(entry
, 1);
1032 msix_set_enable(dev
, 0);
1033 pci_intx_for_msi(dev
, 1);
1034 dev
->msix_enabled
= 0;
1037 void pci_disable_msix(struct pci_dev
*dev
)
1039 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1042 pci_msix_shutdown(dev
);
1045 EXPORT_SYMBOL(pci_disable_msix
);
1048 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
1049 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1051 * Being called during hotplug remove, from which the device function
1052 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1053 * allocated for this device function, are reclaimed to unused state,
1054 * which may be used later on.
1056 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
)
1058 if (!pci_msi_enable
|| !dev
)
1061 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1065 void pci_no_msi(void)
1071 * pci_msi_enabled - is MSI enabled?
1073 * Returns true if MSI has not been disabled by the command-line option
1076 int pci_msi_enabled(void)
1078 return pci_msi_enable
;
1080 EXPORT_SYMBOL(pci_msi_enabled
);
1082 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
1084 INIT_LIST_HEAD(&dev
->msi_list
);
1086 /* Disable the msi hardware to avoid screaming interrupts
1087 * during boot. This is the power on reset default so
1088 * usually this should be a noop.
1090 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1092 msi_set_enable(dev
, 0);
1094 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1096 msix_set_enable(dev
, 0);