3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/irqdomain.h>
23 #include <linux/of_irq.h>
27 static int pci_msi_enable
= 1;
28 int pci_msi_ignore_mask
;
30 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
32 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
33 static struct irq_domain
*pci_msi_default_domain
;
34 static DEFINE_MUTEX(pci_msi_domain_lock
);
36 struct irq_domain
* __weak
arch_get_pci_msi_domain(struct pci_dev
*dev
)
38 return pci_msi_default_domain
;
41 static struct irq_domain
*pci_msi_get_domain(struct pci_dev
*dev
)
43 struct irq_domain
*domain
;
45 domain
= dev_get_msi_domain(&dev
->dev
);
49 return arch_get_pci_msi_domain(dev
);
52 static int pci_msi_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
54 struct irq_domain
*domain
;
56 domain
= pci_msi_get_domain(dev
);
57 if (domain
&& irq_domain_is_hierarchy(domain
))
58 return pci_msi_domain_alloc_irqs(domain
, dev
, nvec
, type
);
60 return arch_setup_msi_irqs(dev
, nvec
, type
);
63 static void pci_msi_teardown_msi_irqs(struct pci_dev
*dev
)
65 struct irq_domain
*domain
;
67 domain
= pci_msi_get_domain(dev
);
68 if (domain
&& irq_domain_is_hierarchy(domain
))
69 pci_msi_domain_free_irqs(domain
, dev
);
71 arch_teardown_msi_irqs(dev
);
74 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
75 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
80 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
82 struct msi_controller
*chip
= dev
->bus
->msi
;
85 if (!chip
|| !chip
->setup_irq
)
88 err
= chip
->setup_irq(chip
, dev
, desc
);
92 irq_set_chip_data(desc
->irq
, chip
);
97 void __weak
arch_teardown_msi_irq(unsigned int irq
)
99 struct msi_controller
*chip
= irq_get_chip_data(irq
);
101 if (!chip
|| !chip
->teardown_irq
)
104 chip
->teardown_irq(chip
, irq
);
107 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
109 struct msi_controller
*chip
= dev
->bus
->msi
;
110 struct msi_desc
*entry
;
113 if (chip
&& chip
->setup_irqs
)
114 return chip
->setup_irqs(chip
, dev
, nvec
, type
);
116 * If an architecture wants to support multiple MSI, it needs to
117 * override arch_setup_msi_irqs()
119 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
122 for_each_pci_msi_entry(entry
, dev
) {
123 ret
= arch_setup_msi_irq(dev
, entry
);
134 * We have a default implementation available as a separate non-weak
135 * function, as it is used by the Xen x86 PCI code
137 void default_teardown_msi_irqs(struct pci_dev
*dev
)
140 struct msi_desc
*entry
;
142 for_each_pci_msi_entry(entry
, dev
)
144 for (i
= 0; i
< entry
->nvec_used
; i
++)
145 arch_teardown_msi_irq(entry
->irq
+ i
);
148 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
150 return default_teardown_msi_irqs(dev
);
153 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
155 struct msi_desc
*entry
;
158 if (dev
->msix_enabled
) {
159 for_each_pci_msi_entry(entry
, dev
) {
160 if (irq
== entry
->irq
)
163 } else if (dev
->msi_enabled
) {
164 entry
= irq_get_msi_desc(irq
);
168 __pci_write_msi_msg(entry
, &entry
->msg
);
171 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
173 return default_restore_msi_irqs(dev
);
176 static inline __attribute_const__ u32
msi_mask(unsigned x
)
178 /* Don't shift by >= width of type */
181 return (1 << (1 << x
)) - 1;
185 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
186 * mask all MSI interrupts by clearing the MSI enable bit does not work
187 * reliably as devices without an INTx disable bit will then generate a
188 * level IRQ which will never be cleared.
190 u32
__pci_msi_desc_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
192 u32 mask_bits
= desc
->masked
;
194 if (pci_msi_ignore_mask
|| !desc
->msi_attrib
.maskbit
)
199 pci_write_config_dword(msi_desc_to_pci_dev(desc
), desc
->mask_pos
,
205 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
207 desc
->masked
= __pci_msi_desc_mask_irq(desc
, mask
, flag
);
210 static void __iomem
*pci_msix_desc_addr(struct msi_desc
*desc
)
212 return desc
->mask_base
+
213 desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
217 * This internal function does not flush PCI writes to the device.
218 * All users must ensure that they read from the device before either
219 * assuming that the device state is up to date, or returning out of this
220 * file. This saves a few milliseconds when initialising devices with lots
221 * of MSI-X interrupts.
223 u32
__pci_msix_desc_mask_irq(struct msi_desc
*desc
, u32 flag
)
225 u32 mask_bits
= desc
->masked
;
227 if (pci_msi_ignore_mask
)
230 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
232 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
233 writel(mask_bits
, pci_msix_desc_addr(desc
) + PCI_MSIX_ENTRY_VECTOR_CTRL
);
238 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
240 desc
->masked
= __pci_msix_desc_mask_irq(desc
, flag
);
243 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
245 struct msi_desc
*desc
= irq_data_get_msi_desc(data
);
247 if (desc
->msi_attrib
.is_msix
) {
248 msix_mask_irq(desc
, flag
);
249 readl(desc
->mask_base
); /* Flush write to device */
251 unsigned offset
= data
->irq
- desc
->irq
;
252 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
257 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
258 * @data: pointer to irqdata associated to that interrupt
260 void pci_msi_mask_irq(struct irq_data
*data
)
262 msi_set_mask_bit(data
, 1);
264 EXPORT_SYMBOL_GPL(pci_msi_mask_irq
);
267 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
268 * @data: pointer to irqdata associated to that interrupt
270 void pci_msi_unmask_irq(struct irq_data
*data
)
272 msi_set_mask_bit(data
, 0);
274 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq
);
276 void default_restore_msi_irqs(struct pci_dev
*dev
)
278 struct msi_desc
*entry
;
280 for_each_pci_msi_entry(entry
, dev
)
281 default_restore_msi_irq(dev
, entry
->irq
);
284 void __pci_read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
286 struct pci_dev
*dev
= msi_desc_to_pci_dev(entry
);
288 BUG_ON(dev
->current_state
!= PCI_D0
);
290 if (entry
->msi_attrib
.is_msix
) {
291 void __iomem
*base
= pci_msix_desc_addr(entry
);
293 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
294 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
295 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
297 int pos
= dev
->msi_cap
;
300 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
302 if (entry
->msi_attrib
.is_64
) {
303 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
305 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
308 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
314 void __pci_write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
316 struct pci_dev
*dev
= msi_desc_to_pci_dev(entry
);
318 if (dev
->current_state
!= PCI_D0
) {
319 /* Don't touch the hardware now */
320 } else if (entry
->msi_attrib
.is_msix
) {
321 void __iomem
*base
= pci_msix_desc_addr(entry
);
323 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
324 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
325 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
327 int pos
= dev
->msi_cap
;
330 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
331 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
332 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
333 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
335 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
337 if (entry
->msi_attrib
.is_64
) {
338 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
340 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
343 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
350 void pci_write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
352 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
354 __pci_write_msi_msg(entry
, msg
);
356 EXPORT_SYMBOL_GPL(pci_write_msi_msg
);
358 static void free_msi_irqs(struct pci_dev
*dev
)
360 struct list_head
*msi_list
= dev_to_msi_list(&dev
->dev
);
361 struct msi_desc
*entry
, *tmp
;
362 struct attribute
**msi_attrs
;
363 struct device_attribute
*dev_attr
;
366 for_each_pci_msi_entry(entry
, dev
)
368 for (i
= 0; i
< entry
->nvec_used
; i
++)
369 BUG_ON(irq_has_action(entry
->irq
+ i
));
371 pci_msi_teardown_msi_irqs(dev
);
373 list_for_each_entry_safe(entry
, tmp
, msi_list
, list
) {
374 if (entry
->msi_attrib
.is_msix
) {
375 if (list_is_last(&entry
->list
, msi_list
))
376 iounmap(entry
->mask_base
);
379 list_del(&entry
->list
);
383 if (dev
->msi_irq_groups
) {
384 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
385 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
386 while (msi_attrs
[count
]) {
387 dev_attr
= container_of(msi_attrs
[count
],
388 struct device_attribute
, attr
);
389 kfree(dev_attr
->attr
.name
);
394 kfree(dev
->msi_irq_groups
[0]);
395 kfree(dev
->msi_irq_groups
);
396 dev
->msi_irq_groups
= NULL
;
400 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
402 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
403 pci_intx(dev
, enable
);
406 static void __pci_restore_msi_state(struct pci_dev
*dev
)
409 struct msi_desc
*entry
;
411 if (!dev
->msi_enabled
)
414 entry
= irq_get_msi_desc(dev
->irq
);
416 pci_intx_for_msi(dev
, 0);
417 pci_msi_set_enable(dev
, 0);
418 arch_restore_msi_irqs(dev
);
420 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
421 msi_mask_irq(entry
, msi_mask(entry
->msi_attrib
.multi_cap
),
423 control
&= ~PCI_MSI_FLAGS_QSIZE
;
424 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
425 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
428 static void __pci_restore_msix_state(struct pci_dev
*dev
)
430 struct msi_desc
*entry
;
432 if (!dev
->msix_enabled
)
434 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
436 /* route the table */
437 pci_intx_for_msi(dev
, 0);
438 pci_msix_clear_and_set_ctrl(dev
, 0,
439 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
441 arch_restore_msi_irqs(dev
);
442 for_each_pci_msi_entry(entry
, dev
)
443 msix_mask_irq(entry
, entry
->masked
);
445 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
448 void pci_restore_msi_state(struct pci_dev
*dev
)
450 __pci_restore_msi_state(dev
);
451 __pci_restore_msix_state(dev
);
453 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
455 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
458 struct msi_desc
*entry
;
462 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
466 entry
= irq_get_msi_desc(irq
);
468 return sprintf(buf
, "%s\n",
469 entry
->msi_attrib
.is_msix
? "msix" : "msi");
474 static int populate_msi_sysfs(struct pci_dev
*pdev
)
476 struct attribute
**msi_attrs
;
477 struct attribute
*msi_attr
;
478 struct device_attribute
*msi_dev_attr
;
479 struct attribute_group
*msi_irq_group
;
480 const struct attribute_group
**msi_irq_groups
;
481 struct msi_desc
*entry
;
487 /* Determine how many msi entries we have */
488 for_each_pci_msi_entry(entry
, pdev
)
489 num_msi
+= entry
->nvec_used
;
493 /* Dynamically create the MSI attributes for the PCI device */
494 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
497 for_each_pci_msi_entry(entry
, pdev
) {
498 for (i
= 0; i
< entry
->nvec_used
; i
++) {
499 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
502 msi_attrs
[count
] = &msi_dev_attr
->attr
;
504 sysfs_attr_init(&msi_dev_attr
->attr
);
505 msi_dev_attr
->attr
.name
= kasprintf(GFP_KERNEL
, "%d",
507 if (!msi_dev_attr
->attr
.name
)
509 msi_dev_attr
->attr
.mode
= S_IRUGO
;
510 msi_dev_attr
->show
= msi_mode_show
;
515 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
518 msi_irq_group
->name
= "msi_irqs";
519 msi_irq_group
->attrs
= msi_attrs
;
521 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
523 goto error_irq_group
;
524 msi_irq_groups
[0] = msi_irq_group
;
526 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
528 goto error_irq_groups
;
529 pdev
->msi_irq_groups
= msi_irq_groups
;
534 kfree(msi_irq_groups
);
536 kfree(msi_irq_group
);
539 msi_attr
= msi_attrs
[count
];
541 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
542 kfree(msi_attr
->name
);
545 msi_attr
= msi_attrs
[count
];
551 static struct msi_desc
*msi_setup_entry(struct pci_dev
*dev
, int nvec
)
554 struct msi_desc
*entry
;
556 /* MSI Entry Initialization */
557 entry
= alloc_msi_entry(&dev
->dev
);
561 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
563 entry
->msi_attrib
.is_msix
= 0;
564 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
565 entry
->msi_attrib
.entry_nr
= 0;
566 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
567 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
568 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
569 entry
->msi_attrib
.multiple
= ilog2(__roundup_pow_of_two(nvec
));
570 entry
->nvec_used
= nvec
;
572 if (control
& PCI_MSI_FLAGS_64BIT
)
573 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
575 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
577 /* Save the initial mask status */
578 if (entry
->msi_attrib
.maskbit
)
579 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
584 static int msi_verify_entries(struct pci_dev
*dev
)
586 struct msi_desc
*entry
;
588 for_each_pci_msi_entry(entry
, dev
) {
589 if (!dev
->no_64bit_msi
|| !entry
->msg
.address_hi
)
591 dev_err(&dev
->dev
, "Device has broken 64-bit MSI but arch"
592 " tried to assign one above 4G\n");
599 * msi_capability_init - configure device's MSI capability structure
600 * @dev: pointer to the pci_dev data structure of MSI device function
601 * @nvec: number of interrupts to allocate
603 * Setup the MSI capability structure of the device with the requested
604 * number of interrupts. A return value of zero indicates the successful
605 * setup of an entry with the new MSI irq. A negative return value indicates
606 * an error, and a positive return value indicates the number of interrupts
607 * which could have been allocated.
609 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
611 struct msi_desc
*entry
;
615 pci_msi_set_enable(dev
, 0); /* Disable MSI during set up */
617 entry
= msi_setup_entry(dev
, nvec
);
621 /* All MSIs are unmasked by default, Mask them all */
622 mask
= msi_mask(entry
->msi_attrib
.multi_cap
);
623 msi_mask_irq(entry
, mask
, mask
);
625 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
627 /* Configure MSI capability structure */
628 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
630 msi_mask_irq(entry
, mask
, ~mask
);
635 ret
= msi_verify_entries(dev
);
637 msi_mask_irq(entry
, mask
, ~mask
);
642 ret
= populate_msi_sysfs(dev
);
644 msi_mask_irq(entry
, mask
, ~mask
);
649 /* Set MSI enabled bits */
650 pci_intx_for_msi(dev
, 0);
651 pci_msi_set_enable(dev
, 1);
652 dev
->msi_enabled
= 1;
654 pcibios_free_irq(dev
);
655 dev
->irq
= entry
->irq
;
659 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
661 resource_size_t phys_addr
;
666 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
668 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
669 flags
= pci_resource_flags(dev
, bir
);
670 if (!flags
|| (flags
& IORESOURCE_UNSET
))
673 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
674 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
676 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
679 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
680 struct msix_entry
*entries
, int nvec
)
682 struct msi_desc
*entry
;
685 for (i
= 0; i
< nvec
; i
++) {
686 entry
= alloc_msi_entry(&dev
->dev
);
692 /* No enough memory. Don't try again */
696 entry
->msi_attrib
.is_msix
= 1;
697 entry
->msi_attrib
.is_64
= 1;
698 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
699 entry
->msi_attrib
.default_irq
= dev
->irq
;
700 entry
->mask_base
= base
;
701 entry
->nvec_used
= 1;
703 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
709 static void msix_program_entries(struct pci_dev
*dev
,
710 struct msix_entry
*entries
)
712 struct msi_desc
*entry
;
715 for_each_pci_msi_entry(entry
, dev
) {
716 entries
[i
].vector
= entry
->irq
;
717 entry
->masked
= readl(pci_msix_desc_addr(entry
) +
718 PCI_MSIX_ENTRY_VECTOR_CTRL
);
719 msix_mask_irq(entry
, 1);
725 * msix_capability_init - configure device's MSI-X capability
726 * @dev: pointer to the pci_dev data structure of MSI-X device function
727 * @entries: pointer to an array of struct msix_entry entries
728 * @nvec: number of @entries
730 * Setup the MSI-X capability structure of device function with a
731 * single MSI-X irq. A return of zero indicates the successful setup of
732 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
734 static int msix_capability_init(struct pci_dev
*dev
,
735 struct msix_entry
*entries
, int nvec
)
741 /* Ensure MSI-X is disabled while it is set up */
742 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
744 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
745 /* Request & Map MSI-X table region */
746 base
= msix_map_region(dev
, msix_table_size(control
));
750 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
754 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
758 /* Check if all MSI entries honor device restrictions */
759 ret
= msi_verify_entries(dev
);
764 * Some devices require MSI-X to be enabled before we can touch the
765 * MSI-X registers. We need to mask all the vectors to prevent
766 * interrupts coming in before they're fully set up.
768 pci_msix_clear_and_set_ctrl(dev
, 0,
769 PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
);
771 msix_program_entries(dev
, entries
);
773 ret
= populate_msi_sysfs(dev
);
777 /* Set MSI-X enabled bits and unmask the function */
778 pci_intx_for_msi(dev
, 0);
779 dev
->msix_enabled
= 1;
780 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
782 pcibios_free_irq(dev
);
788 * If we had some success, report the number of irqs
789 * we succeeded in setting up.
791 struct msi_desc
*entry
;
794 for_each_pci_msi_entry(entry
, dev
) {
809 * pci_msi_supported - check whether MSI may be enabled on a device
810 * @dev: pointer to the pci_dev data structure of MSI device function
811 * @nvec: how many MSIs have been requested ?
813 * Look at global flags, the device itself, and its parent buses
814 * to determine if MSI/-X are supported for the device. If MSI/-X is
815 * supported return 1, else return 0.
817 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
821 /* MSI must be globally enabled and supported by the device */
825 if (!dev
|| dev
->no_msi
|| dev
->current_state
!= PCI_D0
)
829 * You can't ask to have 0 or less MSIs configured.
831 * b) the list manipulation code assumes nvec >= 1.
837 * Any bridge which does NOT route MSI transactions from its
838 * secondary bus to its primary bus must set NO_MSI flag on
839 * the secondary pci_bus.
840 * We expect only arch-specific PCI host bus controller driver
841 * or quirks for specific PCI bridges to be setting NO_MSI.
843 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
844 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
851 * pci_msi_vec_count - Return the number of MSI vectors a device can send
852 * @dev: device to report about
854 * This function returns the number of MSI vectors a device requested via
855 * Multiple Message Capable register. It returns a negative errno if the
856 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
857 * and returns a power of two, up to a maximum of 2^5 (32), according to the
860 int pci_msi_vec_count(struct pci_dev
*dev
)
868 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
869 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
873 EXPORT_SYMBOL(pci_msi_vec_count
);
875 void pci_msi_shutdown(struct pci_dev
*dev
)
877 struct msi_desc
*desc
;
880 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
883 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
884 desc
= first_pci_msi_entry(dev
);
886 pci_msi_set_enable(dev
, 0);
887 pci_intx_for_msi(dev
, 1);
888 dev
->msi_enabled
= 0;
890 /* Return the device with MSI unmasked as initial states */
891 mask
= msi_mask(desc
->msi_attrib
.multi_cap
);
892 /* Keep cached state to be restored */
893 __pci_msi_desc_mask_irq(desc
, mask
, ~mask
);
895 /* Restore dev->irq to its default pin-assertion irq */
896 dev
->irq
= desc
->msi_attrib
.default_irq
;
897 pcibios_alloc_irq(dev
);
900 void pci_disable_msi(struct pci_dev
*dev
)
902 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
905 pci_msi_shutdown(dev
);
908 EXPORT_SYMBOL(pci_disable_msi
);
911 * pci_msix_vec_count - return the number of device's MSI-X table entries
912 * @dev: pointer to the pci_dev data structure of MSI-X device function
913 * This function returns the number of device's MSI-X table entries and
914 * therefore the number of MSI-X vectors device is capable of sending.
915 * It returns a negative errno if the device is not capable of sending MSI-X
918 int pci_msix_vec_count(struct pci_dev
*dev
)
925 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
926 return msix_table_size(control
);
928 EXPORT_SYMBOL(pci_msix_vec_count
);
931 * pci_enable_msix - configure device's MSI-X capability structure
932 * @dev: pointer to the pci_dev data structure of MSI-X device function
933 * @entries: pointer to an array of MSI-X entries
934 * @nvec: number of MSI-X irqs requested for allocation by device driver
936 * Setup the MSI-X capability structure of device function with the number
937 * of requested irqs upon its software driver call to request for
938 * MSI-X mode enabled on its hardware device function. A return of zero
939 * indicates the successful configuration of MSI-X capability structure
940 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
941 * Or a return of > 0 indicates that driver request is exceeding the number
942 * of irqs or MSI-X vectors available. Driver should use the returned value to
943 * re-send its request.
945 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
950 if (!pci_msi_supported(dev
, nvec
))
956 nr_entries
= pci_msix_vec_count(dev
);
959 if (nvec
> nr_entries
)
962 /* Check for any invalid entries */
963 for (i
= 0; i
< nvec
; i
++) {
964 if (entries
[i
].entry
>= nr_entries
)
965 return -EINVAL
; /* invalid entry */
966 for (j
= i
+ 1; j
< nvec
; j
++) {
967 if (entries
[i
].entry
== entries
[j
].entry
)
968 return -EINVAL
; /* duplicate entry */
971 WARN_ON(!!dev
->msix_enabled
);
973 /* Check whether driver already requested for MSI irq */
974 if (dev
->msi_enabled
) {
975 dev_info(&dev
->dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
978 return msix_capability_init(dev
, entries
, nvec
);
980 EXPORT_SYMBOL(pci_enable_msix
);
982 void pci_msix_shutdown(struct pci_dev
*dev
)
984 struct msi_desc
*entry
;
986 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
989 /* Return the device with MSI-X masked as initial states */
990 for_each_pci_msi_entry(entry
, dev
) {
991 /* Keep cached states to be restored */
992 __pci_msix_desc_mask_irq(entry
, 1);
995 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
996 pci_intx_for_msi(dev
, 1);
997 dev
->msix_enabled
= 0;
998 pcibios_alloc_irq(dev
);
1001 void pci_disable_msix(struct pci_dev
*dev
)
1003 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1006 pci_msix_shutdown(dev
);
1009 EXPORT_SYMBOL(pci_disable_msix
);
1011 void pci_no_msi(void)
1017 * pci_msi_enabled - is MSI enabled?
1019 * Returns true if MSI has not been disabled by the command-line option
1022 int pci_msi_enabled(void)
1024 return pci_msi_enable
;
1026 EXPORT_SYMBOL(pci_msi_enabled
);
1029 * pci_enable_msi_range - configure device's MSI capability structure
1030 * @dev: device to configure
1031 * @minvec: minimal number of interrupts to configure
1032 * @maxvec: maximum number of interrupts to configure
1034 * This function tries to allocate a maximum possible number of interrupts in a
1035 * range between @minvec and @maxvec. It returns a negative errno if an error
1036 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1037 * and updates the @dev's irq member to the lowest new interrupt number;
1038 * the other interrupt numbers allocated to this device are consecutive.
1040 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
)
1045 if (!pci_msi_supported(dev
, minvec
))
1048 WARN_ON(!!dev
->msi_enabled
);
1050 /* Check whether driver already requested MSI-X irqs */
1051 if (dev
->msix_enabled
) {
1053 "can't enable MSI (MSI-X already enabled)\n");
1057 if (maxvec
< minvec
)
1060 nvec
= pci_msi_vec_count(dev
);
1063 else if (nvec
< minvec
)
1065 else if (nvec
> maxvec
)
1069 rc
= msi_capability_init(dev
, nvec
);
1072 } else if (rc
> 0) {
1081 EXPORT_SYMBOL(pci_enable_msi_range
);
1084 * pci_enable_msix_range - configure device's MSI-X capability structure
1085 * @dev: pointer to the pci_dev data structure of MSI-X device function
1086 * @entries: pointer to an array of MSI-X entries
1087 * @minvec: minimum number of MSI-X irqs requested
1088 * @maxvec: maximum number of MSI-X irqs requested
1090 * Setup the MSI-X capability structure of device function with a maximum
1091 * possible number of interrupts in the range between @minvec and @maxvec
1092 * upon its software driver call to request for MSI-X mode enabled on its
1093 * hardware device function. It returns a negative errno if an error occurs.
1094 * If it succeeds, it returns the actual number of interrupts allocated and
1095 * indicates the successful configuration of MSI-X capability structure
1096 * with new allocated MSI-X interrupts.
1098 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1099 int minvec
, int maxvec
)
1104 if (maxvec
< minvec
)
1108 rc
= pci_enable_msix(dev
, entries
, nvec
);
1111 } else if (rc
> 0) {
1120 EXPORT_SYMBOL(pci_enable_msix_range
);
1122 struct pci_dev
*msi_desc_to_pci_dev(struct msi_desc
*desc
)
1124 return to_pci_dev(desc
->dev
);
1126 EXPORT_SYMBOL(msi_desc_to_pci_dev
);
1128 void *msi_desc_to_pci_sysdata(struct msi_desc
*desc
)
1130 struct pci_dev
*dev
= msi_desc_to_pci_dev(desc
);
1132 return dev
->bus
->sysdata
;
1134 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata
);
1136 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1138 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1139 * @irq_data: Pointer to interrupt data of the MSI interrupt
1140 * @msg: Pointer to the message
1142 void pci_msi_domain_write_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
1144 struct msi_desc
*desc
= irq_data_get_msi_desc(irq_data
);
1147 * For MSI-X desc->irq is always equal to irq_data->irq. For
1148 * MSI only the first interrupt of MULTI MSI passes the test.
1150 if (desc
->irq
== irq_data
->irq
)
1151 __pci_write_msi_msg(desc
, msg
);
1155 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1156 * @dev: Pointer to the PCI device
1157 * @desc: Pointer to the msi descriptor
1159 * The ID number is only used within the irqdomain.
1161 irq_hw_number_t
pci_msi_domain_calc_hwirq(struct pci_dev
*dev
,
1162 struct msi_desc
*desc
)
1164 return (irq_hw_number_t
)desc
->msi_attrib
.entry_nr
|
1165 PCI_DEVID(dev
->bus
->number
, dev
->devfn
) << 11 |
1166 (pci_domain_nr(dev
->bus
) & 0xFFFFFFFF) << 27;
1169 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc
*desc
)
1171 return !desc
->msi_attrib
.is_msix
&& desc
->nvec_used
> 1;
1175 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1176 * @domain: The interrupt domain to check
1177 * @info: The domain info for verification
1178 * @dev: The device to check
1181 * 0 if the functionality is supported
1182 * 1 if Multi MSI is requested, but the domain does not support it
1183 * -ENOTSUPP otherwise
1185 int pci_msi_domain_check_cap(struct irq_domain
*domain
,
1186 struct msi_domain_info
*info
, struct device
*dev
)
1188 struct msi_desc
*desc
= first_pci_msi_entry(to_pci_dev(dev
));
1190 /* Special handling to support pci_enable_msi_range() */
1191 if (pci_msi_desc_is_multi_msi(desc
) &&
1192 !(info
->flags
& MSI_FLAG_MULTI_PCI_MSI
))
1194 else if (desc
->msi_attrib
.is_msix
&& !(info
->flags
& MSI_FLAG_PCI_MSIX
))
1200 static int pci_msi_domain_handle_error(struct irq_domain
*domain
,
1201 struct msi_desc
*desc
, int error
)
1203 /* Special handling to support pci_enable_msi_range() */
1204 if (pci_msi_desc_is_multi_msi(desc
) && error
== -ENOSPC
)
1210 #ifdef GENERIC_MSI_DOMAIN_OPS
1211 static void pci_msi_domain_set_desc(msi_alloc_info_t
*arg
,
1212 struct msi_desc
*desc
)
1215 arg
->hwirq
= pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc
),
1219 #define pci_msi_domain_set_desc NULL
1222 static struct msi_domain_ops pci_msi_domain_ops_default
= {
1223 .set_desc
= pci_msi_domain_set_desc
,
1224 .msi_check
= pci_msi_domain_check_cap
,
1225 .handle_error
= pci_msi_domain_handle_error
,
1228 static void pci_msi_domain_update_dom_ops(struct msi_domain_info
*info
)
1230 struct msi_domain_ops
*ops
= info
->ops
;
1233 info
->ops
= &pci_msi_domain_ops_default
;
1235 if (ops
->set_desc
== NULL
)
1236 ops
->set_desc
= pci_msi_domain_set_desc
;
1237 if (ops
->msi_check
== NULL
)
1238 ops
->msi_check
= pci_msi_domain_check_cap
;
1239 if (ops
->handle_error
== NULL
)
1240 ops
->handle_error
= pci_msi_domain_handle_error
;
1244 static void pci_msi_domain_update_chip_ops(struct msi_domain_info
*info
)
1246 struct irq_chip
*chip
= info
->chip
;
1249 if (!chip
->irq_write_msi_msg
)
1250 chip
->irq_write_msi_msg
= pci_msi_domain_write_msg
;
1251 if (!chip
->irq_mask
)
1252 chip
->irq_mask
= pci_msi_mask_irq
;
1253 if (!chip
->irq_unmask
)
1254 chip
->irq_unmask
= pci_msi_unmask_irq
;
1258 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1259 * @fwnode: Optional fwnode of the interrupt controller
1260 * @info: MSI domain info
1261 * @parent: Parent irq domain
1263 * Updates the domain and chip ops and creates a MSI interrupt domain.
1266 * A domain pointer or NULL in case of failure.
1268 struct irq_domain
*pci_msi_create_irq_domain(struct fwnode_handle
*fwnode
,
1269 struct msi_domain_info
*info
,
1270 struct irq_domain
*parent
)
1272 struct irq_domain
*domain
;
1274 if (info
->flags
& MSI_FLAG_USE_DEF_DOM_OPS
)
1275 pci_msi_domain_update_dom_ops(info
);
1276 if (info
->flags
& MSI_FLAG_USE_DEF_CHIP_OPS
)
1277 pci_msi_domain_update_chip_ops(info
);
1279 domain
= msi_create_irq_domain(fwnode
, info
, parent
);
1283 domain
->bus_token
= DOMAIN_BUS_PCI_MSI
;
1286 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain
);
1289 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1290 * @domain: The interrupt domain to allocate from
1291 * @dev: The device for which to allocate
1292 * @nvec: The number of interrupts to allocate
1293 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1296 * A virtual interrupt number or an error code in case of failure
1298 int pci_msi_domain_alloc_irqs(struct irq_domain
*domain
, struct pci_dev
*dev
,
1301 return msi_domain_alloc_irqs(domain
, &dev
->dev
, nvec
);
1305 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1306 * @domain: The interrupt domain
1307 * @dev: The device for which to free interrupts
1309 void pci_msi_domain_free_irqs(struct irq_domain
*domain
, struct pci_dev
*dev
)
1311 msi_domain_free_irqs(domain
, &dev
->dev
);
1315 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1316 * @fwnode: Optional fwnode of the interrupt controller
1317 * @info: MSI domain info
1318 * @parent: Parent irq domain
1320 * Returns: A domain pointer or NULL in case of failure. If successful
1321 * the default PCI/MSI irqdomain pointer is updated.
1323 struct irq_domain
*pci_msi_create_default_irq_domain(struct fwnode_handle
*fwnode
,
1324 struct msi_domain_info
*info
, struct irq_domain
*parent
)
1326 struct irq_domain
*domain
;
1328 mutex_lock(&pci_msi_domain_lock
);
1329 if (pci_msi_default_domain
) {
1330 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1333 domain
= pci_msi_create_irq_domain(fwnode
, info
, parent
);
1334 pci_msi_default_domain
= domain
;
1336 mutex_unlock(&pci_msi_domain_lock
);
1341 static int get_msi_id_cb(struct pci_dev
*pdev
, u16 alias
, void *data
)
1349 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1350 * @domain: The interrupt domain
1351 * @pdev: The PCI device.
1353 * The RID for a device is formed from the alias, with a firmware
1354 * supplied mapping applied
1358 u32
pci_msi_domain_get_msi_rid(struct irq_domain
*domain
, struct pci_dev
*pdev
)
1360 struct device_node
*of_node
;
1363 pci_for_each_dma_alias(pdev
, get_msi_id_cb
, &rid
);
1365 of_node
= irq_domain_get_of_node(domain
);
1367 rid
= of_msi_map_rid(&pdev
->dev
, of_node
, rid
);
1373 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1374 * @pdev: The PCI device
1376 * Use the firmware data to find a device-specific MSI domain
1377 * (i.e. not one that is ste as a default).
1379 * Returns: The coresponding MSI domain or NULL if none has been found.
1381 struct irq_domain
*pci_msi_get_device_domain(struct pci_dev
*pdev
)
1385 pci_for_each_dma_alias(pdev
, get_msi_id_cb
, &rid
);
1386 return of_msi_map_get_device_domain(&pdev
->dev
, rid
);
1388 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */