3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
25 static int pci_msi_enable
= 1;
27 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
32 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
34 struct msi_chip
*chip
= dev
->bus
->msi
;
37 if (!chip
|| !chip
->setup_irq
)
40 err
= chip
->setup_irq(chip
, dev
, desc
);
44 irq_set_chip_data(desc
->irq
, chip
);
49 void __weak
arch_teardown_msi_irq(unsigned int irq
)
51 struct msi_chip
*chip
= irq_get_chip_data(irq
);
53 if (!chip
|| !chip
->teardown_irq
)
56 chip
->teardown_irq(chip
, irq
);
59 int __weak
arch_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
61 struct msi_chip
*chip
= dev
->bus
->msi
;
63 if (!chip
|| !chip
->check_device
)
66 return chip
->check_device(chip
, dev
, nvec
, type
);
69 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
71 struct msi_desc
*entry
;
75 * If an architecture wants to support multiple MSI, it needs to
76 * override arch_setup_msi_irqs()
78 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
81 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
82 ret
= arch_setup_msi_irq(dev
, entry
);
93 * We have a default implementation available as a separate non-weak
94 * function, as it is used by the Xen x86 PCI code
96 void default_teardown_msi_irqs(struct pci_dev
*dev
)
98 struct msi_desc
*entry
;
100 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
104 if (entry
->nvec_used
)
105 nvec
= entry
->nvec_used
;
107 nvec
= 1 << entry
->msi_attrib
.multiple
;
108 for (i
= 0; i
< nvec
; i
++)
109 arch_teardown_msi_irq(entry
->irq
+ i
);
113 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
115 return default_teardown_msi_irqs(dev
);
118 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
120 struct msi_desc
*entry
;
123 if (dev
->msix_enabled
) {
124 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
125 if (irq
== entry
->irq
)
128 } else if (dev
->msi_enabled
) {
129 entry
= irq_get_msi_desc(irq
);
133 write_msi_msg(irq
, &entry
->msg
);
136 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
138 return default_restore_msi_irqs(dev
);
141 static void msi_set_enable(struct pci_dev
*dev
, int enable
)
145 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
146 control
&= ~PCI_MSI_FLAGS_ENABLE
;
148 control
|= PCI_MSI_FLAGS_ENABLE
;
149 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
152 static void msix_set_enable(struct pci_dev
*dev
, int enable
)
156 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
157 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
159 control
|= PCI_MSIX_FLAGS_ENABLE
;
160 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
163 static inline __attribute_const__ u32
msi_mask(unsigned x
)
165 /* Don't shift by >= width of type */
168 return (1 << (1 << x
)) - 1;
171 static inline __attribute_const__ u32
msi_capable_mask(u16 control
)
173 return msi_mask((control
>> 1) & 7);
176 static inline __attribute_const__ u32
msi_enabled_mask(u16 control
)
178 return msi_mask((control
>> 4) & 7);
182 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
183 * mask all MSI interrupts by clearing the MSI enable bit does not work
184 * reliably as devices without an INTx disable bit will then generate a
185 * level IRQ which will never be cleared.
187 u32
default_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
189 u32 mask_bits
= desc
->masked
;
191 if (!desc
->msi_attrib
.maskbit
)
196 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
201 __weak u32
arch_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
203 return default_msi_mask_irq(desc
, mask
, flag
);
206 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
208 desc
->masked
= arch_msi_mask_irq(desc
, mask
, flag
);
212 * This internal function does not flush PCI writes to the device.
213 * All users must ensure that they read from the device before either
214 * assuming that the device state is up to date, or returning out of this
215 * file. This saves a few milliseconds when initialising devices with lots
216 * of MSI-X interrupts.
218 u32
default_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
220 u32 mask_bits
= desc
->masked
;
221 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
222 PCI_MSIX_ENTRY_VECTOR_CTRL
;
223 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
225 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
226 writel(mask_bits
, desc
->mask_base
+ offset
);
231 __weak u32
arch_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
233 return default_msix_mask_irq(desc
, flag
);
236 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
238 desc
->masked
= arch_msix_mask_irq(desc
, flag
);
241 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
243 struct msi_desc
*desc
= irq_data_get_msi(data
);
245 if (desc
->msi_attrib
.is_msix
) {
246 msix_mask_irq(desc
, flag
);
247 readl(desc
->mask_base
); /* Flush write to device */
249 unsigned offset
= data
->irq
- desc
->dev
->irq
;
250 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
254 void mask_msi_irq(struct irq_data
*data
)
256 msi_set_mask_bit(data
, 1);
259 void unmask_msi_irq(struct irq_data
*data
)
261 msi_set_mask_bit(data
, 0);
264 void default_restore_msi_irqs(struct pci_dev
*dev
)
266 struct msi_desc
*entry
;
268 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
269 default_restore_msi_irq(dev
, entry
->irq
);
273 void __read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
275 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
277 if (entry
->msi_attrib
.is_msix
) {
278 void __iomem
*base
= entry
->mask_base
+
279 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
281 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
282 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
283 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
285 struct pci_dev
*dev
= entry
->dev
;
286 int pos
= dev
->msi_cap
;
289 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
291 if (entry
->msi_attrib
.is_64
) {
292 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
294 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
297 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
303 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
305 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
307 __read_msi_msg(entry
, msg
);
310 void __get_cached_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
312 /* Assert that the cache is valid, assuming that
313 * valid messages are not all-zeroes. */
314 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
320 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
322 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
324 __get_cached_msi_msg(entry
, msg
);
327 void __write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
329 if (entry
->dev
->current_state
!= PCI_D0
) {
330 /* Don't touch the hardware now */
331 } else if (entry
->msi_attrib
.is_msix
) {
333 base
= entry
->mask_base
+
334 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
336 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
337 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
338 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
340 struct pci_dev
*dev
= entry
->dev
;
341 int pos
= dev
->msi_cap
;
344 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
345 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
346 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
347 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
349 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
351 if (entry
->msi_attrib
.is_64
) {
352 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
354 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
357 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
364 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
366 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
368 __write_msi_msg(entry
, msg
);
371 static void free_msi_irqs(struct pci_dev
*dev
)
373 struct msi_desc
*entry
, *tmp
;
374 struct attribute
**msi_attrs
;
375 struct device_attribute
*dev_attr
;
378 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
382 if (entry
->nvec_used
)
383 nvec
= entry
->nvec_used
;
385 nvec
= 1 << entry
->msi_attrib
.multiple
;
386 for (i
= 0; i
< nvec
; i
++)
387 BUG_ON(irq_has_action(entry
->irq
+ i
));
390 arch_teardown_msi_irqs(dev
);
392 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
393 if (entry
->msi_attrib
.is_msix
) {
394 if (list_is_last(&entry
->list
, &dev
->msi_list
))
395 iounmap(entry
->mask_base
);
399 * Its possible that we get into this path
400 * When populate_msi_sysfs fails, which means the entries
401 * were not registered with sysfs. In that case don't
404 if (entry
->kobj
.parent
) {
405 kobject_del(&entry
->kobj
);
406 kobject_put(&entry
->kobj
);
409 list_del(&entry
->list
);
413 if (dev
->msi_irq_groups
) {
414 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
415 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
416 while (msi_attrs
[count
]) {
417 dev_attr
= container_of(msi_attrs
[count
],
418 struct device_attribute
, attr
);
419 kfree(dev_attr
->attr
.name
);
424 kfree(dev
->msi_irq_groups
[0]);
425 kfree(dev
->msi_irq_groups
);
426 dev
->msi_irq_groups
= NULL
;
430 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
432 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
436 INIT_LIST_HEAD(&desc
->list
);
442 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
444 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
445 pci_intx(dev
, enable
);
448 static void __pci_restore_msi_state(struct pci_dev
*dev
)
451 struct msi_desc
*entry
;
453 if (!dev
->msi_enabled
)
456 entry
= irq_get_msi_desc(dev
->irq
);
458 pci_intx_for_msi(dev
, 0);
459 msi_set_enable(dev
, 0);
460 arch_restore_msi_irqs(dev
);
462 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
463 msi_mask_irq(entry
, msi_capable_mask(control
), entry
->masked
);
464 control
&= ~PCI_MSI_FLAGS_QSIZE
;
465 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
466 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
469 static void __pci_restore_msix_state(struct pci_dev
*dev
)
471 struct msi_desc
*entry
;
474 if (!dev
->msix_enabled
)
476 BUG_ON(list_empty(&dev
->msi_list
));
477 entry
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
478 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
480 /* route the table */
481 pci_intx_for_msi(dev
, 0);
482 control
|= PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
;
483 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
485 arch_restore_msi_irqs(dev
);
486 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
487 msix_mask_irq(entry
, entry
->masked
);
490 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
491 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
494 void pci_restore_msi_state(struct pci_dev
*dev
)
496 __pci_restore_msi_state(dev
);
497 __pci_restore_msix_state(dev
);
499 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
501 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
504 struct pci_dev
*pdev
= to_pci_dev(dev
);
505 struct msi_desc
*entry
;
509 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
513 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
514 if (entry
->irq
== irq
) {
515 return sprintf(buf
, "%s\n",
516 entry
->msi_attrib
.is_msix
? "msix" : "msi");
522 static int populate_msi_sysfs(struct pci_dev
*pdev
)
524 struct attribute
**msi_attrs
;
525 struct attribute
*msi_attr
;
526 struct device_attribute
*msi_dev_attr
;
527 struct attribute_group
*msi_irq_group
;
528 const struct attribute_group
**msi_irq_groups
;
529 struct msi_desc
*entry
;
534 /* Determine how many msi entries we have */
535 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
541 /* Dynamically create the MSI attributes for the PCI device */
542 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
545 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
546 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
549 msi_attrs
[count
] = &msi_dev_attr
->attr
;
551 sysfs_attr_init(&msi_dev_attr
->attr
);
552 msi_dev_attr
->attr
.name
= kasprintf(GFP_KERNEL
, "%d",
554 if (!msi_dev_attr
->attr
.name
)
556 msi_dev_attr
->attr
.mode
= S_IRUGO
;
557 msi_dev_attr
->show
= msi_mode_show
;
561 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
564 msi_irq_group
->name
= "msi_irqs";
565 msi_irq_group
->attrs
= msi_attrs
;
567 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
569 goto error_irq_group
;
570 msi_irq_groups
[0] = msi_irq_group
;
572 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
574 goto error_irq_groups
;
575 pdev
->msi_irq_groups
= msi_irq_groups
;
580 kfree(msi_irq_groups
);
582 kfree(msi_irq_group
);
585 msi_attr
= msi_attrs
[count
];
587 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
588 kfree(msi_attr
->name
);
591 msi_attr
= msi_attrs
[count
];
598 * msi_capability_init - configure device's MSI capability structure
599 * @dev: pointer to the pci_dev data structure of MSI device function
600 * @nvec: number of interrupts to allocate
602 * Setup the MSI capability structure of the device with the requested
603 * number of interrupts. A return value of zero indicates the successful
604 * setup of an entry with the new MSI irq. A negative return value indicates
605 * an error, and a positive return value indicates the number of interrupts
606 * which could have been allocated.
608 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
610 struct msi_desc
*entry
;
615 msi_set_enable(dev
, 0); /* Disable MSI during set up */
617 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
618 /* MSI Entry Initialization */
619 entry
= alloc_msi_entry(dev
);
623 entry
->msi_attrib
.is_msix
= 0;
624 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
625 entry
->msi_attrib
.entry_nr
= 0;
626 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
627 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
628 entry
->msi_attrib
.pos
= dev
->msi_cap
;
630 if (control
& PCI_MSI_FLAGS_64BIT
)
631 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
633 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
634 /* All MSIs are unmasked by default, Mask them all */
635 if (entry
->msi_attrib
.maskbit
)
636 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
637 mask
= msi_capable_mask(control
);
638 msi_mask_irq(entry
, mask
, mask
);
640 list_add_tail(&entry
->list
, &dev
->msi_list
);
642 /* Configure MSI capability structure */
643 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
645 msi_mask_irq(entry
, mask
, ~mask
);
650 ret
= populate_msi_sysfs(dev
);
652 msi_mask_irq(entry
, mask
, ~mask
);
657 /* Set MSI enabled bits */
658 pci_intx_for_msi(dev
, 0);
659 msi_set_enable(dev
, 1);
660 dev
->msi_enabled
= 1;
662 dev
->irq
= entry
->irq
;
666 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
668 resource_size_t phys_addr
;
672 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
674 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
675 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
676 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
678 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
681 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
682 struct msix_entry
*entries
, int nvec
)
684 struct msi_desc
*entry
;
687 for (i
= 0; i
< nvec
; i
++) {
688 entry
= alloc_msi_entry(dev
);
694 /* No enough memory. Don't try again */
698 entry
->msi_attrib
.is_msix
= 1;
699 entry
->msi_attrib
.is_64
= 1;
700 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
701 entry
->msi_attrib
.default_irq
= dev
->irq
;
702 entry
->msi_attrib
.pos
= dev
->msix_cap
;
703 entry
->mask_base
= base
;
705 list_add_tail(&entry
->list
, &dev
->msi_list
);
711 static void msix_program_entries(struct pci_dev
*dev
,
712 struct msix_entry
*entries
)
714 struct msi_desc
*entry
;
717 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
718 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
719 PCI_MSIX_ENTRY_VECTOR_CTRL
;
721 entries
[i
].vector
= entry
->irq
;
722 irq_set_msi_desc(entry
->irq
, entry
);
723 entry
->masked
= readl(entry
->mask_base
+ offset
);
724 msix_mask_irq(entry
, 1);
730 * msix_capability_init - configure device's MSI-X capability
731 * @dev: pointer to the pci_dev data structure of MSI-X device function
732 * @entries: pointer to an array of struct msix_entry entries
733 * @nvec: number of @entries
735 * Setup the MSI-X capability structure of device function with a
736 * single MSI-X irq. A return of zero indicates the successful setup of
737 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
739 static int msix_capability_init(struct pci_dev
*dev
,
740 struct msix_entry
*entries
, int nvec
)
746 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
748 /* Ensure MSI-X is disabled while it is set up */
749 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
750 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
752 /* Request & Map MSI-X table region */
753 base
= msix_map_region(dev
, msix_table_size(control
));
757 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
761 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
766 * Some devices require MSI-X to be enabled before we can touch the
767 * MSI-X registers. We need to mask all the vectors to prevent
768 * interrupts coming in before they're fully set up.
770 control
|= PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
;
771 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
773 msix_program_entries(dev
, entries
);
775 ret
= populate_msi_sysfs(dev
);
779 /* Set MSI-X enabled bits and unmask the function */
780 pci_intx_for_msi(dev
, 0);
781 dev
->msix_enabled
= 1;
783 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
784 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, control
);
791 * If we had some success, report the number of irqs
792 * we succeeded in setting up.
794 struct msi_desc
*entry
;
797 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
812 * pci_msi_check_device - check whether MSI may be enabled on a device
813 * @dev: pointer to the pci_dev data structure of MSI device function
814 * @nvec: how many MSIs have been requested ?
815 * @type: are we checking for MSI or MSI-X ?
817 * Look at global flags, the device itself, and its parent buses
818 * to determine if MSI/-X are supported for the device. If MSI/-X is
819 * supported return 0, else return an error code.
821 static int pci_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
826 /* MSI must be globally enabled and supported by the device */
827 if (!pci_msi_enable
|| !dev
|| dev
->no_msi
)
831 * You can't ask to have 0 or less MSIs configured.
833 * b) the list manipulation code assumes nvec >= 1.
839 * Any bridge which does NOT route MSI transactions from its
840 * secondary bus to its primary bus must set NO_MSI flag on
841 * the secondary pci_bus.
842 * We expect only arch-specific PCI host bus controller driver
843 * or quirks for specific PCI bridges to be setting NO_MSI.
845 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
846 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
849 ret
= arch_msi_check_device(dev
, nvec
, type
);
857 * pci_msi_vec_count - Return the number of MSI vectors a device can send
858 * @dev: device to report about
860 * This function returns the number of MSI vectors a device requested via
861 * Multiple Message Capable register. It returns a negative errno if the
862 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
863 * and returns a power of two, up to a maximum of 2^5 (32), according to the
866 int pci_msi_vec_count(struct pci_dev
*dev
)
874 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
875 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
879 EXPORT_SYMBOL(pci_msi_vec_count
);
881 void pci_msi_shutdown(struct pci_dev
*dev
)
883 struct msi_desc
*desc
;
887 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
890 BUG_ON(list_empty(&dev
->msi_list
));
891 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
893 msi_set_enable(dev
, 0);
894 pci_intx_for_msi(dev
, 1);
895 dev
->msi_enabled
= 0;
897 /* Return the device with MSI unmasked as initial states */
898 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &ctrl
);
899 mask
= msi_capable_mask(ctrl
);
900 /* Keep cached state to be restored */
901 arch_msi_mask_irq(desc
, mask
, ~mask
);
903 /* Restore dev->irq to its default pin-assertion irq */
904 dev
->irq
= desc
->msi_attrib
.default_irq
;
907 void pci_disable_msi(struct pci_dev
*dev
)
909 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
912 pci_msi_shutdown(dev
);
915 EXPORT_SYMBOL(pci_disable_msi
);
918 * pci_msix_vec_count - return the number of device's MSI-X table entries
919 * @dev: pointer to the pci_dev data structure of MSI-X device function
920 * This function returns the number of device's MSI-X table entries and
921 * therefore the number of MSI-X vectors device is capable of sending.
922 * It returns a negative errno if the device is not capable of sending MSI-X
925 int pci_msix_vec_count(struct pci_dev
*dev
)
932 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
933 return msix_table_size(control
);
935 EXPORT_SYMBOL(pci_msix_vec_count
);
938 * pci_enable_msix - configure device's MSI-X capability structure
939 * @dev: pointer to the pci_dev data structure of MSI-X device function
940 * @entries: pointer to an array of MSI-X entries
941 * @nvec: number of MSI-X irqs requested for allocation by device driver
943 * Setup the MSI-X capability structure of device function with the number
944 * of requested irqs upon its software driver call to request for
945 * MSI-X mode enabled on its hardware device function. A return of zero
946 * indicates the successful configuration of MSI-X capability structure
947 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
948 * Or a return of > 0 indicates that driver request is exceeding the number
949 * of irqs or MSI-X vectors available. Driver should use the returned value to
950 * re-send its request.
952 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
954 int status
, nr_entries
;
957 if (!entries
|| !dev
->msix_cap
|| dev
->current_state
!= PCI_D0
)
960 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSIX
);
964 nr_entries
= pci_msix_vec_count(dev
);
967 if (nvec
> nr_entries
)
970 /* Check for any invalid entries */
971 for (i
= 0; i
< nvec
; i
++) {
972 if (entries
[i
].entry
>= nr_entries
)
973 return -EINVAL
; /* invalid entry */
974 for (j
= i
+ 1; j
< nvec
; j
++) {
975 if (entries
[i
].entry
== entries
[j
].entry
)
976 return -EINVAL
; /* duplicate entry */
979 WARN_ON(!!dev
->msix_enabled
);
981 /* Check whether driver already requested for MSI irq */
982 if (dev
->msi_enabled
) {
983 dev_info(&dev
->dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
986 status
= msix_capability_init(dev
, entries
, nvec
);
989 EXPORT_SYMBOL(pci_enable_msix
);
991 void pci_msix_shutdown(struct pci_dev
*dev
)
993 struct msi_desc
*entry
;
995 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
998 /* Return the device with MSI-X masked as initial states */
999 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
1000 /* Keep cached states to be restored */
1001 arch_msix_mask_irq(entry
, 1);
1004 msix_set_enable(dev
, 0);
1005 pci_intx_for_msi(dev
, 1);
1006 dev
->msix_enabled
= 0;
1009 void pci_disable_msix(struct pci_dev
*dev
)
1011 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1014 pci_msix_shutdown(dev
);
1017 EXPORT_SYMBOL(pci_disable_msix
);
1020 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
1021 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1023 * Being called during hotplug remove, from which the device function
1024 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1025 * allocated for this device function, are reclaimed to unused state,
1026 * which may be used later on.
1028 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
)
1030 if (!pci_msi_enable
|| !dev
)
1033 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1037 void pci_no_msi(void)
1043 * pci_msi_enabled - is MSI enabled?
1045 * Returns true if MSI has not been disabled by the command-line option
1048 int pci_msi_enabled(void)
1050 return pci_msi_enable
;
1052 EXPORT_SYMBOL(pci_msi_enabled
);
1054 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
1056 INIT_LIST_HEAD(&dev
->msi_list
);
1058 /* Disable the msi hardware to avoid screaming interrupts
1059 * during boot. This is the power on reset default so
1060 * usually this should be a noop.
1062 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1064 msi_set_enable(dev
, 0);
1066 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1068 msix_set_enable(dev
, 0);
1072 * pci_enable_msi_range - configure device's MSI capability structure
1073 * @dev: device to configure
1074 * @minvec: minimal number of interrupts to configure
1075 * @maxvec: maximum number of interrupts to configure
1077 * This function tries to allocate a maximum possible number of interrupts in a
1078 * range between @minvec and @maxvec. It returns a negative errno if an error
1079 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1080 * and updates the @dev's irq member to the lowest new interrupt number;
1081 * the other interrupt numbers allocated to this device are consecutive.
1083 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
)
1088 if (dev
->current_state
!= PCI_D0
)
1091 WARN_ON(!!dev
->msi_enabled
);
1093 /* Check whether driver already requested MSI-X irqs */
1094 if (dev
->msix_enabled
) {
1096 "can't enable MSI (MSI-X already enabled)\n");
1100 if (maxvec
< minvec
)
1103 nvec
= pci_msi_vec_count(dev
);
1106 else if (nvec
< minvec
)
1108 else if (nvec
> maxvec
)
1112 rc
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSI
);
1115 } else if (rc
> 0) {
1123 rc
= msi_capability_init(dev
, nvec
);
1126 } else if (rc
> 0) {
1135 EXPORT_SYMBOL(pci_enable_msi_range
);
1138 * pci_enable_msix_range - configure device's MSI-X capability structure
1139 * @dev: pointer to the pci_dev data structure of MSI-X device function
1140 * @entries: pointer to an array of MSI-X entries
1141 * @minvec: minimum number of MSI-X irqs requested
1142 * @maxvec: maximum number of MSI-X irqs requested
1144 * Setup the MSI-X capability structure of device function with a maximum
1145 * possible number of interrupts in the range between @minvec and @maxvec
1146 * upon its software driver call to request for MSI-X mode enabled on its
1147 * hardware device function. It returns a negative errno if an error occurs.
1148 * If it succeeds, it returns the actual number of interrupts allocated and
1149 * indicates the successful configuration of MSI-X capability structure
1150 * with new allocated MSI-X interrupts.
1152 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1153 int minvec
, int maxvec
)
1158 if (maxvec
< minvec
)
1162 rc
= pci_enable_msix(dev
, entries
, nvec
);
1165 } else if (rc
> 0) {
1174 EXPORT_SYMBOL(pci_enable_msix_range
);