2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 const char *pci_power_names
[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 EXPORT_SYMBOL_GPL(pci_power_names
);
32 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
34 #ifdef CONFIG_PCI_DOMAINS
35 int pci_domains_supported
= 1;
38 #define DEFAULT_CARDBUS_IO_SIZE (256)
39 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
40 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
41 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
42 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
44 #define DEFAULT_HOTPLUG_IO_SIZE (256)
45 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
46 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
47 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
48 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
50 #ifndef PCI_CACHE_LINE_BYTES
51 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
55 * The default CLS is used if arch didn't set CLS explicitly and not
56 * all pci devices agree on the same value. Arch can override either
57 * the dfl or actual value as it sees fit. Don't forget this is
58 * measured in 32-bit words, not bytes.
60 u8 pci_dfl_cache_line_size __initdata
= PCI_CACHE_LINE_BYTES
>> 2;
61 u8 pci_cache_line_size
;
64 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
65 * @bus: pointer to PCI bus structure to search
67 * Given a PCI bus, returns the highest PCI bus number present in the set
68 * including the given PCI bus and its list of child PCI buses.
70 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
72 struct list_head
*tmp
;
75 max
= bus
->subordinate
;
76 list_for_each(tmp
, &bus
->children
) {
77 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
83 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
85 #ifdef CONFIG_HAS_IOMEM
86 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
89 * Make sure the BAR is actually a memory resource, not an IO resource
91 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
95 return ioremap_nocache(pci_resource_start(pdev
, bar
),
96 pci_resource_len(pdev
, bar
));
98 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
103 * pci_max_busnr - returns maximum PCI bus number
105 * Returns the highest PCI bus number present in the system global list of
108 unsigned char __devinit
111 struct pci_bus
*bus
= NULL
;
112 unsigned char max
, n
;
115 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
116 n
= pci_bus_max_busnr(bus
);
125 #define PCI_FIND_CAP_TTL 48
127 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
128 u8 pos
, int cap
, int *ttl
)
133 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
137 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
143 pos
+= PCI_CAP_LIST_NEXT
;
148 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
151 int ttl
= PCI_FIND_CAP_TTL
;
153 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
156 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
158 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
159 pos
+ PCI_CAP_LIST_NEXT
, cap
);
161 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
163 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
164 unsigned int devfn
, u8 hdr_type
)
168 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
169 if (!(status
& PCI_STATUS_CAP_LIST
))
173 case PCI_HEADER_TYPE_NORMAL
:
174 case PCI_HEADER_TYPE_BRIDGE
:
175 return PCI_CAPABILITY_LIST
;
176 case PCI_HEADER_TYPE_CARDBUS
:
177 return PCI_CB_CAPABILITY_LIST
;
186 * pci_find_capability - query for devices' capabilities
187 * @dev: PCI device to query
188 * @cap: capability code
190 * Tell if a device supports a given PCI capability.
191 * Returns the address of the requested capability structure within the
192 * device's PCI configuration space or 0 in case the device does not
193 * support it. Possible values for @cap:
195 * %PCI_CAP_ID_PM Power Management
196 * %PCI_CAP_ID_AGP Accelerated Graphics Port
197 * %PCI_CAP_ID_VPD Vital Product Data
198 * %PCI_CAP_ID_SLOTID Slot Identification
199 * %PCI_CAP_ID_MSI Message Signalled Interrupts
200 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
201 * %PCI_CAP_ID_PCIX PCI-X
202 * %PCI_CAP_ID_EXP PCI Express
204 int pci_find_capability(struct pci_dev
*dev
, int cap
)
208 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
210 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
216 * pci_bus_find_capability - query for devices' capabilities
217 * @bus: the PCI bus to query
218 * @devfn: PCI device to query
219 * @cap: capability code
221 * Like pci_find_capability() but works for pci devices that do not have a
222 * pci_dev structure set up yet.
224 * Returns the address of the requested capability structure within the
225 * device's PCI configuration space or 0 in case the device does not
228 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
233 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
235 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
237 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
243 * pci_find_ext_capability - Find an extended capability
244 * @dev: PCI device to query
245 * @cap: capability code
247 * Returns the address of the requested extended capability structure
248 * within the device's PCI configuration space or 0 if the device does
249 * not support it. Possible values for @cap:
251 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
252 * %PCI_EXT_CAP_ID_VC Virtual Channel
253 * %PCI_EXT_CAP_ID_DSN Device Serial Number
254 * %PCI_EXT_CAP_ID_PWR Power Budgeting
256 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
260 int pos
= PCI_CFG_SPACE_SIZE
;
262 /* minimum 8 bytes per capability */
263 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
265 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
268 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
272 * If we have no capabilities, this is indicated by cap ID,
273 * cap version and next pointer all being 0.
279 if (PCI_EXT_CAP_ID(header
) == cap
)
282 pos
= PCI_EXT_CAP_NEXT(header
);
283 if (pos
< PCI_CFG_SPACE_SIZE
)
286 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
292 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
294 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
296 int rc
, ttl
= PCI_FIND_CAP_TTL
;
299 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
300 mask
= HT_3BIT_CAP_MASK
;
302 mask
= HT_5BIT_CAP_MASK
;
304 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
305 PCI_CAP_ID_HT
, &ttl
);
307 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
308 if (rc
!= PCIBIOS_SUCCESSFUL
)
311 if ((cap
& mask
) == ht_cap
)
314 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
315 pos
+ PCI_CAP_LIST_NEXT
,
316 PCI_CAP_ID_HT
, &ttl
);
322 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
323 * @dev: PCI device to query
324 * @pos: Position from which to continue searching
325 * @ht_cap: Hypertransport capability code
327 * To be used in conjunction with pci_find_ht_capability() to search for
328 * all capabilities matching @ht_cap. @pos should always be a value returned
329 * from pci_find_ht_capability().
331 * NB. To be 100% safe against broken PCI devices, the caller should take
332 * steps to avoid an infinite loop.
334 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
336 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
338 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
341 * pci_find_ht_capability - query a device's Hypertransport capabilities
342 * @dev: PCI device to query
343 * @ht_cap: Hypertransport capability code
345 * Tell if a device supports a given Hypertransport capability.
346 * Returns an address within the device's PCI configuration space
347 * or 0 in case the device does not support the request capability.
348 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
349 * which has a Hypertransport capability matching @ht_cap.
351 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
355 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
357 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
361 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
364 * pci_find_parent_resource - return resource region of parent bus of given region
365 * @dev: PCI device structure contains resources to be searched
366 * @res: child resource record for which parent is sought
368 * For given resource region of given device, return the resource
369 * region of parent bus the given region is contained in or where
370 * it should be allocated from.
373 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
375 const struct pci_bus
*bus
= dev
->bus
;
377 struct resource
*best
= NULL
;
379 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
380 struct resource
*r
= bus
->resource
[i
];
383 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
384 continue; /* Not contained */
385 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
386 continue; /* Wrong type */
387 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
388 return r
; /* Exact match */
389 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
390 best
= r
; /* Approximating prefetchable by non-prefetchable */
396 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
397 * @dev: PCI device to have its BARs restored
399 * Restore the BAR values for a given device, so as to make it
400 * accessible by its driver.
403 pci_restore_bars(struct pci_dev
*dev
)
407 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
408 pci_update_resource(dev
, i
);
411 static struct pci_platform_pm_ops
*pci_platform_pm
;
413 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
415 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
416 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
418 pci_platform_pm
= ops
;
422 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
424 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
427 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
430 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
433 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
435 return pci_platform_pm
?
436 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
439 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
441 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
444 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
446 return pci_platform_pm
?
447 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
451 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
453 * @dev: PCI device to handle.
454 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
457 * -EINVAL if the requested state is invalid.
458 * -EIO if device does not support PCI PM or its PM capabilities register has a
459 * wrong version, or device doesn't support the requested state.
460 * 0 if device already is in the requested state.
461 * 0 if device's power state has been successfully changed.
463 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
466 bool need_restore
= false;
468 /* Check if we're already there */
469 if (dev
->current_state
== state
)
475 if (state
< PCI_D0
|| state
> PCI_D3hot
)
478 /* Validate current state:
479 * Can enter D0 from any state, but if we can only go deeper
480 * to sleep if we're already in a low power state
482 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
483 && dev
->current_state
> state
) {
484 dev_err(&dev
->dev
, "invalid power transition "
485 "(from state %d to %d)\n", dev
->current_state
, state
);
489 /* check if this device supports the desired state */
490 if ((state
== PCI_D1
&& !dev
->d1_support
)
491 || (state
== PCI_D2
&& !dev
->d2_support
))
494 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
496 /* If we're (effectively) in D3, force entire word to 0.
497 * This doesn't affect PME_Status, disables PME_En, and
498 * sets PowerState to 0.
500 switch (dev
->current_state
) {
504 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
509 case PCI_UNKNOWN
: /* Boot-up */
510 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
511 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
513 /* Fall-through: force to D0 */
519 /* enter specified state */
520 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
522 /* Mandatory power management transition delays */
523 /* see PCI PM 1.1 5.6.1 table 18 */
524 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
525 msleep(pci_pm_d3_delay
);
526 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
527 udelay(PCI_PM_D2_DELAY
);
529 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
530 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
531 if (dev
->current_state
!= state
&& printk_ratelimit())
532 dev_info(&dev
->dev
, "Refused to change power state, "
533 "currently in D%d\n", dev
->current_state
);
535 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
536 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
537 * from D3hot to D0 _may_ perform an internal reset, thereby
538 * going to "D0 Uninitialized" rather than "D0 Initialized".
539 * For example, at least some versions of the 3c905B and the
540 * 3c556B exhibit this behaviour.
542 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
543 * devices in a D3hot state at boot. Consequently, we need to
544 * restore at least the BARs so that the device will be
545 * accessible to its driver.
548 pci_restore_bars(dev
);
551 pcie_aspm_pm_state_change(dev
->bus
->self
);
557 * pci_update_current_state - Read PCI power state of given device from its
558 * PCI PM registers and cache it
559 * @dev: PCI device to handle.
560 * @state: State to cache in case the device doesn't have the PM capability
562 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
567 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
568 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
570 dev
->current_state
= state
;
575 * pci_platform_power_transition - Use platform to change device power state
576 * @dev: PCI device to handle.
577 * @state: State to put the device into.
579 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
583 if (platform_pci_power_manageable(dev
)) {
584 error
= platform_pci_set_power_state(dev
, state
);
586 pci_update_current_state(dev
, state
);
589 /* Fall back to PCI_D0 if native PM is not supported */
591 dev
->current_state
= PCI_D0
;
598 * __pci_start_power_transition - Start power transition of a PCI device
599 * @dev: PCI device to handle.
600 * @state: State to put the device into.
602 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
605 pci_platform_power_transition(dev
, PCI_D0
);
609 * __pci_complete_power_transition - Complete power transition of a PCI device
610 * @dev: PCI device to handle.
611 * @state: State to put the device into.
613 * This function should not be called directly by device drivers.
615 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
617 return state
> PCI_D0
?
618 pci_platform_power_transition(dev
, state
) : -EINVAL
;
620 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
623 * pci_set_power_state - Set the power state of a PCI device
624 * @dev: PCI device to handle.
625 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
627 * Transition a device to a new power state, using the platform firmware and/or
628 * the device's PCI PM registers.
631 * -EINVAL if the requested state is invalid.
632 * -EIO if device does not support PCI PM or its PM capabilities register has a
633 * wrong version, or device doesn't support the requested state.
634 * 0 if device already is in the requested state.
635 * 0 if device's power state has been successfully changed.
637 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
641 /* bound the state we're entering */
642 if (state
> PCI_D3hot
)
644 else if (state
< PCI_D0
)
646 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
648 * If the device or the parent bridge do not support PCI PM,
649 * ignore the request if we're doing anything other than putting
650 * it into D0 (which would only happen on boot).
654 /* Check if we're already there */
655 if (dev
->current_state
== state
)
658 __pci_start_power_transition(dev
, state
);
660 /* This device is quirked not to be put into D3, so
661 don't put it in D3 */
662 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
665 error
= pci_raw_set_power_state(dev
, state
);
667 if (!__pci_complete_power_transition(dev
, state
))
674 * pci_choose_state - Choose the power state of a PCI device
675 * @dev: PCI device to be suspended
676 * @state: target sleep state for the whole system. This is the value
677 * that is passed to suspend() function.
679 * Returns PCI power state suitable for given device and given system
683 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
687 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
690 ret
= platform_pci_choose_state(dev
);
691 if (ret
!= PCI_POWER_ERROR
)
694 switch (state
.event
) {
697 case PM_EVENT_FREEZE
:
698 case PM_EVENT_PRETHAW
:
699 /* REVISIT both freeze and pre-thaw "should" use D0 */
700 case PM_EVENT_SUSPEND
:
701 case PM_EVENT_HIBERNATE
:
704 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
711 EXPORT_SYMBOL(pci_choose_state
);
713 #define PCI_EXP_SAVE_REGS 7
715 #define pcie_cap_has_devctl(type, flags) 1
716 #define pcie_cap_has_lnkctl(type, flags) \
717 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
718 (type == PCI_EXP_TYPE_ROOT_PORT || \
719 type == PCI_EXP_TYPE_ENDPOINT || \
720 type == PCI_EXP_TYPE_LEG_END))
721 #define pcie_cap_has_sltctl(type, flags) \
722 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
723 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
724 (type == PCI_EXP_TYPE_DOWNSTREAM && \
725 (flags & PCI_EXP_FLAGS_SLOT))))
726 #define pcie_cap_has_rtctl(type, flags) \
727 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
728 (type == PCI_EXP_TYPE_ROOT_PORT || \
729 type == PCI_EXP_TYPE_RC_EC))
730 #define pcie_cap_has_devctl2(type, flags) \
731 ((flags & PCI_EXP_FLAGS_VERS) > 1)
732 #define pcie_cap_has_lnkctl2(type, flags) \
733 ((flags & PCI_EXP_FLAGS_VERS) > 1)
734 #define pcie_cap_has_sltctl2(type, flags) \
735 ((flags & PCI_EXP_FLAGS_VERS) > 1)
737 static int pci_save_pcie_state(struct pci_dev
*dev
)
740 struct pci_cap_saved_state
*save_state
;
744 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
748 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
750 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
753 cap
= (u16
*)&save_state
->data
[0];
755 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
757 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
758 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
759 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
760 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
761 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
762 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
763 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
764 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
765 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
766 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
767 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
768 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
769 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
770 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
775 static void pci_restore_pcie_state(struct pci_dev
*dev
)
778 struct pci_cap_saved_state
*save_state
;
782 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
783 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
784 if (!save_state
|| pos
<= 0)
786 cap
= (u16
*)&save_state
->data
[0];
788 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
790 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
791 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
792 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
793 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
794 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
795 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
796 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
797 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
798 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
799 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
800 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
801 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
802 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
803 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
807 static int pci_save_pcix_state(struct pci_dev
*dev
)
810 struct pci_cap_saved_state
*save_state
;
812 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
816 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
818 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
822 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
827 static void pci_restore_pcix_state(struct pci_dev
*dev
)
830 struct pci_cap_saved_state
*save_state
;
833 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
834 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
835 if (!save_state
|| pos
<= 0)
837 cap
= (u16
*)&save_state
->data
[0];
839 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
844 * pci_save_state - save the PCI configuration space of a device before suspending
845 * @dev: - PCI device that we're dealing with
848 pci_save_state(struct pci_dev
*dev
)
851 /* XXX: 100% dword access ok here? */
852 for (i
= 0; i
< 16; i
++)
853 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
854 dev
->state_saved
= true;
855 if ((i
= pci_save_pcie_state(dev
)) != 0)
857 if ((i
= pci_save_pcix_state(dev
)) != 0)
863 * pci_restore_state - Restore the saved state of a PCI device
864 * @dev: - PCI device that we're dealing with
867 pci_restore_state(struct pci_dev
*dev
)
872 if (!dev
->state_saved
)
875 /* PCI Express register must be restored first */
876 pci_restore_pcie_state(dev
);
879 * The Base Address register should be programmed before the command
882 for (i
= 15; i
>= 0; i
--) {
883 pci_read_config_dword(dev
, i
* 4, &val
);
884 if (val
!= dev
->saved_config_space
[i
]) {
885 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
886 "space at offset %#x (was %#x, writing %#x)\n",
887 i
, val
, (int)dev
->saved_config_space
[i
]);
888 pci_write_config_dword(dev
,i
* 4,
889 dev
->saved_config_space
[i
]);
892 pci_restore_pcix_state(dev
);
893 pci_restore_msi_state(dev
);
894 pci_restore_iov_state(dev
);
896 dev
->state_saved
= false;
901 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
905 err
= pci_set_power_state(dev
, PCI_D0
);
906 if (err
< 0 && err
!= -EIO
)
908 err
= pcibios_enable_device(dev
, bars
);
911 pci_fixup_device(pci_fixup_enable
, dev
);
917 * pci_reenable_device - Resume abandoned device
918 * @dev: PCI device to be resumed
920 * Note this function is a backend of pci_default_resume and is not supposed
921 * to be called by normal code, write proper resume handler and use it instead.
923 int pci_reenable_device(struct pci_dev
*dev
)
925 if (pci_is_enabled(dev
))
926 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
930 static int __pci_enable_device_flags(struct pci_dev
*dev
,
931 resource_size_t flags
)
936 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
937 return 0; /* already enabled */
939 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
940 if (dev
->resource
[i
].flags
& flags
)
943 err
= do_pci_enable_device(dev
, bars
);
945 atomic_dec(&dev
->enable_cnt
);
950 * pci_enable_device_io - Initialize a device for use with IO space
951 * @dev: PCI device to be initialized
953 * Initialize device before it's used by a driver. Ask low-level code
954 * to enable I/O resources. Wake up the device if it was suspended.
955 * Beware, this function can fail.
957 int pci_enable_device_io(struct pci_dev
*dev
)
959 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
963 * pci_enable_device_mem - Initialize a device for use with Memory space
964 * @dev: PCI device to be initialized
966 * Initialize device before it's used by a driver. Ask low-level code
967 * to enable Memory resources. Wake up the device if it was suspended.
968 * Beware, this function can fail.
970 int pci_enable_device_mem(struct pci_dev
*dev
)
972 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
976 * pci_enable_device - Initialize device before it's used by a driver.
977 * @dev: PCI device to be initialized
979 * Initialize device before it's used by a driver. Ask low-level code
980 * to enable I/O and memory. Wake up the device if it was suspended.
981 * Beware, this function can fail.
983 * Note we don't actually enable the device many times if we call
984 * this function repeatedly (we just increment the count).
986 int pci_enable_device(struct pci_dev
*dev
)
988 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
992 * Managed PCI resources. This manages device on/off, intx/msi/msix
993 * on/off and BAR regions. pci_dev itself records msi/msix status, so
994 * there's no need to track it separately. pci_devres is initialized
995 * when a device is enabled using managed PCI device enable interface.
998 unsigned int enabled
:1;
999 unsigned int pinned
:1;
1000 unsigned int orig_intx
:1;
1001 unsigned int restore_intx
:1;
1005 static void pcim_release(struct device
*gendev
, void *res
)
1007 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1008 struct pci_devres
*this = res
;
1011 if (dev
->msi_enabled
)
1012 pci_disable_msi(dev
);
1013 if (dev
->msix_enabled
)
1014 pci_disable_msix(dev
);
1016 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1017 if (this->region_mask
& (1 << i
))
1018 pci_release_region(dev
, i
);
1020 if (this->restore_intx
)
1021 pci_intx(dev
, this->orig_intx
);
1023 if (this->enabled
&& !this->pinned
)
1024 pci_disable_device(dev
);
1027 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1029 struct pci_devres
*dr
, *new_dr
;
1031 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1035 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1038 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1041 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1043 if (pci_is_managed(pdev
))
1044 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1049 * pcim_enable_device - Managed pci_enable_device()
1050 * @pdev: PCI device to be initialized
1052 * Managed pci_enable_device().
1054 int pcim_enable_device(struct pci_dev
*pdev
)
1056 struct pci_devres
*dr
;
1059 dr
= get_pci_dr(pdev
);
1065 rc
= pci_enable_device(pdev
);
1067 pdev
->is_managed
= 1;
1074 * pcim_pin_device - Pin managed PCI device
1075 * @pdev: PCI device to pin
1077 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1078 * driver detach. @pdev must have been enabled with
1079 * pcim_enable_device().
1081 void pcim_pin_device(struct pci_dev
*pdev
)
1083 struct pci_devres
*dr
;
1085 dr
= find_pci_dr(pdev
);
1086 WARN_ON(!dr
|| !dr
->enabled
);
1092 * pcibios_disable_device - disable arch specific PCI resources for device dev
1093 * @dev: the PCI device to disable
1095 * Disables architecture specific PCI resources for the device. This
1096 * is the default implementation. Architecture implementations can
1099 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1101 static void do_pci_disable_device(struct pci_dev
*dev
)
1105 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1106 if (pci_command
& PCI_COMMAND_MASTER
) {
1107 pci_command
&= ~PCI_COMMAND_MASTER
;
1108 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1111 pcibios_disable_device(dev
);
1115 * pci_disable_enabled_device - Disable device without updating enable_cnt
1116 * @dev: PCI device to disable
1118 * NOTE: This function is a backend of PCI power management routines and is
1119 * not supposed to be called drivers.
1121 void pci_disable_enabled_device(struct pci_dev
*dev
)
1123 if (pci_is_enabled(dev
))
1124 do_pci_disable_device(dev
);
1128 * pci_disable_device - Disable PCI device after use
1129 * @dev: PCI device to be disabled
1131 * Signal to the system that the PCI device is not in use by the system
1132 * anymore. This only involves disabling PCI bus-mastering, if active.
1134 * Note we don't actually disable the device until all callers of
1135 * pci_device_enable() have called pci_device_disable().
1138 pci_disable_device(struct pci_dev
*dev
)
1140 struct pci_devres
*dr
;
1142 dr
= find_pci_dr(dev
);
1146 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1149 do_pci_disable_device(dev
);
1151 dev
->is_busmaster
= 0;
1155 * pcibios_set_pcie_reset_state - set reset state for device dev
1156 * @dev: the PCI-E device reset
1157 * @state: Reset state to enter into
1160 * Sets the PCI-E reset state for the device. This is the default
1161 * implementation. Architecture implementations can override this.
1163 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1164 enum pcie_reset_state state
)
1170 * pci_set_pcie_reset_state - set reset state for device dev
1171 * @dev: the PCI-E device reset
1172 * @state: Reset state to enter into
1175 * Sets the PCI reset state for the device.
1177 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1179 return pcibios_set_pcie_reset_state(dev
, state
);
1183 * pci_pme_capable - check the capability of PCI device to generate PME#
1184 * @dev: PCI device to handle.
1185 * @state: PCI state from which device will issue PME#.
1187 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1192 return !!(dev
->pme_support
& (1 << state
));
1196 * pci_pme_active - enable or disable PCI device's PME# function
1197 * @dev: PCI device to handle.
1198 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1200 * The caller must verify that the device is capable of generating PME# before
1201 * calling this function with @enable equal to 'true'.
1203 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1210 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1211 /* Clear PME_Status by writing 1 to it and enable PME# */
1212 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1214 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1216 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1218 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1219 enable
? "enabled" : "disabled");
1223 * pci_enable_wake - enable PCI device as wakeup event source
1224 * @dev: PCI device affected
1225 * @state: PCI state from which device will issue wakeup events
1226 * @enable: True to enable event generation; false to disable
1228 * This enables the device as a wakeup event source, or disables it.
1229 * When such events involves platform-specific hooks, those hooks are
1230 * called automatically by this routine.
1232 * Devices with legacy power management (no standard PCI PM capabilities)
1233 * always require such platform hooks.
1236 * 0 is returned on success
1237 * -EINVAL is returned if device is not supposed to wake up the system
1238 * Error code depending on the platform is returned if both the platform and
1239 * the native mechanism fail to enable the generation of wake-up events
1241 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
1245 if (enable
&& !device_may_wakeup(&dev
->dev
))
1248 /* Don't do the same thing twice in a row for one device. */
1249 if (!!enable
== !!dev
->wakeup_prepared
)
1253 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1254 * Anderson we should be doing PME# wake enable followed by ACPI wake
1255 * enable. To disable wake-up we call the platform first, for symmetry.
1261 if (pci_pme_capable(dev
, state
))
1262 pci_pme_active(dev
, true);
1265 error
= platform_pci_sleep_wake(dev
, true);
1269 dev
->wakeup_prepared
= true;
1271 platform_pci_sleep_wake(dev
, false);
1272 pci_pme_active(dev
, false);
1273 dev
->wakeup_prepared
= false;
1280 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1281 * @dev: PCI device to prepare
1282 * @enable: True to enable wake-up event generation; false to disable
1284 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1285 * and this function allows them to set that up cleanly - pci_enable_wake()
1286 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1287 * ordering constraints.
1289 * This function only returns error code if the device is not capable of
1290 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1291 * enable wake-up power for it.
1293 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1295 return pci_pme_capable(dev
, PCI_D3cold
) ?
1296 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1297 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1301 * pci_target_state - find an appropriate low power state for a given PCI dev
1304 * Use underlying platform code to find a supported low power state for @dev.
1305 * If the platform can't manage @dev, return the deepest state from which it
1306 * can generate wake events, based on any available PME info.
1308 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1310 pci_power_t target_state
= PCI_D3hot
;
1312 if (platform_pci_power_manageable(dev
)) {
1314 * Call the platform to choose the target state of the device
1315 * and enable wake-up from this state if supported.
1317 pci_power_t state
= platform_pci_choose_state(dev
);
1320 case PCI_POWER_ERROR
:
1325 if (pci_no_d1d2(dev
))
1328 target_state
= state
;
1330 } else if (!dev
->pm_cap
) {
1331 target_state
= PCI_D0
;
1332 } else if (device_may_wakeup(&dev
->dev
)) {
1334 * Find the deepest state from which the device can generate
1335 * wake-up events, make it the target state and enable device
1338 if (dev
->pme_support
) {
1340 && !(dev
->pme_support
& (1 << target_state
)))
1345 return target_state
;
1349 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1350 * @dev: Device to handle.
1352 * Choose the power state appropriate for the device depending on whether
1353 * it can wake up the system and/or is power manageable by the platform
1354 * (PCI_D3hot is the default) and put the device into that state.
1356 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1358 pci_power_t target_state
= pci_target_state(dev
);
1361 if (target_state
== PCI_POWER_ERROR
)
1364 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1366 error
= pci_set_power_state(dev
, target_state
);
1369 pci_enable_wake(dev
, target_state
, false);
1375 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1376 * @dev: Device to handle.
1378 * Disable device's sytem wake-up capability and put it into D0.
1380 int pci_back_from_sleep(struct pci_dev
*dev
)
1382 pci_enable_wake(dev
, PCI_D0
, false);
1383 return pci_set_power_state(dev
, PCI_D0
);
1387 * pci_pm_init - Initialize PM functions of given PCI device
1388 * @dev: PCI device to handle.
1390 void pci_pm_init(struct pci_dev
*dev
)
1395 dev
->wakeup_prepared
= false;
1398 /* find PCI PM capability in list */
1399 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1402 /* Check device's ability to generate PME# */
1403 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1405 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1406 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1407 pmc
& PCI_PM_CAP_VER_MASK
);
1413 dev
->d1_support
= false;
1414 dev
->d2_support
= false;
1415 if (!pci_no_d1d2(dev
)) {
1416 if (pmc
& PCI_PM_CAP_D1
)
1417 dev
->d1_support
= true;
1418 if (pmc
& PCI_PM_CAP_D2
)
1419 dev
->d2_support
= true;
1421 if (dev
->d1_support
|| dev
->d2_support
)
1422 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1423 dev
->d1_support
? " D1" : "",
1424 dev
->d2_support
? " D2" : "");
1427 pmc
&= PCI_PM_CAP_PME_MASK
;
1429 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1430 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1431 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1432 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1433 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1434 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1435 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1437 * Make device's PM flags reflect the wake-up capability, but
1438 * let the user space enable it to wake up the system as needed.
1440 device_set_wakeup_capable(&dev
->dev
, true);
1441 device_set_wakeup_enable(&dev
->dev
, false);
1442 /* Disable the PME# generation functionality */
1443 pci_pme_active(dev
, false);
1445 dev
->pme_support
= 0;
1450 * platform_pci_wakeup_init - init platform wakeup if present
1453 * Some devices don't have PCI PM caps but can still generate wakeup
1454 * events through platform methods (like ACPI events). If @dev supports
1455 * platform wakeup events, set the device flag to indicate as much. This
1456 * may be redundant if the device also supports PCI PM caps, but double
1457 * initialization should be safe in that case.
1459 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1461 if (!platform_pci_can_wakeup(dev
))
1464 device_set_wakeup_capable(&dev
->dev
, true);
1465 device_set_wakeup_enable(&dev
->dev
, false);
1466 platform_pci_sleep_wake(dev
, false);
1470 * pci_add_save_buffer - allocate buffer for saving given capability registers
1471 * @dev: the PCI device
1472 * @cap: the capability to allocate the buffer for
1473 * @size: requested size of the buffer
1475 static int pci_add_cap_save_buffer(
1476 struct pci_dev
*dev
, char cap
, unsigned int size
)
1479 struct pci_cap_saved_state
*save_state
;
1481 pos
= pci_find_capability(dev
, cap
);
1485 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1489 save_state
->cap_nr
= cap
;
1490 pci_add_saved_cap(dev
, save_state
);
1496 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1497 * @dev: the PCI device
1499 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1503 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1504 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1507 "unable to preallocate PCI Express save buffer\n");
1509 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1512 "unable to preallocate PCI-X save buffer\n");
1516 * pci_enable_ari - enable ARI forwarding if hardware support it
1517 * @dev: the PCI device
1519 void pci_enable_ari(struct pci_dev
*dev
)
1524 struct pci_dev
*bridge
;
1526 if (!dev
->is_pcie
|| dev
->devfn
)
1529 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1533 bridge
= dev
->bus
->self
;
1534 if (!bridge
|| !bridge
->is_pcie
)
1537 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1541 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1542 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1545 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1546 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1547 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1549 bridge
->ari_enabled
= 1;
1553 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1554 * @dev: the PCI device
1555 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1557 * Perform INTx swizzling for a device behind one level of bridge. This is
1558 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1559 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1560 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1561 * the PCI Express Base Specification, Revision 2.1)
1563 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1567 if (pci_ari_enabled(dev
->bus
))
1570 slot
= PCI_SLOT(dev
->devfn
);
1572 return (((pin
- 1) + slot
) % 4) + 1;
1576 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1584 while (!pci_is_root_bus(dev
->bus
)) {
1585 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1586 dev
= dev
->bus
->self
;
1593 * pci_common_swizzle - swizzle INTx all the way to root bridge
1594 * @dev: the PCI device
1595 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1597 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1598 * bridges all the way up to a PCI root bus.
1600 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1604 while (!pci_is_root_bus(dev
->bus
)) {
1605 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1606 dev
= dev
->bus
->self
;
1609 return PCI_SLOT(dev
->devfn
);
1613 * pci_release_region - Release a PCI bar
1614 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1615 * @bar: BAR to release
1617 * Releases the PCI I/O and memory resources previously reserved by a
1618 * successful call to pci_request_region. Call this function only
1619 * after all use of the PCI regions has ceased.
1621 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1623 struct pci_devres
*dr
;
1625 if (pci_resource_len(pdev
, bar
) == 0)
1627 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1628 release_region(pci_resource_start(pdev
, bar
),
1629 pci_resource_len(pdev
, bar
));
1630 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1631 release_mem_region(pci_resource_start(pdev
, bar
),
1632 pci_resource_len(pdev
, bar
));
1634 dr
= find_pci_dr(pdev
);
1636 dr
->region_mask
&= ~(1 << bar
);
1640 * __pci_request_region - Reserved PCI I/O and memory resource
1641 * @pdev: PCI device whose resources are to be reserved
1642 * @bar: BAR to be reserved
1643 * @res_name: Name to be associated with resource.
1644 * @exclusive: whether the region access is exclusive or not
1646 * Mark the PCI region associated with PCI device @pdev BR @bar as
1647 * being reserved by owner @res_name. Do not access any
1648 * address inside the PCI regions unless this call returns
1651 * If @exclusive is set, then the region is marked so that userspace
1652 * is explicitly not allowed to map the resource via /dev/mem or
1653 * sysfs MMIO access.
1655 * Returns 0 on success, or %EBUSY on error. A warning
1656 * message is also printed on failure.
1658 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1661 struct pci_devres
*dr
;
1663 if (pci_resource_len(pdev
, bar
) == 0)
1666 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1667 if (!request_region(pci_resource_start(pdev
, bar
),
1668 pci_resource_len(pdev
, bar
), res_name
))
1671 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1672 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1673 pci_resource_len(pdev
, bar
), res_name
,
1678 dr
= find_pci_dr(pdev
);
1680 dr
->region_mask
|= 1 << bar
;
1685 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1687 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1688 &pdev
->resource
[bar
]);
1693 * pci_request_region - Reserve PCI I/O and memory resource
1694 * @pdev: PCI device whose resources are to be reserved
1695 * @bar: BAR to be reserved
1696 * @res_name: Name to be associated with resource
1698 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1699 * being reserved by owner @res_name. Do not access any
1700 * address inside the PCI regions unless this call returns
1703 * Returns 0 on success, or %EBUSY on error. A warning
1704 * message is also printed on failure.
1706 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1708 return __pci_request_region(pdev
, bar
, res_name
, 0);
1712 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1713 * @pdev: PCI device whose resources are to be reserved
1714 * @bar: BAR to be reserved
1715 * @res_name: Name to be associated with resource.
1717 * Mark the PCI region associated with PCI device @pdev BR @bar as
1718 * being reserved by owner @res_name. Do not access any
1719 * address inside the PCI regions unless this call returns
1722 * Returns 0 on success, or %EBUSY on error. A warning
1723 * message is also printed on failure.
1725 * The key difference that _exclusive makes it that userspace is
1726 * explicitly not allowed to map the resource via /dev/mem or
1729 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1731 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1734 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1735 * @pdev: PCI device whose resources were previously reserved
1736 * @bars: Bitmask of BARs to be released
1738 * Release selected PCI I/O and memory resources previously reserved.
1739 * Call this function only after all use of the PCI regions has ceased.
1741 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1745 for (i
= 0; i
< 6; i
++)
1746 if (bars
& (1 << i
))
1747 pci_release_region(pdev
, i
);
1750 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1751 const char *res_name
, int excl
)
1755 for (i
= 0; i
< 6; i
++)
1756 if (bars
& (1 << i
))
1757 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1763 if (bars
& (1 << i
))
1764 pci_release_region(pdev
, i
);
1771 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1772 * @pdev: PCI device whose resources are to be reserved
1773 * @bars: Bitmask of BARs to be requested
1774 * @res_name: Name to be associated with resource
1776 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1777 const char *res_name
)
1779 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1782 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1783 int bars
, const char *res_name
)
1785 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1786 IORESOURCE_EXCLUSIVE
);
1790 * pci_release_regions - Release reserved PCI I/O and memory resources
1791 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1793 * Releases all PCI I/O and memory resources previously reserved by a
1794 * successful call to pci_request_regions. Call this function only
1795 * after all use of the PCI regions has ceased.
1798 void pci_release_regions(struct pci_dev
*pdev
)
1800 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1804 * pci_request_regions - Reserved PCI I/O and memory resources
1805 * @pdev: PCI device whose resources are to be reserved
1806 * @res_name: Name to be associated with resource.
1808 * Mark all PCI regions associated with PCI device @pdev as
1809 * being reserved by owner @res_name. Do not access any
1810 * address inside the PCI regions unless this call returns
1813 * Returns 0 on success, or %EBUSY on error. A warning
1814 * message is also printed on failure.
1816 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1818 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1822 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1823 * @pdev: PCI device whose resources are to be reserved
1824 * @res_name: Name to be associated with resource.
1826 * Mark all PCI regions associated with PCI device @pdev as
1827 * being reserved by owner @res_name. Do not access any
1828 * address inside the PCI regions unless this call returns
1831 * pci_request_regions_exclusive() will mark the region so that
1832 * /dev/mem and the sysfs MMIO access will not be allowed.
1834 * Returns 0 on success, or %EBUSY on error. A warning
1835 * message is also printed on failure.
1837 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1839 return pci_request_selected_regions_exclusive(pdev
,
1840 ((1 << 6) - 1), res_name
);
1843 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1847 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1849 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1851 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1852 if (cmd
!= old_cmd
) {
1853 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1854 enable
? "enabling" : "disabling");
1855 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1857 dev
->is_busmaster
= enable
;
1861 * pci_set_master - enables bus-mastering for device dev
1862 * @dev: the PCI device to enable
1864 * Enables bus-mastering on the device and calls pcibios_set_master()
1865 * to do the needed arch specific settings.
1867 void pci_set_master(struct pci_dev
*dev
)
1869 __pci_set_master(dev
, true);
1870 pcibios_set_master(dev
);
1874 * pci_clear_master - disables bus-mastering for device dev
1875 * @dev: the PCI device to disable
1877 void pci_clear_master(struct pci_dev
*dev
)
1879 __pci_set_master(dev
, false);
1882 #ifdef PCI_DISABLE_MWI
1883 int pci_set_mwi(struct pci_dev
*dev
)
1888 int pci_try_set_mwi(struct pci_dev
*dev
)
1893 void pci_clear_mwi(struct pci_dev
*dev
)
1900 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1901 * @dev: the PCI device for which MWI is to be enabled
1903 * Helper function for pci_set_mwi.
1904 * Originally copied from drivers/net/acenic.c.
1905 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1907 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1910 pci_set_cacheline_size(struct pci_dev
*dev
)
1914 if (!pci_cache_line_size
)
1915 return -EINVAL
; /* The system doesn't support MWI. */
1917 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1918 equal to or multiple of the right value. */
1919 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1920 if (cacheline_size
>= pci_cache_line_size
&&
1921 (cacheline_size
% pci_cache_line_size
) == 0)
1924 /* Write the correct value. */
1925 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1927 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1928 if (cacheline_size
== pci_cache_line_size
)
1931 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1932 "supported\n", pci_cache_line_size
<< 2);
1938 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1939 * @dev: the PCI device for which MWI is enabled
1941 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1943 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1946 pci_set_mwi(struct pci_dev
*dev
)
1951 rc
= pci_set_cacheline_size(dev
);
1955 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1956 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1957 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1958 cmd
|= PCI_COMMAND_INVALIDATE
;
1959 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1966 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1967 * @dev: the PCI device for which MWI is enabled
1969 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1970 * Callers are not required to check the return value.
1972 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1974 int pci_try_set_mwi(struct pci_dev
*dev
)
1976 int rc
= pci_set_mwi(dev
);
1981 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1982 * @dev: the PCI device to disable
1984 * Disables PCI Memory-Write-Invalidate transaction on the device
1987 pci_clear_mwi(struct pci_dev
*dev
)
1991 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1992 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1993 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1994 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1997 #endif /* ! PCI_DISABLE_MWI */
2000 * pci_intx - enables/disables PCI INTx for device dev
2001 * @pdev: the PCI device to operate on
2002 * @enable: boolean: whether to enable or disable PCI INTx
2004 * Enables/disables PCI INTx for device dev
2007 pci_intx(struct pci_dev
*pdev
, int enable
)
2009 u16 pci_command
, new;
2011 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2014 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2016 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2019 if (new != pci_command
) {
2020 struct pci_devres
*dr
;
2022 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2024 dr
= find_pci_dr(pdev
);
2025 if (dr
&& !dr
->restore_intx
) {
2026 dr
->restore_intx
= 1;
2027 dr
->orig_intx
= !enable
;
2033 * pci_msi_off - disables any msi or msix capabilities
2034 * @dev: the PCI device to operate on
2036 * If you want to use msi see pci_enable_msi and friends.
2037 * This is a lower level primitive that allows us to disable
2038 * msi operation at the device level.
2040 void pci_msi_off(struct pci_dev
*dev
)
2045 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2047 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2048 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2049 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2051 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2053 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2054 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2055 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2059 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2061 * These can be overridden by arch-specific implementations
2064 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
2066 if (!pci_dma_supported(dev
, mask
))
2069 dev
->dma_mask
= mask
;
2075 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
2077 if (!pci_dma_supported(dev
, mask
))
2080 dev
->dev
.coherent_dma_mask
= mask
;
2086 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2087 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2089 return dma_set_max_seg_size(&dev
->dev
, size
);
2091 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2094 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2095 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2097 return dma_set_seg_boundary(&dev
->dev
, mask
);
2099 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2102 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2109 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2113 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
2114 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2120 /* Wait for Transaction Pending bit clean */
2121 for (i
= 0; i
< 4; i
++) {
2123 msleep((1 << (i
- 1)) * 100);
2125 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
2126 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2130 dev_err(&dev
->dev
, "transaction is not cleared; "
2131 "proceeding with reset anyway\n");
2134 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
,
2135 PCI_EXP_DEVCTL_BCR_FLR
);
2141 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
2148 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2152 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
2153 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2159 /* Wait for Transaction Pending bit clean */
2160 for (i
= 0; i
< 4; i
++) {
2162 msleep((1 << (i
- 1)) * 100);
2164 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
2165 if (!(status
& PCI_AF_STATUS_TP
))
2169 dev_err(&dev
->dev
, "transaction is not cleared; "
2170 "proceeding with reset anyway\n");
2173 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2179 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
2186 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
2187 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
2193 if (dev
->current_state
!= PCI_D0
)
2196 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2198 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2199 msleep(pci_pm_d3_delay
);
2201 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2203 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2204 msleep(pci_pm_d3_delay
);
2209 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
2212 struct pci_dev
*pdev
;
2214 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
2217 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
2224 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
2225 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
2226 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2229 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
2230 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2236 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
2243 pci_block_user_cfg_access(dev
);
2244 /* block PM suspend, driver probe, etc. */
2245 down(&dev
->dev
.sem
);
2248 rc
= pcie_flr(dev
, probe
);
2252 rc
= pci_af_flr(dev
, probe
);
2256 rc
= pci_pm_reset(dev
, probe
);
2260 rc
= pci_parent_bus_reset(dev
, probe
);
2264 pci_unblock_user_cfg_access(dev
);
2271 * __pci_reset_function - reset a PCI device function
2272 * @dev: PCI device to reset
2274 * Some devices allow an individual function to be reset without affecting
2275 * other functions in the same device. The PCI device must be responsive
2276 * to PCI config space in order to use this function.
2278 * The device function is presumed to be unused when this function is called.
2279 * Resetting the device will make the contents of PCI configuration space
2280 * random, so any caller of this must be prepared to reinitialise the
2281 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2284 * Returns 0 if the device function was successfully reset or negative if the
2285 * device doesn't support resetting a single function.
2287 int __pci_reset_function(struct pci_dev
*dev
)
2289 return pci_dev_reset(dev
, 0);
2291 EXPORT_SYMBOL_GPL(__pci_reset_function
);
2294 * pci_probe_reset_function - check whether the device can be safely reset
2295 * @dev: PCI device to reset
2297 * Some devices allow an individual function to be reset without affecting
2298 * other functions in the same device. The PCI device must be responsive
2299 * to PCI config space in order to use this function.
2301 * Returns 0 if the device function can be reset or negative if the
2302 * device doesn't support resetting a single function.
2304 int pci_probe_reset_function(struct pci_dev
*dev
)
2306 return pci_dev_reset(dev
, 1);
2310 * pci_reset_function - quiesce and reset a PCI device function
2311 * @dev: PCI device to reset
2313 * Some devices allow an individual function to be reset without affecting
2314 * other functions in the same device. The PCI device must be responsive
2315 * to PCI config space in order to use this function.
2317 * This function does not just reset the PCI portion of a device, but
2318 * clears all the state associated with the device. This function differs
2319 * from __pci_reset_function in that it saves and restores device state
2322 * Returns 0 if the device function was successfully reset or negative if the
2323 * device doesn't support resetting a single function.
2325 int pci_reset_function(struct pci_dev
*dev
)
2329 rc
= pci_dev_reset(dev
, 1);
2333 pci_save_state(dev
);
2336 * both INTx and MSI are disabled after the Interrupt Disable bit
2337 * is set and the Bus Master bit is cleared.
2339 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2341 rc
= pci_dev_reset(dev
, 0);
2343 pci_restore_state(dev
);
2347 EXPORT_SYMBOL_GPL(pci_reset_function
);
2350 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2351 * @dev: PCI device to query
2353 * Returns mmrbc: maximum designed memory read count in bytes
2354 * or appropriate error value.
2356 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2361 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2365 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2369 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2371 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2374 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2375 * @dev: PCI device to query
2377 * Returns mmrbc: maximum memory read count in bytes
2378 * or appropriate error value.
2380 int pcix_get_mmrbc(struct pci_dev
*dev
)
2385 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2389 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2391 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2395 EXPORT_SYMBOL(pcix_get_mmrbc
);
2398 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2399 * @dev: PCI device to query
2400 * @mmrbc: maximum memory read count in bytes
2401 * valid values are 512, 1024, 2048, 4096
2403 * If possible sets maximum memory read byte count, some bridges have erratas
2404 * that prevent this.
2406 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2408 int cap
, err
= -EINVAL
;
2409 u32 stat
, cmd
, v
, o
;
2411 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2414 v
= ffs(mmrbc
) - 10;
2416 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2420 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2424 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2427 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2431 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2433 if (v
> o
&& dev
->bus
&&
2434 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2437 cmd
&= ~PCI_X_CMD_MAX_READ
;
2439 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2444 EXPORT_SYMBOL(pcix_set_mmrbc
);
2447 * pcie_get_readrq - get PCI Express read request size
2448 * @dev: PCI device to query
2450 * Returns maximum memory read request in bytes
2451 * or appropriate error value.
2453 int pcie_get_readrq(struct pci_dev
*dev
)
2458 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2462 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2464 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2468 EXPORT_SYMBOL(pcie_get_readrq
);
2471 * pcie_set_readrq - set PCI Express maximum memory read request
2472 * @dev: PCI device to query
2473 * @rq: maximum memory read count in bytes
2474 * valid values are 128, 256, 512, 1024, 2048, 4096
2476 * If possible sets maximum read byte count
2478 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2480 int cap
, err
= -EINVAL
;
2483 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2486 v
= (ffs(rq
) - 8) << 12;
2488 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2492 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2496 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2497 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2499 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2505 EXPORT_SYMBOL(pcie_set_readrq
);
2508 * pci_select_bars - Make BAR mask from the type of resource
2509 * @dev: the PCI device for which BAR mask is made
2510 * @flags: resource type mask to be selected
2512 * This helper routine makes bar mask from the type of resource.
2514 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2517 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2518 if (pci_resource_flags(dev
, i
) & flags
)
2524 * pci_resource_bar - get position of the BAR associated with a resource
2525 * @dev: the PCI device
2526 * @resno: the resource number
2527 * @type: the BAR type to be filled in
2529 * Returns BAR position in config space, or 0 if the BAR is invalid.
2531 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2535 if (resno
< PCI_ROM_RESOURCE
) {
2536 *type
= pci_bar_unknown
;
2537 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2538 } else if (resno
== PCI_ROM_RESOURCE
) {
2539 *type
= pci_bar_mem32
;
2540 return dev
->rom_base_reg
;
2541 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2542 /* device specific resource */
2543 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2548 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2553 * pci_set_vga_state - set VGA decode state on device and parents if requested
2554 * @dev: the PCI device
2555 * @decode: true = enable decoding, false = disable decoding
2556 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2557 * @change_bridge: traverse ancestors and change bridges
2559 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
2560 unsigned int command_bits
, bool change_bridge
)
2562 struct pci_bus
*bus
;
2563 struct pci_dev
*bridge
;
2566 WARN_ON(command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
));
2568 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2570 cmd
|= command_bits
;
2572 cmd
&= ~command_bits
;
2573 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2575 if (change_bridge
== false)
2582 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
2585 cmd
|= PCI_BRIDGE_CTL_VGA
;
2587 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
2588 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
2596 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2597 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2598 spinlock_t resource_alignment_lock
= SPIN_LOCK_UNLOCKED
;
2601 * pci_specified_resource_alignment - get resource alignment specified by user.
2602 * @dev: the PCI device to get
2604 * RETURNS: Resource alignment if it is specified.
2605 * Zero if it is not specified.
2607 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2609 int seg
, bus
, slot
, func
, align_order
, count
;
2610 resource_size_t align
= 0;
2613 spin_lock(&resource_alignment_lock
);
2614 p
= resource_alignment_param
;
2617 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2623 if (sscanf(p
, "%x:%x:%x.%x%n",
2624 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2626 if (sscanf(p
, "%x:%x.%x%n",
2627 &bus
, &slot
, &func
, &count
) != 3) {
2628 /* Invalid format */
2629 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2635 if (seg
== pci_domain_nr(dev
->bus
) &&
2636 bus
== dev
->bus
->number
&&
2637 slot
== PCI_SLOT(dev
->devfn
) &&
2638 func
== PCI_FUNC(dev
->devfn
)) {
2639 if (align_order
== -1) {
2642 align
= 1 << align_order
;
2647 if (*p
!= ';' && *p
!= ',') {
2648 /* End of param or invalid format */
2653 spin_unlock(&resource_alignment_lock
);
2658 * pci_is_reassigndev - check if specified PCI is target device to reassign
2659 * @dev: the PCI device to check
2661 * RETURNS: non-zero for PCI device is a target device to reassign,
2664 int pci_is_reassigndev(struct pci_dev
*dev
)
2666 return (pci_specified_resource_alignment(dev
) != 0);
2669 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2671 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2672 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2673 spin_lock(&resource_alignment_lock
);
2674 strncpy(resource_alignment_param
, buf
, count
);
2675 resource_alignment_param
[count
] = '\0';
2676 spin_unlock(&resource_alignment_lock
);
2680 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2683 spin_lock(&resource_alignment_lock
);
2684 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2685 spin_unlock(&resource_alignment_lock
);
2689 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2691 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2694 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2695 const char *buf
, size_t count
)
2697 return pci_set_resource_alignment_param(buf
, count
);
2700 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2701 pci_resource_alignment_store
);
2703 static int __init
pci_resource_alignment_sysfs_init(void)
2705 return bus_create_file(&pci_bus_type
,
2706 &bus_attr_resource_alignment
);
2709 late_initcall(pci_resource_alignment_sysfs_init
);
2711 static void __devinit
pci_no_domains(void)
2713 #ifdef CONFIG_PCI_DOMAINS
2714 pci_domains_supported
= 0;
2719 * pci_ext_cfg_enabled - can we access extended PCI config space?
2720 * @dev: The PCI device of the root bridge.
2722 * Returns 1 if we can access PCI extended config space (offsets
2723 * greater than 0xff). This is the default implementation. Architecture
2724 * implementations can override this.
2726 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2731 static int __init
pci_setup(char *str
)
2734 char *k
= strchr(str
, ',');
2737 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2738 if (!strcmp(str
, "nomsi")) {
2740 } else if (!strcmp(str
, "noaer")) {
2742 } else if (!strcmp(str
, "nodomains")) {
2744 } else if (!strncmp(str
, "cbiosize=", 9)) {
2745 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2746 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2747 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2748 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2749 pci_set_resource_alignment_param(str
+ 19,
2751 } else if (!strncmp(str
, "ecrc=", 5)) {
2752 pcie_ecrc_get_policy(str
+ 5);
2753 } else if (!strncmp(str
, "hpiosize=", 9)) {
2754 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
2755 } else if (!strncmp(str
, "hpmemsize=", 10)) {
2756 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
2758 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2766 early_param("pci", pci_setup
);
2768 EXPORT_SYMBOL(pci_reenable_device
);
2769 EXPORT_SYMBOL(pci_enable_device_io
);
2770 EXPORT_SYMBOL(pci_enable_device_mem
);
2771 EXPORT_SYMBOL(pci_enable_device
);
2772 EXPORT_SYMBOL(pcim_enable_device
);
2773 EXPORT_SYMBOL(pcim_pin_device
);
2774 EXPORT_SYMBOL(pci_disable_device
);
2775 EXPORT_SYMBOL(pci_find_capability
);
2776 EXPORT_SYMBOL(pci_bus_find_capability
);
2777 EXPORT_SYMBOL(pci_release_regions
);
2778 EXPORT_SYMBOL(pci_request_regions
);
2779 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2780 EXPORT_SYMBOL(pci_release_region
);
2781 EXPORT_SYMBOL(pci_request_region
);
2782 EXPORT_SYMBOL(pci_request_region_exclusive
);
2783 EXPORT_SYMBOL(pci_release_selected_regions
);
2784 EXPORT_SYMBOL(pci_request_selected_regions
);
2785 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2786 EXPORT_SYMBOL(pci_set_master
);
2787 EXPORT_SYMBOL(pci_clear_master
);
2788 EXPORT_SYMBOL(pci_set_mwi
);
2789 EXPORT_SYMBOL(pci_try_set_mwi
);
2790 EXPORT_SYMBOL(pci_clear_mwi
);
2791 EXPORT_SYMBOL_GPL(pci_intx
);
2792 EXPORT_SYMBOL(pci_set_dma_mask
);
2793 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2794 EXPORT_SYMBOL(pci_assign_resource
);
2795 EXPORT_SYMBOL(pci_find_parent_resource
);
2796 EXPORT_SYMBOL(pci_select_bars
);
2798 EXPORT_SYMBOL(pci_set_power_state
);
2799 EXPORT_SYMBOL(pci_save_state
);
2800 EXPORT_SYMBOL(pci_restore_state
);
2801 EXPORT_SYMBOL(pci_pme_capable
);
2802 EXPORT_SYMBOL(pci_pme_active
);
2803 EXPORT_SYMBOL(pci_enable_wake
);
2804 EXPORT_SYMBOL(pci_wake_from_d3
);
2805 EXPORT_SYMBOL(pci_target_state
);
2806 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2807 EXPORT_SYMBOL(pci_back_from_sleep
);
2808 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);