2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay
= 10;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported
= 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
35 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
46 struct list_head
*tmp
;
49 max
= bus
->subordinate
;
50 list_for_each(tmp
, &bus
->children
) {
51 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
59 #ifdef CONFIG_HAS_IOMEM
60 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
63 * Make sure the BAR is actually a memory resource, not an IO resource
65 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
69 return ioremap_nocache(pci_resource_start(pdev
, bar
),
70 pci_resource_len(pdev
, bar
));
72 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
77 * pci_max_busnr - returns maximum PCI bus number
79 * Returns the highest PCI bus number present in the system global list of
82 unsigned char __devinit
85 struct pci_bus
*bus
= NULL
;
89 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
90 n
= pci_bus_max_busnr(bus
);
99 #define PCI_FIND_CAP_TTL 48
101 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
102 u8 pos
, int cap
, int *ttl
)
107 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
111 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
117 pos
+= PCI_CAP_LIST_NEXT
;
122 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
125 int ttl
= PCI_FIND_CAP_TTL
;
127 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
130 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
132 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
133 pos
+ PCI_CAP_LIST_NEXT
, cap
);
135 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
137 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
138 unsigned int devfn
, u8 hdr_type
)
142 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
143 if (!(status
& PCI_STATUS_CAP_LIST
))
147 case PCI_HEADER_TYPE_NORMAL
:
148 case PCI_HEADER_TYPE_BRIDGE
:
149 return PCI_CAPABILITY_LIST
;
150 case PCI_HEADER_TYPE_CARDBUS
:
151 return PCI_CB_CAPABILITY_LIST
;
160 * pci_find_capability - query for devices' capabilities
161 * @dev: PCI device to query
162 * @cap: capability code
164 * Tell if a device supports a given PCI capability.
165 * Returns the address of the requested capability structure within the
166 * device's PCI configuration space or 0 in case the device does not
167 * support it. Possible values for @cap:
169 * %PCI_CAP_ID_PM Power Management
170 * %PCI_CAP_ID_AGP Accelerated Graphics Port
171 * %PCI_CAP_ID_VPD Vital Product Data
172 * %PCI_CAP_ID_SLOTID Slot Identification
173 * %PCI_CAP_ID_MSI Message Signalled Interrupts
174 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
175 * %PCI_CAP_ID_PCIX PCI-X
176 * %PCI_CAP_ID_EXP PCI Express
178 int pci_find_capability(struct pci_dev
*dev
, int cap
)
182 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
184 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
190 * pci_bus_find_capability - query for devices' capabilities
191 * @bus: the PCI bus to query
192 * @devfn: PCI device to query
193 * @cap: capability code
195 * Like pci_find_capability() but works for pci devices that do not have a
196 * pci_dev structure set up yet.
198 * Returns the address of the requested capability structure within the
199 * device's PCI configuration space or 0 in case the device does not
202 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
207 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
209 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
211 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
217 * pci_find_ext_capability - Find an extended capability
218 * @dev: PCI device to query
219 * @cap: capability code
221 * Returns the address of the requested extended capability structure
222 * within the device's PCI configuration space or 0 if the device does
223 * not support it. Possible values for @cap:
225 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
226 * %PCI_EXT_CAP_ID_VC Virtual Channel
227 * %PCI_EXT_CAP_ID_DSN Device Serial Number
228 * %PCI_EXT_CAP_ID_PWR Power Budgeting
230 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
234 int pos
= PCI_CFG_SPACE_SIZE
;
236 /* minimum 8 bytes per capability */
237 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
239 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
242 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
246 * If we have no capabilities, this is indicated by cap ID,
247 * cap version and next pointer all being 0.
253 if (PCI_EXT_CAP_ID(header
) == cap
)
256 pos
= PCI_EXT_CAP_NEXT(header
);
257 if (pos
< PCI_CFG_SPACE_SIZE
)
260 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
266 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
268 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
270 int rc
, ttl
= PCI_FIND_CAP_TTL
;
273 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
274 mask
= HT_3BIT_CAP_MASK
;
276 mask
= HT_5BIT_CAP_MASK
;
278 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
279 PCI_CAP_ID_HT
, &ttl
);
281 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
282 if (rc
!= PCIBIOS_SUCCESSFUL
)
285 if ((cap
& mask
) == ht_cap
)
288 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
289 pos
+ PCI_CAP_LIST_NEXT
,
290 PCI_CAP_ID_HT
, &ttl
);
296 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
297 * @dev: PCI device to query
298 * @pos: Position from which to continue searching
299 * @ht_cap: Hypertransport capability code
301 * To be used in conjunction with pci_find_ht_capability() to search for
302 * all capabilities matching @ht_cap. @pos should always be a value returned
303 * from pci_find_ht_capability().
305 * NB. To be 100% safe against broken PCI devices, the caller should take
306 * steps to avoid an infinite loop.
308 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
310 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
312 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
315 * pci_find_ht_capability - query a device's Hypertransport capabilities
316 * @dev: PCI device to query
317 * @ht_cap: Hypertransport capability code
319 * Tell if a device supports a given Hypertransport capability.
320 * Returns an address within the device's PCI configuration space
321 * or 0 in case the device does not support the request capability.
322 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
323 * which has a Hypertransport capability matching @ht_cap.
325 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
329 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
331 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
335 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
338 * pci_find_parent_resource - return resource region of parent bus of given region
339 * @dev: PCI device structure contains resources to be searched
340 * @res: child resource record for which parent is sought
342 * For given resource region of given device, return the resource
343 * region of parent bus the given region is contained in or where
344 * it should be allocated from.
347 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
349 const struct pci_bus
*bus
= dev
->bus
;
351 struct resource
*best
= NULL
;
353 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
354 struct resource
*r
= bus
->resource
[i
];
357 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
358 continue; /* Not contained */
359 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
360 continue; /* Wrong type */
361 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
362 return r
; /* Exact match */
363 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
364 best
= r
; /* Approximating prefetchable by non-prefetchable */
370 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
371 * @dev: PCI device to have its BARs restored
373 * Restore the BAR values for a given device, so as to make it
374 * accessible by its driver.
377 pci_restore_bars(struct pci_dev
*dev
)
381 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
382 pci_update_resource(dev
, i
);
385 static struct pci_platform_pm_ops
*pci_platform_pm
;
387 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
389 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
390 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
392 pci_platform_pm
= ops
;
396 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
398 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
401 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
404 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
407 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
409 return pci_platform_pm
?
410 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
413 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
415 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
418 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
420 return pci_platform_pm
?
421 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
425 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
427 * @dev: PCI device to handle.
428 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
431 * -EINVAL if the requested state is invalid.
432 * -EIO if device does not support PCI PM or its PM capabilities register has a
433 * wrong version, or device doesn't support the requested state.
434 * 0 if device already is in the requested state.
435 * 0 if device's power state has been successfully changed.
438 pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
441 bool need_restore
= false;
446 if (state
< PCI_D0
|| state
> PCI_D3hot
)
449 /* Validate current state:
450 * Can enter D0 from any state, but if we can only go deeper
451 * to sleep if we're already in a low power state
453 if (dev
->current_state
== state
) {
454 /* we're already there */
456 } else if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
457 && dev
->current_state
> state
) {
458 dev_err(&dev
->dev
, "invalid power transition "
459 "(from state %d to %d)\n", dev
->current_state
, state
);
463 /* check if this device supports the desired state */
464 if ((state
== PCI_D1
&& !dev
->d1_support
)
465 || (state
== PCI_D2
&& !dev
->d2_support
))
468 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
470 /* If we're (effectively) in D3, force entire word to 0.
471 * This doesn't affect PME_Status, disables PME_En, and
472 * sets PowerState to 0.
474 switch (dev
->current_state
) {
478 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
481 case PCI_UNKNOWN
: /* Boot-up */
482 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
483 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
485 /* Fall-through: force to D0 */
491 /* enter specified state */
492 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
494 /* Mandatory power management transition delays */
495 /* see PCI PM 1.1 5.6.1 table 18 */
496 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
497 msleep(pci_pm_d3_delay
);
498 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
501 dev
->current_state
= state
;
503 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
504 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
505 * from D3hot to D0 _may_ perform an internal reset, thereby
506 * going to "D0 Uninitialized" rather than "D0 Initialized".
507 * For example, at least some versions of the 3c905B and the
508 * 3c556B exhibit this behaviour.
510 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
511 * devices in a D3hot state at boot. Consequently, we need to
512 * restore at least the BARs so that the device will be
513 * accessible to its driver.
516 pci_restore_bars(dev
);
519 pcie_aspm_pm_state_change(dev
->bus
->self
);
525 * pci_update_current_state - Read PCI power state of given device from its
526 * PCI PM registers and cache it
527 * @dev: PCI device to handle.
529 static void pci_update_current_state(struct pci_dev
*dev
)
534 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
535 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
540 * pci_set_power_state - Set the power state of a PCI device
541 * @dev: PCI device to handle.
542 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
544 * Transition a device to a new power state, using the platform formware and/or
545 * the device's PCI PM registers.
548 * -EINVAL if the requested state is invalid.
549 * -EIO if device does not support PCI PM or its PM capabilities register has a
550 * wrong version, or device doesn't support the requested state.
551 * 0 if device already is in the requested state.
552 * 0 if device's power state has been successfully changed.
554 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
558 /* bound the state we're entering */
559 if (state
> PCI_D3hot
)
561 else if (state
< PCI_D0
)
563 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
565 * If the device or the parent bridge do not support PCI PM,
566 * ignore the request if we're doing anything other than putting
567 * it into D0 (which would only happen on boot).
571 if (state
== PCI_D0
&& platform_pci_power_manageable(dev
)) {
573 * Allow the platform to change the state, for example via ACPI
574 * _PR0, _PS0 and some such, but do not trust it.
576 int ret
= platform_pci_set_power_state(dev
, PCI_D0
);
578 pci_update_current_state(dev
);
580 /* This device is quirked not to be put into D3, so
581 don't put it in D3 */
582 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
585 error
= pci_raw_set_power_state(dev
, state
);
587 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
588 /* Allow the platform to finalize the transition */
589 int ret
= platform_pci_set_power_state(dev
, state
);
591 pci_update_current_state(dev
);
600 * pci_choose_state - Choose the power state of a PCI device
601 * @dev: PCI device to be suspended
602 * @state: target sleep state for the whole system. This is the value
603 * that is passed to suspend() function.
605 * Returns PCI power state suitable for given device and given system
609 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
613 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
616 ret
= platform_pci_choose_state(dev
);
617 if (ret
!= PCI_POWER_ERROR
)
620 switch (state
.event
) {
623 case PM_EVENT_FREEZE
:
624 case PM_EVENT_PRETHAW
:
625 /* REVISIT both freeze and pre-thaw "should" use D0 */
626 case PM_EVENT_SUSPEND
:
627 case PM_EVENT_HIBERNATE
:
630 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
637 EXPORT_SYMBOL(pci_choose_state
);
639 static int pci_save_pcie_state(struct pci_dev
*dev
)
642 struct pci_cap_saved_state
*save_state
;
645 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
649 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
651 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
654 cap
= (u16
*)&save_state
->data
[0];
656 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
657 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
658 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
659 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
664 static void pci_restore_pcie_state(struct pci_dev
*dev
)
667 struct pci_cap_saved_state
*save_state
;
670 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
671 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
672 if (!save_state
|| pos
<= 0)
674 cap
= (u16
*)&save_state
->data
[0];
676 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
677 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
678 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
679 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
683 static int pci_save_pcix_state(struct pci_dev
*dev
)
686 struct pci_cap_saved_state
*save_state
;
688 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
692 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
694 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
698 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
703 static void pci_restore_pcix_state(struct pci_dev
*dev
)
706 struct pci_cap_saved_state
*save_state
;
709 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
710 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
711 if (!save_state
|| pos
<= 0)
713 cap
= (u16
*)&save_state
->data
[0];
715 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
720 * pci_save_state - save the PCI configuration space of a device before suspending
721 * @dev: - PCI device that we're dealing with
724 pci_save_state(struct pci_dev
*dev
)
727 /* XXX: 100% dword access ok here? */
728 for (i
= 0; i
< 16; i
++)
729 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
730 if ((i
= pci_save_pcie_state(dev
)) != 0)
732 if ((i
= pci_save_pcix_state(dev
)) != 0)
738 * pci_restore_state - Restore the saved state of a PCI device
739 * @dev: - PCI device that we're dealing with
742 pci_restore_state(struct pci_dev
*dev
)
747 /* PCI Express register must be restored first */
748 pci_restore_pcie_state(dev
);
751 * The Base Address register should be programmed before the command
754 for (i
= 15; i
>= 0; i
--) {
755 pci_read_config_dword(dev
, i
* 4, &val
);
756 if (val
!= dev
->saved_config_space
[i
]) {
757 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
758 "space at offset %#x (was %#x, writing %#x)\n",
759 i
, val
, (int)dev
->saved_config_space
[i
]);
760 pci_write_config_dword(dev
,i
* 4,
761 dev
->saved_config_space
[i
]);
764 pci_restore_pcix_state(dev
);
765 pci_restore_msi_state(dev
);
770 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
774 err
= pci_set_power_state(dev
, PCI_D0
);
775 if (err
< 0 && err
!= -EIO
)
777 err
= pcibios_enable_device(dev
, bars
);
780 pci_fixup_device(pci_fixup_enable
, dev
);
786 * pci_reenable_device - Resume abandoned device
787 * @dev: PCI device to be resumed
789 * Note this function is a backend of pci_default_resume and is not supposed
790 * to be called by normal code, write proper resume handler and use it instead.
792 int pci_reenable_device(struct pci_dev
*dev
)
794 if (atomic_read(&dev
->enable_cnt
))
795 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
799 static int __pci_enable_device_flags(struct pci_dev
*dev
,
800 resource_size_t flags
)
805 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
806 return 0; /* already enabled */
808 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
809 if (dev
->resource
[i
].flags
& flags
)
812 err
= do_pci_enable_device(dev
, bars
);
814 atomic_dec(&dev
->enable_cnt
);
819 * pci_enable_device_io - Initialize a device for use with IO space
820 * @dev: PCI device to be initialized
822 * Initialize device before it's used by a driver. Ask low-level code
823 * to enable I/O resources. Wake up the device if it was suspended.
824 * Beware, this function can fail.
826 int pci_enable_device_io(struct pci_dev
*dev
)
828 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
832 * pci_enable_device_mem - Initialize a device for use with Memory space
833 * @dev: PCI device to be initialized
835 * Initialize device before it's used by a driver. Ask low-level code
836 * to enable Memory resources. Wake up the device if it was suspended.
837 * Beware, this function can fail.
839 int pci_enable_device_mem(struct pci_dev
*dev
)
841 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
845 * pci_enable_device - Initialize device before it's used by a driver.
846 * @dev: PCI device to be initialized
848 * Initialize device before it's used by a driver. Ask low-level code
849 * to enable I/O and memory. Wake up the device if it was suspended.
850 * Beware, this function can fail.
852 * Note we don't actually enable the device many times if we call
853 * this function repeatedly (we just increment the count).
855 int pci_enable_device(struct pci_dev
*dev
)
857 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
861 * Managed PCI resources. This manages device on/off, intx/msi/msix
862 * on/off and BAR regions. pci_dev itself records msi/msix status, so
863 * there's no need to track it separately. pci_devres is initialized
864 * when a device is enabled using managed PCI device enable interface.
867 unsigned int enabled
:1;
868 unsigned int pinned
:1;
869 unsigned int orig_intx
:1;
870 unsigned int restore_intx
:1;
874 static void pcim_release(struct device
*gendev
, void *res
)
876 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
877 struct pci_devres
*this = res
;
880 if (dev
->msi_enabled
)
881 pci_disable_msi(dev
);
882 if (dev
->msix_enabled
)
883 pci_disable_msix(dev
);
885 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
886 if (this->region_mask
& (1 << i
))
887 pci_release_region(dev
, i
);
889 if (this->restore_intx
)
890 pci_intx(dev
, this->orig_intx
);
892 if (this->enabled
&& !this->pinned
)
893 pci_disable_device(dev
);
896 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
898 struct pci_devres
*dr
, *new_dr
;
900 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
904 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
907 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
910 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
912 if (pci_is_managed(pdev
))
913 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
918 * pcim_enable_device - Managed pci_enable_device()
919 * @pdev: PCI device to be initialized
921 * Managed pci_enable_device().
923 int pcim_enable_device(struct pci_dev
*pdev
)
925 struct pci_devres
*dr
;
928 dr
= get_pci_dr(pdev
);
934 rc
= pci_enable_device(pdev
);
936 pdev
->is_managed
= 1;
943 * pcim_pin_device - Pin managed PCI device
944 * @pdev: PCI device to pin
946 * Pin managed PCI device @pdev. Pinned device won't be disabled on
947 * driver detach. @pdev must have been enabled with
948 * pcim_enable_device().
950 void pcim_pin_device(struct pci_dev
*pdev
)
952 struct pci_devres
*dr
;
954 dr
= find_pci_dr(pdev
);
955 WARN_ON(!dr
|| !dr
->enabled
);
961 * pcibios_disable_device - disable arch specific PCI resources for device dev
962 * @dev: the PCI device to disable
964 * Disables architecture specific PCI resources for the device. This
965 * is the default implementation. Architecture implementations can
968 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
971 * pci_disable_device - Disable PCI device after use
972 * @dev: PCI device to be disabled
974 * Signal to the system that the PCI device is not in use by the system
975 * anymore. This only involves disabling PCI bus-mastering, if active.
977 * Note we don't actually disable the device until all callers of
978 * pci_device_enable() have called pci_device_disable().
981 pci_disable_device(struct pci_dev
*dev
)
983 struct pci_devres
*dr
;
986 dr
= find_pci_dr(dev
);
990 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
993 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
994 if (pci_command
& PCI_COMMAND_MASTER
) {
995 pci_command
&= ~PCI_COMMAND_MASTER
;
996 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
998 dev
->is_busmaster
= 0;
1000 pcibios_disable_device(dev
);
1004 * pcibios_set_pcie_reset_state - set reset state for device dev
1005 * @dev: the PCI-E device reset
1006 * @state: Reset state to enter into
1009 * Sets the PCI-E reset state for the device. This is the default
1010 * implementation. Architecture implementations can override this.
1012 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1013 enum pcie_reset_state state
)
1019 * pci_set_pcie_reset_state - set reset state for device dev
1020 * @dev: the PCI-E device reset
1021 * @state: Reset state to enter into
1024 * Sets the PCI reset state for the device.
1026 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1028 return pcibios_set_pcie_reset_state(dev
, state
);
1032 * pci_pme_capable - check the capability of PCI device to generate PME#
1033 * @dev: PCI device to handle.
1034 * @state: PCI state from which device will issue PME#.
1036 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1041 return !!(dev
->pme_support
& (1 << state
));
1045 * pci_pme_active - enable or disable PCI device's PME# function
1046 * @dev: PCI device to handle.
1047 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1049 * The caller must verify that the device is capable of generating PME# before
1050 * calling this function with @enable equal to 'true'.
1052 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1059 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1060 /* Clear PME_Status by writing 1 to it and enable PME# */
1061 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1063 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1065 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1067 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1068 enable
? "enabled" : "disabled");
1072 * pci_enable_wake - enable PCI device as wakeup event source
1073 * @dev: PCI device affected
1074 * @state: PCI state from which device will issue wakeup events
1075 * @enable: True to enable event generation; false to disable
1077 * This enables the device as a wakeup event source, or disables it.
1078 * When such events involves platform-specific hooks, those hooks are
1079 * called automatically by this routine.
1081 * Devices with legacy power management (no standard PCI PM capabilities)
1082 * always require such platform hooks.
1085 * 0 is returned on success
1086 * -EINVAL is returned if device is not supposed to wake up the system
1087 * Error code depending on the platform is returned if both the platform and
1088 * the native mechanism fail to enable the generation of wake-up events
1090 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1093 bool pme_done
= false;
1095 if (enable
&& !device_may_wakeup(&dev
->dev
))
1099 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1100 * Anderson we should be doing PME# wake enable followed by ACPI wake
1101 * enable. To disable wake-up we call the platform first, for symmetry.
1104 if (!enable
&& platform_pci_can_wakeup(dev
))
1105 error
= platform_pci_sleep_wake(dev
, false);
1107 if (!enable
|| pci_pme_capable(dev
, state
)) {
1108 pci_pme_active(dev
, enable
);
1112 if (enable
&& platform_pci_can_wakeup(dev
))
1113 error
= platform_pci_sleep_wake(dev
, true);
1115 return pme_done
? 0 : error
;
1119 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1120 * @dev: PCI device to prepare
1121 * @enable: True to enable wake-up event generation; false to disable
1123 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1124 * and this function allows them to set that up cleanly - pci_enable_wake()
1125 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1126 * ordering constraints.
1128 * This function only returns error code if the device is not capable of
1129 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1130 * enable wake-up power for it.
1132 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1134 return pci_pme_capable(dev
, PCI_D3cold
) ?
1135 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1136 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1140 * pci_target_state - find an appropriate low power state for a given PCI dev
1143 * Use underlying platform code to find a supported low power state for @dev.
1144 * If the platform can't manage @dev, return the deepest state from which it
1145 * can generate wake events, based on any available PME info.
1147 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1149 pci_power_t target_state
= PCI_D3hot
;
1151 if (platform_pci_power_manageable(dev
)) {
1153 * Call the platform to choose the target state of the device
1154 * and enable wake-up from this state if supported.
1156 pci_power_t state
= platform_pci_choose_state(dev
);
1159 case PCI_POWER_ERROR
:
1164 if (pci_no_d1d2(dev
))
1167 target_state
= state
;
1169 } else if (device_may_wakeup(&dev
->dev
)) {
1171 * Find the deepest state from which the device can generate
1172 * wake-up events, make it the target state and enable device
1176 return PCI_POWER_ERROR
;
1178 if (dev
->pme_support
) {
1180 && !(dev
->pme_support
& (1 << target_state
)))
1185 return target_state
;
1189 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1190 * @dev: Device to handle.
1192 * Choose the power state appropriate for the device depending on whether
1193 * it can wake up the system and/or is power manageable by the platform
1194 * (PCI_D3hot is the default) and put the device into that state.
1196 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1198 pci_power_t target_state
= pci_target_state(dev
);
1201 if (target_state
== PCI_POWER_ERROR
)
1204 pci_enable_wake(dev
, target_state
, true);
1206 error
= pci_set_power_state(dev
, target_state
);
1209 pci_enable_wake(dev
, target_state
, false);
1215 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1216 * @dev: Device to handle.
1218 * Disable device's sytem wake-up capability and put it into D0.
1220 int pci_back_from_sleep(struct pci_dev
*dev
)
1222 pci_enable_wake(dev
, PCI_D0
, false);
1223 return pci_set_power_state(dev
, PCI_D0
);
1227 * pci_pm_init - Initialize PM functions of given PCI device
1228 * @dev: PCI device to handle.
1230 void pci_pm_init(struct pci_dev
*dev
)
1237 /* find PCI PM capability in list */
1238 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1241 /* Check device's ability to generate PME# */
1242 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1244 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1245 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1246 pmc
& PCI_PM_CAP_VER_MASK
);
1252 dev
->d1_support
= false;
1253 dev
->d2_support
= false;
1254 if (!pci_no_d1d2(dev
)) {
1255 if (pmc
& PCI_PM_CAP_D1
)
1256 dev
->d1_support
= true;
1257 if (pmc
& PCI_PM_CAP_D2
)
1258 dev
->d2_support
= true;
1260 if (dev
->d1_support
|| dev
->d2_support
)
1261 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1262 dev
->d1_support
? " D1" : "",
1263 dev
->d2_support
? " D2" : "");
1266 pmc
&= PCI_PM_CAP_PME_MASK
;
1268 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1269 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1270 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1271 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1272 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1273 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1274 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1276 * Make device's PM flags reflect the wake-up capability, but
1277 * let the user space enable it to wake up the system as needed.
1279 device_set_wakeup_capable(&dev
->dev
, true);
1280 device_set_wakeup_enable(&dev
->dev
, false);
1281 /* Disable the PME# generation functionality */
1282 pci_pme_active(dev
, false);
1284 dev
->pme_support
= 0;
1289 * pci_add_save_buffer - allocate buffer for saving given capability registers
1290 * @dev: the PCI device
1291 * @cap: the capability to allocate the buffer for
1292 * @size: requested size of the buffer
1294 static int pci_add_cap_save_buffer(
1295 struct pci_dev
*dev
, char cap
, unsigned int size
)
1298 struct pci_cap_saved_state
*save_state
;
1300 pos
= pci_find_capability(dev
, cap
);
1304 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1308 save_state
->cap_nr
= cap
;
1309 pci_add_saved_cap(dev
, save_state
);
1315 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1316 * @dev: the PCI device
1318 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1322 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
, 4 * sizeof(u16
));
1325 "unable to preallocate PCI Express save buffer\n");
1327 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1330 "unable to preallocate PCI-X save buffer\n");
1334 * pci_enable_ari - enable ARI forwarding if hardware support it
1335 * @dev: the PCI device
1337 void pci_enable_ari(struct pci_dev
*dev
)
1342 struct pci_dev
*bridge
;
1344 if (!dev
->is_pcie
|| dev
->devfn
)
1347 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1351 bridge
= dev
->bus
->self
;
1352 if (!bridge
|| !bridge
->is_pcie
)
1355 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1359 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1360 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1363 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1364 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1365 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1367 bridge
->ari_enabled
= 1;
1371 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1372 * @dev: the PCI device
1373 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1375 * Perform INTx swizzling for a device behind one level of bridge. This is
1376 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1377 * behind bridges on add-in cards.
1379 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1381 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1385 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1393 while (dev
->bus
->self
) {
1394 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1395 dev
= dev
->bus
->self
;
1402 * pci_release_region - Release a PCI bar
1403 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1404 * @bar: BAR to release
1406 * Releases the PCI I/O and memory resources previously reserved by a
1407 * successful call to pci_request_region. Call this function only
1408 * after all use of the PCI regions has ceased.
1410 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1412 struct pci_devres
*dr
;
1414 if (pci_resource_len(pdev
, bar
) == 0)
1416 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1417 release_region(pci_resource_start(pdev
, bar
),
1418 pci_resource_len(pdev
, bar
));
1419 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1420 release_mem_region(pci_resource_start(pdev
, bar
),
1421 pci_resource_len(pdev
, bar
));
1423 dr
= find_pci_dr(pdev
);
1425 dr
->region_mask
&= ~(1 << bar
);
1429 * pci_request_region - Reserved PCI I/O and memory resource
1430 * @pdev: PCI device whose resources are to be reserved
1431 * @bar: BAR to be reserved
1432 * @res_name: Name to be associated with resource.
1434 * Mark the PCI region associated with PCI device @pdev BR @bar as
1435 * being reserved by owner @res_name. Do not access any
1436 * address inside the PCI regions unless this call returns
1439 * Returns 0 on success, or %EBUSY on error. A warning
1440 * message is also printed on failure.
1442 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1445 struct pci_devres
*dr
;
1447 if (pci_resource_len(pdev
, bar
) == 0)
1450 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1451 if (!request_region(pci_resource_start(pdev
, bar
),
1452 pci_resource_len(pdev
, bar
), res_name
))
1455 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1456 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1457 pci_resource_len(pdev
, bar
), res_name
,
1462 dr
= find_pci_dr(pdev
);
1464 dr
->region_mask
|= 1 << bar
;
1469 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1471 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1472 &pdev
->resource
[bar
]);
1477 * pci_request_region - Reserved PCI I/O and memory resource
1478 * @pdev: PCI device whose resources are to be reserved
1479 * @bar: BAR to be reserved
1480 * @res_name: Name to be associated with resource.
1482 * Mark the PCI region associated with PCI device @pdev BR @bar as
1483 * being reserved by owner @res_name. Do not access any
1484 * address inside the PCI regions unless this call returns
1487 * Returns 0 on success, or %EBUSY on error. A warning
1488 * message is also printed on failure.
1490 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1492 return __pci_request_region(pdev
, bar
, res_name
, 0);
1496 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1497 * @pdev: PCI device whose resources are to be reserved
1498 * @bar: BAR to be reserved
1499 * @res_name: Name to be associated with resource.
1501 * Mark the PCI region associated with PCI device @pdev BR @bar as
1502 * being reserved by owner @res_name. Do not access any
1503 * address inside the PCI regions unless this call returns
1506 * Returns 0 on success, or %EBUSY on error. A warning
1507 * message is also printed on failure.
1509 * The key difference that _exclusive makes it that userspace is
1510 * explicitly not allowed to map the resource via /dev/mem or
1513 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1515 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1518 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1519 * @pdev: PCI device whose resources were previously reserved
1520 * @bars: Bitmask of BARs to be released
1522 * Release selected PCI I/O and memory resources previously reserved.
1523 * Call this function only after all use of the PCI regions has ceased.
1525 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1529 for (i
= 0; i
< 6; i
++)
1530 if (bars
& (1 << i
))
1531 pci_release_region(pdev
, i
);
1534 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1535 const char *res_name
, int excl
)
1539 for (i
= 0; i
< 6; i
++)
1540 if (bars
& (1 << i
))
1541 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1547 if (bars
& (1 << i
))
1548 pci_release_region(pdev
, i
);
1555 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1556 * @pdev: PCI device whose resources are to be reserved
1557 * @bars: Bitmask of BARs to be requested
1558 * @res_name: Name to be associated with resource
1560 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1561 const char *res_name
)
1563 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1566 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1567 int bars
, const char *res_name
)
1569 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1570 IORESOURCE_EXCLUSIVE
);
1574 * pci_release_regions - Release reserved PCI I/O and memory resources
1575 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1577 * Releases all PCI I/O and memory resources previously reserved by a
1578 * successful call to pci_request_regions. Call this function only
1579 * after all use of the PCI regions has ceased.
1582 void pci_release_regions(struct pci_dev
*pdev
)
1584 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1588 * pci_request_regions - Reserved PCI I/O and memory resources
1589 * @pdev: PCI device whose resources are to be reserved
1590 * @res_name: Name to be associated with resource.
1592 * Mark all PCI regions associated with PCI device @pdev as
1593 * being reserved by owner @res_name. Do not access any
1594 * address inside the PCI regions unless this call returns
1597 * Returns 0 on success, or %EBUSY on error. A warning
1598 * message is also printed on failure.
1600 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1602 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1606 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1607 * @pdev: PCI device whose resources are to be reserved
1608 * @res_name: Name to be associated with resource.
1610 * Mark all PCI regions associated with PCI device @pdev as
1611 * being reserved by owner @res_name. Do not access any
1612 * address inside the PCI regions unless this call returns
1615 * pci_request_regions_exclusive() will mark the region so that
1616 * /dev/mem and the sysfs MMIO access will not be allowed.
1618 * Returns 0 on success, or %EBUSY on error. A warning
1619 * message is also printed on failure.
1621 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1623 return pci_request_selected_regions_exclusive(pdev
,
1624 ((1 << 6) - 1), res_name
);
1629 * pci_set_master - enables bus-mastering for device dev
1630 * @dev: the PCI device to enable
1632 * Enables bus-mastering on the device and calls pcibios_set_master()
1633 * to do the needed arch specific settings.
1636 pci_set_master(struct pci_dev
*dev
)
1640 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1641 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1642 dev_dbg(&dev
->dev
, "enabling bus mastering\n");
1643 cmd
|= PCI_COMMAND_MASTER
;
1644 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1646 dev
->is_busmaster
= 1;
1647 pcibios_set_master(dev
);
1650 #ifdef PCI_DISABLE_MWI
1651 int pci_set_mwi(struct pci_dev
*dev
)
1656 int pci_try_set_mwi(struct pci_dev
*dev
)
1661 void pci_clear_mwi(struct pci_dev
*dev
)
1667 #ifndef PCI_CACHE_LINE_BYTES
1668 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1671 /* This can be overridden by arch code. */
1672 /* Don't forget this is measured in 32-bit words, not bytes */
1673 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1676 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1677 * @dev: the PCI device for which MWI is to be enabled
1679 * Helper function for pci_set_mwi.
1680 * Originally copied from drivers/net/acenic.c.
1681 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1683 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1686 pci_set_cacheline_size(struct pci_dev
*dev
)
1690 if (!pci_cache_line_size
)
1691 return -EINVAL
; /* The system doesn't support MWI. */
1693 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1694 equal to or multiple of the right value. */
1695 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1696 if (cacheline_size
>= pci_cache_line_size
&&
1697 (cacheline_size
% pci_cache_line_size
) == 0)
1700 /* Write the correct value. */
1701 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1703 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1704 if (cacheline_size
== pci_cache_line_size
)
1707 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1708 "supported\n", pci_cache_line_size
<< 2);
1714 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1715 * @dev: the PCI device for which MWI is enabled
1717 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1719 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1722 pci_set_mwi(struct pci_dev
*dev
)
1727 rc
= pci_set_cacheline_size(dev
);
1731 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1732 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1733 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1734 cmd
|= PCI_COMMAND_INVALIDATE
;
1735 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1742 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1743 * @dev: the PCI device for which MWI is enabled
1745 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1746 * Callers are not required to check the return value.
1748 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1750 int pci_try_set_mwi(struct pci_dev
*dev
)
1752 int rc
= pci_set_mwi(dev
);
1757 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1758 * @dev: the PCI device to disable
1760 * Disables PCI Memory-Write-Invalidate transaction on the device
1763 pci_clear_mwi(struct pci_dev
*dev
)
1767 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1768 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1769 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1770 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1773 #endif /* ! PCI_DISABLE_MWI */
1776 * pci_intx - enables/disables PCI INTx for device dev
1777 * @pdev: the PCI device to operate on
1778 * @enable: boolean: whether to enable or disable PCI INTx
1780 * Enables/disables PCI INTx for device dev
1783 pci_intx(struct pci_dev
*pdev
, int enable
)
1785 u16 pci_command
, new;
1787 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1790 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1792 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1795 if (new != pci_command
) {
1796 struct pci_devres
*dr
;
1798 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1800 dr
= find_pci_dr(pdev
);
1801 if (dr
&& !dr
->restore_intx
) {
1802 dr
->restore_intx
= 1;
1803 dr
->orig_intx
= !enable
;
1809 * pci_msi_off - disables any msi or msix capabilities
1810 * @dev: the PCI device to operate on
1812 * If you want to use msi see pci_enable_msi and friends.
1813 * This is a lower level primitive that allows us to disable
1814 * msi operation at the device level.
1816 void pci_msi_off(struct pci_dev
*dev
)
1821 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1823 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1824 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1825 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1827 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1829 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1830 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1831 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1835 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1837 * These can be overridden by arch-specific implementations
1840 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1842 if (!pci_dma_supported(dev
, mask
))
1845 dev
->dma_mask
= mask
;
1851 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1853 if (!pci_dma_supported(dev
, mask
))
1856 dev
->dev
.coherent_dma_mask
= mask
;
1862 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1863 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1865 return dma_set_max_seg_size(&dev
->dev
, size
);
1867 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1870 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1871 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1873 return dma_set_seg_boundary(&dev
->dev
, mask
);
1875 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1878 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
1882 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1886 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
1887 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
1893 pci_block_user_cfg_access(dev
);
1895 /* Wait for Transaction Pending bit clean */
1897 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1898 if (status
& PCI_EXP_DEVSTA_TRPND
) {
1899 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
1900 "sleeping for 1 second\n");
1902 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1903 if (status
& PCI_EXP_DEVSTA_TRPND
)
1904 dev_info(&dev
->dev
, "Still busy after 1s; "
1905 "proceeding with reset anyway\n");
1908 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
1909 PCI_EXP_DEVCTL_BCR_FLR
);
1912 pci_unblock_user_cfg_access(dev
);
1916 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
1918 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
1924 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
1925 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
1931 pci_block_user_cfg_access(dev
);
1933 /* Wait for Transaction Pending bit clean */
1935 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
1936 if (status
& PCI_AF_STATUS_TP
) {
1937 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
1938 " reset; sleeping for 1 second\n");
1940 pci_read_config_byte(dev
,
1941 cappos
+ PCI_AF_STATUS
, &status
);
1942 if (status
& PCI_AF_STATUS_TP
)
1943 dev_info(&dev
->dev
, "Still busy after 1s; "
1944 "proceeding with reset anyway\n");
1946 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
1949 pci_unblock_user_cfg_access(dev
);
1953 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
1957 res
= __pcie_flr(pdev
, probe
);
1961 res
= __pci_af_flr(pdev
, probe
);
1969 * pci_execute_reset_function() - Reset a PCI device function
1970 * @dev: Device function to reset
1972 * Some devices allow an individual function to be reset without affecting
1973 * other functions in the same device. The PCI device must be responsive
1974 * to PCI config space in order to use this function.
1976 * The device function is presumed to be unused when this function is called.
1977 * Resetting the device will make the contents of PCI configuration space
1978 * random, so any caller of this must be prepared to reinitialise the
1979 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
1982 * Returns 0 if the device function was successfully reset or -ENOTTY if the
1983 * device doesn't support resetting a single function.
1985 int pci_execute_reset_function(struct pci_dev
*dev
)
1987 return __pci_reset_function(dev
, 0);
1989 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
1992 * pci_reset_function() - quiesce and reset a PCI device function
1993 * @dev: Device function to reset
1995 * Some devices allow an individual function to be reset without affecting
1996 * other functions in the same device. The PCI device must be responsive
1997 * to PCI config space in order to use this function.
1999 * This function does not just reset the PCI portion of a device, but
2000 * clears all the state associated with the device. This function differs
2001 * from pci_execute_reset_function in that it saves and restores device state
2004 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2005 * device doesn't support resetting a single function.
2007 int pci_reset_function(struct pci_dev
*dev
)
2009 int r
= __pci_reset_function(dev
, 1);
2014 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2015 disable_irq(dev
->irq
);
2016 pci_save_state(dev
);
2018 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2020 r
= pci_execute_reset_function(dev
);
2022 pci_restore_state(dev
);
2023 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2024 enable_irq(dev
->irq
);
2028 EXPORT_SYMBOL_GPL(pci_reset_function
);
2031 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2032 * @dev: PCI device to query
2034 * Returns mmrbc: maximum designed memory read count in bytes
2035 * or appropriate error value.
2037 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2042 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2046 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2050 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2052 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2055 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2056 * @dev: PCI device to query
2058 * Returns mmrbc: maximum memory read count in bytes
2059 * or appropriate error value.
2061 int pcix_get_mmrbc(struct pci_dev
*dev
)
2066 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2070 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2072 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2076 EXPORT_SYMBOL(pcix_get_mmrbc
);
2079 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2080 * @dev: PCI device to query
2081 * @mmrbc: maximum memory read count in bytes
2082 * valid values are 512, 1024, 2048, 4096
2084 * If possible sets maximum memory read byte count, some bridges have erratas
2085 * that prevent this.
2087 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2089 int cap
, err
= -EINVAL
;
2090 u32 stat
, cmd
, v
, o
;
2092 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2095 v
= ffs(mmrbc
) - 10;
2097 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2101 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2105 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2108 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2112 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2114 if (v
> o
&& dev
->bus
&&
2115 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2118 cmd
&= ~PCI_X_CMD_MAX_READ
;
2120 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2125 EXPORT_SYMBOL(pcix_set_mmrbc
);
2128 * pcie_get_readrq - get PCI Express read request size
2129 * @dev: PCI device to query
2131 * Returns maximum memory read request in bytes
2132 * or appropriate error value.
2134 int pcie_get_readrq(struct pci_dev
*dev
)
2139 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2143 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2145 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2149 EXPORT_SYMBOL(pcie_get_readrq
);
2152 * pcie_set_readrq - set PCI Express maximum memory read request
2153 * @dev: PCI device to query
2154 * @rq: maximum memory read count in bytes
2155 * valid values are 128, 256, 512, 1024, 2048, 4096
2157 * If possible sets maximum read byte count
2159 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2161 int cap
, err
= -EINVAL
;
2164 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2167 v
= (ffs(rq
) - 8) << 12;
2169 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2173 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2177 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2178 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2180 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2186 EXPORT_SYMBOL(pcie_set_readrq
);
2189 * pci_select_bars - Make BAR mask from the type of resource
2190 * @dev: the PCI device for which BAR mask is made
2191 * @flags: resource type mask to be selected
2193 * This helper routine makes bar mask from the type of resource.
2195 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2198 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2199 if (pci_resource_flags(dev
, i
) & flags
)
2205 * pci_resource_bar - get position of the BAR associated with a resource
2206 * @dev: the PCI device
2207 * @resno: the resource number
2208 * @type: the BAR type to be filled in
2210 * Returns BAR position in config space, or 0 if the BAR is invalid.
2212 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2214 if (resno
< PCI_ROM_RESOURCE
) {
2215 *type
= pci_bar_unknown
;
2216 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2217 } else if (resno
== PCI_ROM_RESOURCE
) {
2218 *type
= pci_bar_mem32
;
2219 return dev
->rom_base_reg
;
2222 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2226 static void __devinit
pci_no_domains(void)
2228 #ifdef CONFIG_PCI_DOMAINS
2229 pci_domains_supported
= 0;
2234 * pci_ext_cfg_enabled - can we access extended PCI config space?
2235 * @dev: The PCI device of the root bridge.
2237 * Returns 1 if we can access PCI extended config space (offsets
2238 * greater than 0xff). This is the default implementation. Architecture
2239 * implementations can override this.
2241 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2246 static int __devinit
pci_init(void)
2248 struct pci_dev
*dev
= NULL
;
2250 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2251 pci_fixup_device(pci_fixup_final
, dev
);
2257 static int __init
pci_setup(char *str
)
2260 char *k
= strchr(str
, ',');
2263 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2264 if (!strcmp(str
, "nomsi")) {
2266 } else if (!strcmp(str
, "noaer")) {
2268 } else if (!strcmp(str
, "nodomains")) {
2270 } else if (!strncmp(str
, "cbiosize=", 9)) {
2271 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2272 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2273 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2275 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2283 early_param("pci", pci_setup
);
2285 device_initcall(pci_init
);
2287 EXPORT_SYMBOL(pci_reenable_device
);
2288 EXPORT_SYMBOL(pci_enable_device_io
);
2289 EXPORT_SYMBOL(pci_enable_device_mem
);
2290 EXPORT_SYMBOL(pci_enable_device
);
2291 EXPORT_SYMBOL(pcim_enable_device
);
2292 EXPORT_SYMBOL(pcim_pin_device
);
2293 EXPORT_SYMBOL(pci_disable_device
);
2294 EXPORT_SYMBOL(pci_find_capability
);
2295 EXPORT_SYMBOL(pci_bus_find_capability
);
2296 EXPORT_SYMBOL(pci_release_regions
);
2297 EXPORT_SYMBOL(pci_request_regions
);
2298 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2299 EXPORT_SYMBOL(pci_release_region
);
2300 EXPORT_SYMBOL(pci_request_region
);
2301 EXPORT_SYMBOL(pci_request_region_exclusive
);
2302 EXPORT_SYMBOL(pci_release_selected_regions
);
2303 EXPORT_SYMBOL(pci_request_selected_regions
);
2304 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2305 EXPORT_SYMBOL(pci_set_master
);
2306 EXPORT_SYMBOL(pci_set_mwi
);
2307 EXPORT_SYMBOL(pci_try_set_mwi
);
2308 EXPORT_SYMBOL(pci_clear_mwi
);
2309 EXPORT_SYMBOL_GPL(pci_intx
);
2310 EXPORT_SYMBOL(pci_set_dma_mask
);
2311 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2312 EXPORT_SYMBOL(pci_assign_resource
);
2313 EXPORT_SYMBOL(pci_find_parent_resource
);
2314 EXPORT_SYMBOL(pci_select_bars
);
2316 EXPORT_SYMBOL(pci_set_power_state
);
2317 EXPORT_SYMBOL(pci_save_state
);
2318 EXPORT_SYMBOL(pci_restore_state
);
2319 EXPORT_SYMBOL(pci_pme_capable
);
2320 EXPORT_SYMBOL(pci_pme_active
);
2321 EXPORT_SYMBOL(pci_enable_wake
);
2322 EXPORT_SYMBOL(pci_wake_from_d3
);
2323 EXPORT_SYMBOL(pci_target_state
);
2324 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2325 EXPORT_SYMBOL(pci_back_from_sleep
);
2326 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);