2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 unsigned int pci_pm_d3_delay
= 10;
25 #ifdef CONFIG_PCI_DOMAINS
26 int pci_domains_supported
= 1;
29 #define DEFAULT_CARDBUS_IO_SIZE (256)
30 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
31 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
32 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
33 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
36 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
37 * @bus: pointer to PCI bus structure to search
39 * Given a PCI bus, returns the highest PCI bus number present in the set
40 * including the given PCI bus and its list of child PCI buses.
42 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
44 struct list_head
*tmp
;
47 max
= bus
->subordinate
;
48 list_for_each(tmp
, &bus
->children
) {
49 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
55 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
59 * pci_max_busnr - returns maximum PCI bus number
61 * Returns the highest PCI bus number present in the system global list of
64 unsigned char __devinit
67 struct pci_bus
*bus
= NULL
;
71 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
72 n
= pci_bus_max_busnr(bus
);
81 #define PCI_FIND_CAP_TTL 48
83 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
84 u8 pos
, int cap
, int *ttl
)
89 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
93 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
99 pos
+= PCI_CAP_LIST_NEXT
;
104 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
107 int ttl
= PCI_FIND_CAP_TTL
;
109 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
112 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
114 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
115 pos
+ PCI_CAP_LIST_NEXT
, cap
);
117 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
119 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
120 unsigned int devfn
, u8 hdr_type
)
124 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
125 if (!(status
& PCI_STATUS_CAP_LIST
))
129 case PCI_HEADER_TYPE_NORMAL
:
130 case PCI_HEADER_TYPE_BRIDGE
:
131 return PCI_CAPABILITY_LIST
;
132 case PCI_HEADER_TYPE_CARDBUS
:
133 return PCI_CB_CAPABILITY_LIST
;
142 * pci_find_capability - query for devices' capabilities
143 * @dev: PCI device to query
144 * @cap: capability code
146 * Tell if a device supports a given PCI capability.
147 * Returns the address of the requested capability structure within the
148 * device's PCI configuration space or 0 in case the device does not
149 * support it. Possible values for @cap:
151 * %PCI_CAP_ID_PM Power Management
152 * %PCI_CAP_ID_AGP Accelerated Graphics Port
153 * %PCI_CAP_ID_VPD Vital Product Data
154 * %PCI_CAP_ID_SLOTID Slot Identification
155 * %PCI_CAP_ID_MSI Message Signalled Interrupts
156 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
157 * %PCI_CAP_ID_PCIX PCI-X
158 * %PCI_CAP_ID_EXP PCI Express
160 int pci_find_capability(struct pci_dev
*dev
, int cap
)
164 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
166 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
172 * pci_bus_find_capability - query for devices' capabilities
173 * @bus: the PCI bus to query
174 * @devfn: PCI device to query
175 * @cap: capability code
177 * Like pci_find_capability() but works for pci devices that do not have a
178 * pci_dev structure set up yet.
180 * Returns the address of the requested capability structure within the
181 * device's PCI configuration space or 0 in case the device does not
184 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
189 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
191 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
193 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
199 * pci_find_ext_capability - Find an extended capability
200 * @dev: PCI device to query
201 * @cap: capability code
203 * Returns the address of the requested extended capability structure
204 * within the device's PCI configuration space or 0 if the device does
205 * not support it. Possible values for @cap:
207 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
208 * %PCI_EXT_CAP_ID_VC Virtual Channel
209 * %PCI_EXT_CAP_ID_DSN Device Serial Number
210 * %PCI_EXT_CAP_ID_PWR Power Budgeting
212 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
215 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
218 if (dev
->cfg_size
<= 256)
221 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
225 * If we have no capabilities, this is indicated by cap ID,
226 * cap version and next pointer all being 0.
232 if (PCI_EXT_CAP_ID(header
) == cap
)
235 pos
= PCI_EXT_CAP_NEXT(header
);
239 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
245 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
247 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
249 int rc
, ttl
= PCI_FIND_CAP_TTL
;
252 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
253 mask
= HT_3BIT_CAP_MASK
;
255 mask
= HT_5BIT_CAP_MASK
;
257 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
258 PCI_CAP_ID_HT
, &ttl
);
260 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
261 if (rc
!= PCIBIOS_SUCCESSFUL
)
264 if ((cap
& mask
) == ht_cap
)
267 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
268 pos
+ PCI_CAP_LIST_NEXT
,
269 PCI_CAP_ID_HT
, &ttl
);
275 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
276 * @dev: PCI device to query
277 * @pos: Position from which to continue searching
278 * @ht_cap: Hypertransport capability code
280 * To be used in conjunction with pci_find_ht_capability() to search for
281 * all capabilities matching @ht_cap. @pos should always be a value returned
282 * from pci_find_ht_capability().
284 * NB. To be 100% safe against broken PCI devices, the caller should take
285 * steps to avoid an infinite loop.
287 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
289 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
291 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
294 * pci_find_ht_capability - query a device's Hypertransport capabilities
295 * @dev: PCI device to query
296 * @ht_cap: Hypertransport capability code
298 * Tell if a device supports a given Hypertransport capability.
299 * Returns an address within the device's PCI configuration space
300 * or 0 in case the device does not support the request capability.
301 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
302 * which has a Hypertransport capability matching @ht_cap.
304 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
308 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
310 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
314 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
317 * pci_find_parent_resource - return resource region of parent bus of given region
318 * @dev: PCI device structure contains resources to be searched
319 * @res: child resource record for which parent is sought
321 * For given resource region of given device, return the resource
322 * region of parent bus the given region is contained in or where
323 * it should be allocated from.
326 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
328 const struct pci_bus
*bus
= dev
->bus
;
330 struct resource
*best
= NULL
;
332 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
333 struct resource
*r
= bus
->resource
[i
];
336 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
337 continue; /* Not contained */
338 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
339 continue; /* Wrong type */
340 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
341 return r
; /* Exact match */
342 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
343 best
= r
; /* Approximating prefetchable by non-prefetchable */
349 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
350 * @dev: PCI device to have its BARs restored
352 * Restore the BAR values for a given device, so as to make it
353 * accessible by its driver.
356 pci_restore_bars(struct pci_dev
*dev
)
360 switch (dev
->hdr_type
) {
361 case PCI_HEADER_TYPE_NORMAL
:
364 case PCI_HEADER_TYPE_BRIDGE
:
367 case PCI_HEADER_TYPE_CARDBUS
:
371 /* Should never get here, but just in case... */
375 for (i
= 0; i
< numres
; i
++)
376 pci_update_resource(dev
, &dev
->resource
[i
], i
);
379 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
382 * pci_set_power_state - Set the power state of a PCI device
383 * @dev: PCI device to be suspended
384 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
386 * Transition a device to a new power state, using the Power Management
387 * Capabilities in the device's config space.
390 * -EINVAL if trying to enter a lower state than we're already in.
391 * 0 if we're already in the requested state.
392 * -EIO if device does not support PCI PM.
393 * 0 if we can successfully change the power state.
396 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
398 int pm
, need_restore
= 0;
401 /* bound the state we're entering */
402 if (state
> PCI_D3hot
)
406 * If the device or the parent bridge can't support PCI PM, ignore
407 * the request if we're doing anything besides putting it into D0
408 * (which would only happen on boot).
410 if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
413 /* find PCI PM capability in list */
414 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
416 /* abort if the device doesn't support PM capabilities */
420 /* Validate current state:
421 * Can enter D0 from any state, but if we can only go deeper
422 * to sleep if we're already in a low power state
424 if (state
!= PCI_D0
&& dev
->current_state
> state
) {
425 dev_err(&dev
->dev
, "invalid power transition "
426 "(from state %d to %d)\n", dev
->current_state
, state
);
428 } else if (dev
->current_state
== state
)
429 return 0; /* we're already there */
432 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
433 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
434 dev_printk(KERN_DEBUG
, &dev
->dev
, "unsupported PM cap regs "
435 "version (%u)\n", pmc
& PCI_PM_CAP_VER_MASK
);
439 /* check if this device supports the desired state */
440 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
442 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
445 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
447 /* If we're (effectively) in D3, force entire word to 0.
448 * This doesn't affect PME_Status, disables PME_En, and
449 * sets PowerState to 0.
451 switch (dev
->current_state
) {
455 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
458 case PCI_UNKNOWN
: /* Boot-up */
459 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
460 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
462 /* Fall-through: force to D0 */
468 /* enter specified state */
469 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
471 /* Mandatory power management transition delays */
472 /* see PCI PM 1.1 5.6.1 table 18 */
473 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
474 msleep(pci_pm_d3_delay
);
475 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
479 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
480 * Firmware method after native method ?
482 if (platform_pci_set_power_state
)
483 platform_pci_set_power_state(dev
, state
);
485 dev
->current_state
= state
;
487 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
488 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
489 * from D3hot to D0 _may_ perform an internal reset, thereby
490 * going to "D0 Uninitialized" rather than "D0 Initialized".
491 * For example, at least some versions of the 3c905B and the
492 * 3c556B exhibit this behaviour.
494 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
495 * devices in a D3hot state at boot. Consequently, we need to
496 * restore at least the BARs so that the device will be
497 * accessible to its driver.
500 pci_restore_bars(dev
);
503 pcie_aspm_pm_state_change(dev
->bus
->self
);
508 pci_power_t (*platform_pci_choose_state
)(struct pci_dev
*dev
);
511 * pci_choose_state - Choose the power state of a PCI device
512 * @dev: PCI device to be suspended
513 * @state: target sleep state for the whole system. This is the value
514 * that is passed to suspend() function.
516 * Returns PCI power state suitable for given device and given system
520 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
524 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
527 if (platform_pci_choose_state
) {
528 ret
= platform_pci_choose_state(dev
);
529 if (ret
!= PCI_POWER_ERROR
)
533 switch (state
.event
) {
536 case PM_EVENT_FREEZE
:
537 case PM_EVENT_PRETHAW
:
538 /* REVISIT both freeze and pre-thaw "should" use D0 */
539 case PM_EVENT_SUSPEND
:
540 case PM_EVENT_HIBERNATE
:
543 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
550 EXPORT_SYMBOL(pci_choose_state
);
552 static int pci_save_pcie_state(struct pci_dev
*dev
)
555 struct pci_cap_saved_state
*save_state
;
559 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
563 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
565 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
) * 4, GFP_KERNEL
);
569 dev_err(&dev
->dev
, "out of memory in pci_save_pcie_state\n");
572 cap
= (u16
*)&save_state
->data
[0];
574 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
575 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
576 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
577 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
578 save_state
->cap_nr
= PCI_CAP_ID_EXP
;
580 pci_add_saved_cap(dev
, save_state
);
584 static void pci_restore_pcie_state(struct pci_dev
*dev
)
587 struct pci_cap_saved_state
*save_state
;
590 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
591 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
592 if (!save_state
|| pos
<= 0)
594 cap
= (u16
*)&save_state
->data
[0];
596 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
597 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
598 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
599 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
603 static int pci_save_pcix_state(struct pci_dev
*dev
)
606 struct pci_cap_saved_state
*save_state
;
610 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
614 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
616 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
), GFP_KERNEL
);
620 dev_err(&dev
->dev
, "out of memory in pci_save_pcie_state\n");
623 cap
= (u16
*)&save_state
->data
[0];
625 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, &cap
[i
++]);
626 save_state
->cap_nr
= PCI_CAP_ID_PCIX
;
628 pci_add_saved_cap(dev
, save_state
);
632 static void pci_restore_pcix_state(struct pci_dev
*dev
)
635 struct pci_cap_saved_state
*save_state
;
638 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
639 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
640 if (!save_state
|| pos
<= 0)
642 cap
= (u16
*)&save_state
->data
[0];
644 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
649 * pci_save_state - save the PCI configuration space of a device before suspending
650 * @dev: - PCI device that we're dealing with
653 pci_save_state(struct pci_dev
*dev
)
656 /* XXX: 100% dword access ok here? */
657 for (i
= 0; i
< 16; i
++)
658 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
659 if ((i
= pci_save_pcie_state(dev
)) != 0)
661 if ((i
= pci_save_pcix_state(dev
)) != 0)
667 * pci_restore_state - Restore the saved state of a PCI device
668 * @dev: - PCI device that we're dealing with
671 pci_restore_state(struct pci_dev
*dev
)
676 /* PCI Express register must be restored first */
677 pci_restore_pcie_state(dev
);
680 * The Base Address register should be programmed before the command
683 for (i
= 15; i
>= 0; i
--) {
684 pci_read_config_dword(dev
, i
* 4, &val
);
685 if (val
!= dev
->saved_config_space
[i
]) {
686 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
687 "space at offset %#x (was %#x, writing %#x)\n",
688 i
, val
, (int)dev
->saved_config_space
[i
]);
689 pci_write_config_dword(dev
,i
* 4,
690 dev
->saved_config_space
[i
]);
693 pci_restore_pcix_state(dev
);
694 pci_restore_msi_state(dev
);
699 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
703 err
= pci_set_power_state(dev
, PCI_D0
);
704 if (err
< 0 && err
!= -EIO
)
706 err
= pcibios_enable_device(dev
, bars
);
709 pci_fixup_device(pci_fixup_enable
, dev
);
715 * pci_reenable_device - Resume abandoned device
716 * @dev: PCI device to be resumed
718 * Note this function is a backend of pci_default_resume and is not supposed
719 * to be called by normal code, write proper resume handler and use it instead.
721 int pci_reenable_device(struct pci_dev
*dev
)
723 if (atomic_read(&dev
->enable_cnt
))
724 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
728 static int __pci_enable_device_flags(struct pci_dev
*dev
,
729 resource_size_t flags
)
734 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
735 return 0; /* already enabled */
737 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
738 if (dev
->resource
[i
].flags
& flags
)
741 err
= do_pci_enable_device(dev
, bars
);
743 atomic_dec(&dev
->enable_cnt
);
748 * pci_enable_device_io - Initialize a device for use with IO space
749 * @dev: PCI device to be initialized
751 * Initialize device before it's used by a driver. Ask low-level code
752 * to enable I/O resources. Wake up the device if it was suspended.
753 * Beware, this function can fail.
755 int pci_enable_device_io(struct pci_dev
*dev
)
757 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
761 * pci_enable_device_mem - Initialize a device for use with Memory space
762 * @dev: PCI device to be initialized
764 * Initialize device before it's used by a driver. Ask low-level code
765 * to enable Memory resources. Wake up the device if it was suspended.
766 * Beware, this function can fail.
768 int pci_enable_device_mem(struct pci_dev
*dev
)
770 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
774 * pci_enable_device - Initialize device before it's used by a driver.
775 * @dev: PCI device to be initialized
777 * Initialize device before it's used by a driver. Ask low-level code
778 * to enable I/O and memory. Wake up the device if it was suspended.
779 * Beware, this function can fail.
781 * Note we don't actually enable the device many times if we call
782 * this function repeatedly (we just increment the count).
784 int pci_enable_device(struct pci_dev
*dev
)
786 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
790 * Managed PCI resources. This manages device on/off, intx/msi/msix
791 * on/off and BAR regions. pci_dev itself records msi/msix status, so
792 * there's no need to track it separately. pci_devres is initialized
793 * when a device is enabled using managed PCI device enable interface.
796 unsigned int enabled
:1;
797 unsigned int pinned
:1;
798 unsigned int orig_intx
:1;
799 unsigned int restore_intx
:1;
803 static void pcim_release(struct device
*gendev
, void *res
)
805 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
806 struct pci_devres
*this = res
;
809 if (dev
->msi_enabled
)
810 pci_disable_msi(dev
);
811 if (dev
->msix_enabled
)
812 pci_disable_msix(dev
);
814 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
815 if (this->region_mask
& (1 << i
))
816 pci_release_region(dev
, i
);
818 if (this->restore_intx
)
819 pci_intx(dev
, this->orig_intx
);
821 if (this->enabled
&& !this->pinned
)
822 pci_disable_device(dev
);
825 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
827 struct pci_devres
*dr
, *new_dr
;
829 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
833 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
836 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
839 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
841 if (pci_is_managed(pdev
))
842 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
847 * pcim_enable_device - Managed pci_enable_device()
848 * @pdev: PCI device to be initialized
850 * Managed pci_enable_device().
852 int pcim_enable_device(struct pci_dev
*pdev
)
854 struct pci_devres
*dr
;
857 dr
= get_pci_dr(pdev
);
863 rc
= pci_enable_device(pdev
);
865 pdev
->is_managed
= 1;
872 * pcim_pin_device - Pin managed PCI device
873 * @pdev: PCI device to pin
875 * Pin managed PCI device @pdev. Pinned device won't be disabled on
876 * driver detach. @pdev must have been enabled with
877 * pcim_enable_device().
879 void pcim_pin_device(struct pci_dev
*pdev
)
881 struct pci_devres
*dr
;
883 dr
= find_pci_dr(pdev
);
884 WARN_ON(!dr
|| !dr
->enabled
);
890 * pcibios_disable_device - disable arch specific PCI resources for device dev
891 * @dev: the PCI device to disable
893 * Disables architecture specific PCI resources for the device. This
894 * is the default implementation. Architecture implementations can
897 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
900 * pci_disable_device - Disable PCI device after use
901 * @dev: PCI device to be disabled
903 * Signal to the system that the PCI device is not in use by the system
904 * anymore. This only involves disabling PCI bus-mastering, if active.
906 * Note we don't actually disable the device until all callers of
907 * pci_device_enable() have called pci_device_disable().
910 pci_disable_device(struct pci_dev
*dev
)
912 struct pci_devres
*dr
;
915 dr
= find_pci_dr(dev
);
919 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
922 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
923 if (pci_command
& PCI_COMMAND_MASTER
) {
924 pci_command
&= ~PCI_COMMAND_MASTER
;
925 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
927 dev
->is_busmaster
= 0;
929 pcibios_disable_device(dev
);
933 * pcibios_set_pcie_reset_state - set reset state for device dev
934 * @dev: the PCI-E device reset
935 * @state: Reset state to enter into
938 * Sets the PCI-E reset state for the device. This is the default
939 * implementation. Architecture implementations can override this.
941 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
942 enum pcie_reset_state state
)
948 * pci_set_pcie_reset_state - set reset state for device dev
949 * @dev: the PCI-E device reset
950 * @state: Reset state to enter into
953 * Sets the PCI reset state for the device.
955 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
957 return pcibios_set_pcie_reset_state(dev
, state
);
961 * pci_enable_wake - enable PCI device as wakeup event source
962 * @dev: PCI device affected
963 * @state: PCI state from which device will issue wakeup events
964 * @enable: True to enable event generation; false to disable
966 * This enables the device as a wakeup event source, or disables it.
967 * When such events involves platform-specific hooks, those hooks are
968 * called automatically by this routine.
970 * Devices with legacy power management (no standard PCI PM capabilities)
971 * always require such platform hooks. Depending on the platform, devices
972 * supporting the standard PCI PME# signal may require such platform hooks;
973 * they always update bits in config space to allow PME# generation.
975 * -EIO is returned if the device can't ever be a wakeup event source.
976 * -EINVAL is returned if the device can't generate wakeup events from
977 * the specified PCI state. Returns zero if the operation is successful.
979 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
985 /* Note that drivers should verify device_may_wakeup(&dev->dev)
986 * before calling this function. Platform code should report
987 * errors when drivers try to enable wakeup on devices that
988 * can't issue wakeups, or on which wakeups were disabled by
989 * userspace updating the /sys/devices.../power/wakeup file.
992 status
= call_platform_enable_wakeup(&dev
->dev
, enable
);
994 /* find PCI PM capability in list */
995 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
997 /* If device doesn't support PM Capabilities, but caller wants to
998 * disable wake events, it's a NOP. Otherwise fail unless the
999 * platform hooks handled this legacy device already.
1002 return enable
? status
: 0;
1004 /* Check device's ability to generate PME# */
1005 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
1007 value
&= PCI_PM_CAP_PME_MASK
;
1008 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
1010 /* Check if it can generate PME# from requested state. */
1011 if (!value
|| !(value
& (1 << state
))) {
1012 /* if it can't, revert what the platform hook changed,
1013 * always reporting the base "EINVAL, can't PME#" error
1016 call_platform_enable_wakeup(&dev
->dev
, 0);
1017 return enable
? -EINVAL
: 0;
1020 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
1022 /* Clear PME_Status by writing 1 to it and enable PME# */
1023 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1026 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
1028 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
1034 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1042 while (dev
->bus
->self
) {
1043 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
1044 dev
= dev
->bus
->self
;
1051 * pci_release_region - Release a PCI bar
1052 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1053 * @bar: BAR to release
1055 * Releases the PCI I/O and memory resources previously reserved by a
1056 * successful call to pci_request_region. Call this function only
1057 * after all use of the PCI regions has ceased.
1059 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1061 struct pci_devres
*dr
;
1063 if (pci_resource_len(pdev
, bar
) == 0)
1065 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1066 release_region(pci_resource_start(pdev
, bar
),
1067 pci_resource_len(pdev
, bar
));
1068 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1069 release_mem_region(pci_resource_start(pdev
, bar
),
1070 pci_resource_len(pdev
, bar
));
1072 dr
= find_pci_dr(pdev
);
1074 dr
->region_mask
&= ~(1 << bar
);
1078 * pci_request_region - Reserved PCI I/O and memory resource
1079 * @pdev: PCI device whose resources are to be reserved
1080 * @bar: BAR to be reserved
1081 * @res_name: Name to be associated with resource.
1083 * Mark the PCI region associated with PCI device @pdev BR @bar as
1084 * being reserved by owner @res_name. Do not access any
1085 * address inside the PCI regions unless this call returns
1088 * Returns 0 on success, or %EBUSY on error. A warning
1089 * message is also printed on failure.
1091 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1093 struct pci_devres
*dr
;
1095 if (pci_resource_len(pdev
, bar
) == 0)
1098 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1099 if (!request_region(pci_resource_start(pdev
, bar
),
1100 pci_resource_len(pdev
, bar
), res_name
))
1103 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1104 if (!request_mem_region(pci_resource_start(pdev
, bar
),
1105 pci_resource_len(pdev
, bar
), res_name
))
1109 dr
= find_pci_dr(pdev
);
1111 dr
->region_mask
|= 1 << bar
;
1116 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
1118 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1119 (unsigned long long)pci_resource_start(pdev
, bar
),
1120 (unsigned long long)pci_resource_end(pdev
, bar
));
1125 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1126 * @pdev: PCI device whose resources were previously reserved
1127 * @bars: Bitmask of BARs to be released
1129 * Release selected PCI I/O and memory resources previously reserved.
1130 * Call this function only after all use of the PCI regions has ceased.
1132 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1136 for (i
= 0; i
< 6; i
++)
1137 if (bars
& (1 << i
))
1138 pci_release_region(pdev
, i
);
1142 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1143 * @pdev: PCI device whose resources are to be reserved
1144 * @bars: Bitmask of BARs to be requested
1145 * @res_name: Name to be associated with resource
1147 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1148 const char *res_name
)
1152 for (i
= 0; i
< 6; i
++)
1153 if (bars
& (1 << i
))
1154 if(pci_request_region(pdev
, i
, res_name
))
1160 if (bars
& (1 << i
))
1161 pci_release_region(pdev
, i
);
1167 * pci_release_regions - Release reserved PCI I/O and memory resources
1168 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1170 * Releases all PCI I/O and memory resources previously reserved by a
1171 * successful call to pci_request_regions. Call this function only
1172 * after all use of the PCI regions has ceased.
1175 void pci_release_regions(struct pci_dev
*pdev
)
1177 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1181 * pci_request_regions - Reserved PCI I/O and memory resources
1182 * @pdev: PCI device whose resources are to be reserved
1183 * @res_name: Name to be associated with resource.
1185 * Mark all PCI regions associated with PCI device @pdev as
1186 * being reserved by owner @res_name. Do not access any
1187 * address inside the PCI regions unless this call returns
1190 * Returns 0 on success, or %EBUSY on error. A warning
1191 * message is also printed on failure.
1193 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1195 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1199 * pci_set_master - enables bus-mastering for device dev
1200 * @dev: the PCI device to enable
1202 * Enables bus-mastering on the device and calls pcibios_set_master()
1203 * to do the needed arch specific settings.
1206 pci_set_master(struct pci_dev
*dev
)
1210 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1211 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1212 dev_dbg(&dev
->dev
, "enabling bus mastering\n");
1213 cmd
|= PCI_COMMAND_MASTER
;
1214 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1216 dev
->is_busmaster
= 1;
1217 pcibios_set_master(dev
);
1220 #ifdef PCI_DISABLE_MWI
1221 int pci_set_mwi(struct pci_dev
*dev
)
1226 int pci_try_set_mwi(struct pci_dev
*dev
)
1231 void pci_clear_mwi(struct pci_dev
*dev
)
1237 #ifndef PCI_CACHE_LINE_BYTES
1238 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1241 /* This can be overridden by arch code. */
1242 /* Don't forget this is measured in 32-bit words, not bytes */
1243 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1246 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1247 * @dev: the PCI device for which MWI is to be enabled
1249 * Helper function for pci_set_mwi.
1250 * Originally copied from drivers/net/acenic.c.
1251 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1253 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1256 pci_set_cacheline_size(struct pci_dev
*dev
)
1260 if (!pci_cache_line_size
)
1261 return -EINVAL
; /* The system doesn't support MWI. */
1263 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1264 equal to or multiple of the right value. */
1265 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1266 if (cacheline_size
>= pci_cache_line_size
&&
1267 (cacheline_size
% pci_cache_line_size
) == 0)
1270 /* Write the correct value. */
1271 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1273 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1274 if (cacheline_size
== pci_cache_line_size
)
1277 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1278 "supported\n", pci_cache_line_size
<< 2);
1284 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1285 * @dev: the PCI device for which MWI is enabled
1287 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1289 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1292 pci_set_mwi(struct pci_dev
*dev
)
1297 rc
= pci_set_cacheline_size(dev
);
1301 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1302 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1303 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1304 cmd
|= PCI_COMMAND_INVALIDATE
;
1305 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1312 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1313 * @dev: the PCI device for which MWI is enabled
1315 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1316 * Callers are not required to check the return value.
1318 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1320 int pci_try_set_mwi(struct pci_dev
*dev
)
1322 int rc
= pci_set_mwi(dev
);
1327 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1328 * @dev: the PCI device to disable
1330 * Disables PCI Memory-Write-Invalidate transaction on the device
1333 pci_clear_mwi(struct pci_dev
*dev
)
1337 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1338 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1339 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1340 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1343 #endif /* ! PCI_DISABLE_MWI */
1346 * pci_intx - enables/disables PCI INTx for device dev
1347 * @pdev: the PCI device to operate on
1348 * @enable: boolean: whether to enable or disable PCI INTx
1350 * Enables/disables PCI INTx for device dev
1353 pci_intx(struct pci_dev
*pdev
, int enable
)
1355 u16 pci_command
, new;
1357 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1360 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1362 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1365 if (new != pci_command
) {
1366 struct pci_devres
*dr
;
1368 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1370 dr
= find_pci_dr(pdev
);
1371 if (dr
&& !dr
->restore_intx
) {
1372 dr
->restore_intx
= 1;
1373 dr
->orig_intx
= !enable
;
1379 * pci_msi_off - disables any msi or msix capabilities
1380 * @dev: the PCI device to operate on
1382 * If you want to use msi see pci_enable_msi and friends.
1383 * This is a lower level primitive that allows us to disable
1384 * msi operation at the device level.
1386 void pci_msi_off(struct pci_dev
*dev
)
1391 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1393 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1394 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1395 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1397 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1399 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1400 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1401 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1405 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1407 * These can be overridden by arch-specific implementations
1410 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1412 if (!pci_dma_supported(dev
, mask
))
1415 dev
->dma_mask
= mask
;
1421 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1423 if (!pci_dma_supported(dev
, mask
))
1426 dev
->dev
.coherent_dma_mask
= mask
;
1432 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1433 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1435 return dma_set_max_seg_size(&dev
->dev
, size
);
1437 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1440 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1441 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1443 return dma_set_seg_boundary(&dev
->dev
, mask
);
1445 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1449 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1450 * @dev: PCI device to query
1452 * Returns mmrbc: maximum designed memory read count in bytes
1453 * or appropriate error value.
1455 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
1460 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1464 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1468 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
1470 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
1473 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1474 * @dev: PCI device to query
1476 * Returns mmrbc: maximum memory read count in bytes
1477 * or appropriate error value.
1479 int pcix_get_mmrbc(struct pci_dev
*dev
)
1484 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1488 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1490 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
1494 EXPORT_SYMBOL(pcix_get_mmrbc
);
1497 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1498 * @dev: PCI device to query
1499 * @mmrbc: maximum memory read count in bytes
1500 * valid values are 512, 1024, 2048, 4096
1502 * If possible sets maximum memory read byte count, some bridges have erratas
1503 * that prevent this.
1505 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
1507 int cap
, err
= -EINVAL
;
1508 u32 stat
, cmd
, v
, o
;
1510 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
1513 v
= ffs(mmrbc
) - 10;
1515 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1519 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1523 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
1526 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1530 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
1532 if (v
> o
&& dev
->bus
&&
1533 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
1536 cmd
&= ~PCI_X_CMD_MAX_READ
;
1538 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
1543 EXPORT_SYMBOL(pcix_set_mmrbc
);
1546 * pcie_get_readrq - get PCI Express read request size
1547 * @dev: PCI device to query
1549 * Returns maximum memory read request in bytes
1550 * or appropriate error value.
1552 int pcie_get_readrq(struct pci_dev
*dev
)
1557 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1561 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1563 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
1567 EXPORT_SYMBOL(pcie_get_readrq
);
1570 * pcie_set_readrq - set PCI Express maximum memory read request
1571 * @dev: PCI device to query
1572 * @rq: maximum memory read count in bytes
1573 * valid values are 128, 256, 512, 1024, 2048, 4096
1575 * If possible sets maximum read byte count
1577 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
1579 int cap
, err
= -EINVAL
;
1582 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
1585 v
= (ffs(rq
) - 8) << 12;
1587 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1591 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1595 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
1596 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
1598 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
1604 EXPORT_SYMBOL(pcie_set_readrq
);
1607 * pci_select_bars - Make BAR mask from the type of resource
1608 * @dev: the PCI device for which BAR mask is made
1609 * @flags: resource type mask to be selected
1611 * This helper routine makes bar mask from the type of resource.
1613 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
1616 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1617 if (pci_resource_flags(dev
, i
) & flags
)
1622 static void __devinit
pci_no_domains(void)
1624 #ifdef CONFIG_PCI_DOMAINS
1625 pci_domains_supported
= 0;
1629 static int __devinit
pci_init(void)
1631 struct pci_dev
*dev
= NULL
;
1633 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1634 pci_fixup_device(pci_fixup_final
, dev
);
1639 static int __devinit
pci_setup(char *str
)
1642 char *k
= strchr(str
, ',');
1645 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1646 if (!strcmp(str
, "nomsi")) {
1648 } else if (!strcmp(str
, "noaer")) {
1650 } else if (!strcmp(str
, "nodomains")) {
1652 } else if (!strncmp(str
, "cbiosize=", 9)) {
1653 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
1654 } else if (!strncmp(str
, "cbmemsize=", 10)) {
1655 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
1657 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
1665 early_param("pci", pci_setup
);
1667 device_initcall(pci_init
);
1669 EXPORT_SYMBOL(pci_reenable_device
);
1670 EXPORT_SYMBOL(pci_enable_device_io
);
1671 EXPORT_SYMBOL(pci_enable_device_mem
);
1672 EXPORT_SYMBOL(pci_enable_device
);
1673 EXPORT_SYMBOL(pcim_enable_device
);
1674 EXPORT_SYMBOL(pcim_pin_device
);
1675 EXPORT_SYMBOL(pci_disable_device
);
1676 EXPORT_SYMBOL(pci_find_capability
);
1677 EXPORT_SYMBOL(pci_bus_find_capability
);
1678 EXPORT_SYMBOL(pci_release_regions
);
1679 EXPORT_SYMBOL(pci_request_regions
);
1680 EXPORT_SYMBOL(pci_release_region
);
1681 EXPORT_SYMBOL(pci_request_region
);
1682 EXPORT_SYMBOL(pci_release_selected_regions
);
1683 EXPORT_SYMBOL(pci_request_selected_regions
);
1684 EXPORT_SYMBOL(pci_set_master
);
1685 EXPORT_SYMBOL(pci_set_mwi
);
1686 EXPORT_SYMBOL(pci_try_set_mwi
);
1687 EXPORT_SYMBOL(pci_clear_mwi
);
1688 EXPORT_SYMBOL_GPL(pci_intx
);
1689 EXPORT_SYMBOL(pci_set_dma_mask
);
1690 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
1691 EXPORT_SYMBOL(pci_assign_resource
);
1692 EXPORT_SYMBOL(pci_find_parent_resource
);
1693 EXPORT_SYMBOL(pci_select_bars
);
1695 EXPORT_SYMBOL(pci_set_power_state
);
1696 EXPORT_SYMBOL(pci_save_state
);
1697 EXPORT_SYMBOL(pci_restore_state
);
1698 EXPORT_SYMBOL(pci_enable_wake
);
1699 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);