2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported
= 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
35 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
46 struct list_head
*tmp
;
49 max
= bus
->subordinate
;
50 list_for_each(tmp
, &bus
->children
) {
51 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
59 #ifdef CONFIG_HAS_IOMEM
60 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
63 * Make sure the BAR is actually a memory resource, not an IO resource
65 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
69 return ioremap_nocache(pci_resource_start(pdev
, bar
),
70 pci_resource_len(pdev
, bar
));
72 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
77 * pci_max_busnr - returns maximum PCI bus number
79 * Returns the highest PCI bus number present in the system global list of
82 unsigned char __devinit
85 struct pci_bus
*bus
= NULL
;
89 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
90 n
= pci_bus_max_busnr(bus
);
99 #define PCI_FIND_CAP_TTL 48
101 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
102 u8 pos
, int cap
, int *ttl
)
107 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
111 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
117 pos
+= PCI_CAP_LIST_NEXT
;
122 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
125 int ttl
= PCI_FIND_CAP_TTL
;
127 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
130 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
132 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
133 pos
+ PCI_CAP_LIST_NEXT
, cap
);
135 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
137 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
138 unsigned int devfn
, u8 hdr_type
)
142 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
143 if (!(status
& PCI_STATUS_CAP_LIST
))
147 case PCI_HEADER_TYPE_NORMAL
:
148 case PCI_HEADER_TYPE_BRIDGE
:
149 return PCI_CAPABILITY_LIST
;
150 case PCI_HEADER_TYPE_CARDBUS
:
151 return PCI_CB_CAPABILITY_LIST
;
160 * pci_find_capability - query for devices' capabilities
161 * @dev: PCI device to query
162 * @cap: capability code
164 * Tell if a device supports a given PCI capability.
165 * Returns the address of the requested capability structure within the
166 * device's PCI configuration space or 0 in case the device does not
167 * support it. Possible values for @cap:
169 * %PCI_CAP_ID_PM Power Management
170 * %PCI_CAP_ID_AGP Accelerated Graphics Port
171 * %PCI_CAP_ID_VPD Vital Product Data
172 * %PCI_CAP_ID_SLOTID Slot Identification
173 * %PCI_CAP_ID_MSI Message Signalled Interrupts
174 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
175 * %PCI_CAP_ID_PCIX PCI-X
176 * %PCI_CAP_ID_EXP PCI Express
178 int pci_find_capability(struct pci_dev
*dev
, int cap
)
182 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
184 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
190 * pci_bus_find_capability - query for devices' capabilities
191 * @bus: the PCI bus to query
192 * @devfn: PCI device to query
193 * @cap: capability code
195 * Like pci_find_capability() but works for pci devices that do not have a
196 * pci_dev structure set up yet.
198 * Returns the address of the requested capability structure within the
199 * device's PCI configuration space or 0 in case the device does not
202 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
207 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
209 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
211 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
217 * pci_find_ext_capability - Find an extended capability
218 * @dev: PCI device to query
219 * @cap: capability code
221 * Returns the address of the requested extended capability structure
222 * within the device's PCI configuration space or 0 if the device does
223 * not support it. Possible values for @cap:
225 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
226 * %PCI_EXT_CAP_ID_VC Virtual Channel
227 * %PCI_EXT_CAP_ID_DSN Device Serial Number
228 * %PCI_EXT_CAP_ID_PWR Power Budgeting
230 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
234 int pos
= PCI_CFG_SPACE_SIZE
;
236 /* minimum 8 bytes per capability */
237 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
239 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
242 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
246 * If we have no capabilities, this is indicated by cap ID,
247 * cap version and next pointer all being 0.
253 if (PCI_EXT_CAP_ID(header
) == cap
)
256 pos
= PCI_EXT_CAP_NEXT(header
);
257 if (pos
< PCI_CFG_SPACE_SIZE
)
260 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
266 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
268 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
270 int rc
, ttl
= PCI_FIND_CAP_TTL
;
273 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
274 mask
= HT_3BIT_CAP_MASK
;
276 mask
= HT_5BIT_CAP_MASK
;
278 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
279 PCI_CAP_ID_HT
, &ttl
);
281 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
282 if (rc
!= PCIBIOS_SUCCESSFUL
)
285 if ((cap
& mask
) == ht_cap
)
288 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
289 pos
+ PCI_CAP_LIST_NEXT
,
290 PCI_CAP_ID_HT
, &ttl
);
296 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
297 * @dev: PCI device to query
298 * @pos: Position from which to continue searching
299 * @ht_cap: Hypertransport capability code
301 * To be used in conjunction with pci_find_ht_capability() to search for
302 * all capabilities matching @ht_cap. @pos should always be a value returned
303 * from pci_find_ht_capability().
305 * NB. To be 100% safe against broken PCI devices, the caller should take
306 * steps to avoid an infinite loop.
308 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
310 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
312 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
315 * pci_find_ht_capability - query a device's Hypertransport capabilities
316 * @dev: PCI device to query
317 * @ht_cap: Hypertransport capability code
319 * Tell if a device supports a given Hypertransport capability.
320 * Returns an address within the device's PCI configuration space
321 * or 0 in case the device does not support the request capability.
322 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
323 * which has a Hypertransport capability matching @ht_cap.
325 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
329 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
331 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
335 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
338 * pci_find_parent_resource - return resource region of parent bus of given region
339 * @dev: PCI device structure contains resources to be searched
340 * @res: child resource record for which parent is sought
342 * For given resource region of given device, return the resource
343 * region of parent bus the given region is contained in or where
344 * it should be allocated from.
347 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
349 const struct pci_bus
*bus
= dev
->bus
;
351 struct resource
*best
= NULL
;
353 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
354 struct resource
*r
= bus
->resource
[i
];
357 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
358 continue; /* Not contained */
359 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
360 continue; /* Wrong type */
361 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
362 return r
; /* Exact match */
363 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
364 best
= r
; /* Approximating prefetchable by non-prefetchable */
370 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
371 * @dev: PCI device to have its BARs restored
373 * Restore the BAR values for a given device, so as to make it
374 * accessible by its driver.
377 pci_restore_bars(struct pci_dev
*dev
)
381 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
382 pci_update_resource(dev
, i
);
385 static struct pci_platform_pm_ops
*pci_platform_pm
;
387 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
389 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
390 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
392 pci_platform_pm
= ops
;
396 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
398 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
401 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
404 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
407 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
409 return pci_platform_pm
?
410 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
413 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
415 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
418 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
420 return pci_platform_pm
?
421 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
425 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
427 * @dev: PCI device to handle.
428 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
431 * -EINVAL if the requested state is invalid.
432 * -EIO if device does not support PCI PM or its PM capabilities register has a
433 * wrong version, or device doesn't support the requested state.
434 * 0 if device already is in the requested state.
435 * 0 if device's power state has been successfully changed.
437 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
440 bool need_restore
= false;
442 /* Check if we're already there */
443 if (dev
->current_state
== state
)
449 if (state
< PCI_D0
|| state
> PCI_D3hot
)
452 /* Validate current state:
453 * Can enter D0 from any state, but if we can only go deeper
454 * to sleep if we're already in a low power state
456 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
457 && dev
->current_state
> state
) {
458 dev_err(&dev
->dev
, "invalid power transition "
459 "(from state %d to %d)\n", dev
->current_state
, state
);
463 /* check if this device supports the desired state */
464 if ((state
== PCI_D1
&& !dev
->d1_support
)
465 || (state
== PCI_D2
&& !dev
->d2_support
))
468 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
470 /* If we're (effectively) in D3, force entire word to 0.
471 * This doesn't affect PME_Status, disables PME_En, and
472 * sets PowerState to 0.
474 switch (dev
->current_state
) {
478 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
481 case PCI_UNKNOWN
: /* Boot-up */
482 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
483 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
485 /* Fall-through: force to D0 */
491 /* enter specified state */
492 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
494 /* Mandatory power management transition delays */
495 /* see PCI PM 1.1 5.6.1 table 18 */
496 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
497 msleep(pci_pm_d3_delay
);
498 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
499 udelay(PCI_PM_D2_DELAY
);
501 dev
->current_state
= state
;
503 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
504 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
505 * from D3hot to D0 _may_ perform an internal reset, thereby
506 * going to "D0 Uninitialized" rather than "D0 Initialized".
507 * For example, at least some versions of the 3c905B and the
508 * 3c556B exhibit this behaviour.
510 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
511 * devices in a D3hot state at boot. Consequently, we need to
512 * restore at least the BARs so that the device will be
513 * accessible to its driver.
516 pci_restore_bars(dev
);
519 pcie_aspm_pm_state_change(dev
->bus
->self
);
525 * pci_update_current_state - Read PCI power state of given device from its
526 * PCI PM registers and cache it
527 * @dev: PCI device to handle.
528 * @state: State to cache in case the device doesn't have the PM capability
530 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
535 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
536 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
538 dev
->current_state
= state
;
543 * pci_set_power_state - Set the power state of a PCI device
544 * @dev: PCI device to handle.
545 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
547 * Transition a device to a new power state, using the platform formware and/or
548 * the device's PCI PM registers.
551 * -EINVAL if the requested state is invalid.
552 * -EIO if device does not support PCI PM or its PM capabilities register has a
553 * wrong version, or device doesn't support the requested state.
554 * 0 if device already is in the requested state.
555 * 0 if device's power state has been successfully changed.
557 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
561 /* bound the state we're entering */
562 if (state
> PCI_D3hot
)
564 else if (state
< PCI_D0
)
566 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
568 * If the device or the parent bridge do not support PCI PM,
569 * ignore the request if we're doing anything other than putting
570 * it into D0 (which would only happen on boot).
574 /* Check if we're already there */
575 if (dev
->current_state
== state
)
578 if (state
== PCI_D0
) {
580 * Allow the platform to change the state, for example via ACPI
581 * _PR0, _PS0 and some such, but do not trust it.
583 int ret
= platform_pci_power_manageable(dev
) ?
584 platform_pci_set_power_state(dev
, PCI_D0
) : 0;
586 pci_update_current_state(dev
, PCI_D0
);
588 /* This device is quirked not to be put into D3, so
589 don't put it in D3 */
590 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
593 error
= pci_raw_set_power_state(dev
, state
);
595 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
596 /* Allow the platform to finalize the transition */
597 int ret
= platform_pci_set_power_state(dev
, state
);
599 pci_update_current_state(dev
, state
);
608 * pci_choose_state - Choose the power state of a PCI device
609 * @dev: PCI device to be suspended
610 * @state: target sleep state for the whole system. This is the value
611 * that is passed to suspend() function.
613 * Returns PCI power state suitable for given device and given system
617 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
621 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
624 ret
= platform_pci_choose_state(dev
);
625 if (ret
!= PCI_POWER_ERROR
)
628 switch (state
.event
) {
631 case PM_EVENT_FREEZE
:
632 case PM_EVENT_PRETHAW
:
633 /* REVISIT both freeze and pre-thaw "should" use D0 */
634 case PM_EVENT_SUSPEND
:
635 case PM_EVENT_HIBERNATE
:
638 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
645 EXPORT_SYMBOL(pci_choose_state
);
647 static int pci_save_pcie_state(struct pci_dev
*dev
)
650 struct pci_cap_saved_state
*save_state
;
653 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
657 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
659 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
662 cap
= (u16
*)&save_state
->data
[0];
664 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
665 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
666 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
667 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
672 static void pci_restore_pcie_state(struct pci_dev
*dev
)
675 struct pci_cap_saved_state
*save_state
;
678 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
679 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
680 if (!save_state
|| pos
<= 0)
682 cap
= (u16
*)&save_state
->data
[0];
684 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
685 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
686 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
687 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
691 static int pci_save_pcix_state(struct pci_dev
*dev
)
694 struct pci_cap_saved_state
*save_state
;
696 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
700 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
702 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
706 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
711 static void pci_restore_pcix_state(struct pci_dev
*dev
)
714 struct pci_cap_saved_state
*save_state
;
717 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
718 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
719 if (!save_state
|| pos
<= 0)
721 cap
= (u16
*)&save_state
->data
[0];
723 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
728 * pci_save_state - save the PCI configuration space of a device before suspending
729 * @dev: - PCI device that we're dealing with
732 pci_save_state(struct pci_dev
*dev
)
735 /* XXX: 100% dword access ok here? */
736 for (i
= 0; i
< 16; i
++)
737 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
738 dev
->state_saved
= true;
739 if ((i
= pci_save_pcie_state(dev
)) != 0)
741 if ((i
= pci_save_pcix_state(dev
)) != 0)
747 * pci_restore_state - Restore the saved state of a PCI device
748 * @dev: - PCI device that we're dealing with
751 pci_restore_state(struct pci_dev
*dev
)
756 /* PCI Express register must be restored first */
757 pci_restore_pcie_state(dev
);
760 * The Base Address register should be programmed before the command
763 for (i
= 15; i
>= 0; i
--) {
764 pci_read_config_dword(dev
, i
* 4, &val
);
765 if (val
!= dev
->saved_config_space
[i
]) {
766 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
767 "space at offset %#x (was %#x, writing %#x)\n",
768 i
, val
, (int)dev
->saved_config_space
[i
]);
769 pci_write_config_dword(dev
,i
* 4,
770 dev
->saved_config_space
[i
]);
773 pci_restore_pcix_state(dev
);
774 pci_restore_msi_state(dev
);
779 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
783 err
= pci_set_power_state(dev
, PCI_D0
);
784 if (err
< 0 && err
!= -EIO
)
786 err
= pcibios_enable_device(dev
, bars
);
789 pci_fixup_device(pci_fixup_enable
, dev
);
795 * pci_reenable_device - Resume abandoned device
796 * @dev: PCI device to be resumed
798 * Note this function is a backend of pci_default_resume and is not supposed
799 * to be called by normal code, write proper resume handler and use it instead.
801 int pci_reenable_device(struct pci_dev
*dev
)
803 if (atomic_read(&dev
->enable_cnt
))
804 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
808 static int __pci_enable_device_flags(struct pci_dev
*dev
,
809 resource_size_t flags
)
814 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
815 return 0; /* already enabled */
817 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
818 if (dev
->resource
[i
].flags
& flags
)
821 err
= do_pci_enable_device(dev
, bars
);
823 atomic_dec(&dev
->enable_cnt
);
828 * pci_enable_device_io - Initialize a device for use with IO space
829 * @dev: PCI device to be initialized
831 * Initialize device before it's used by a driver. Ask low-level code
832 * to enable I/O resources. Wake up the device if it was suspended.
833 * Beware, this function can fail.
835 int pci_enable_device_io(struct pci_dev
*dev
)
837 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
841 * pci_enable_device_mem - Initialize a device for use with Memory space
842 * @dev: PCI device to be initialized
844 * Initialize device before it's used by a driver. Ask low-level code
845 * to enable Memory resources. Wake up the device if it was suspended.
846 * Beware, this function can fail.
848 int pci_enable_device_mem(struct pci_dev
*dev
)
850 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
854 * pci_enable_device - Initialize device before it's used by a driver.
855 * @dev: PCI device to be initialized
857 * Initialize device before it's used by a driver. Ask low-level code
858 * to enable I/O and memory. Wake up the device if it was suspended.
859 * Beware, this function can fail.
861 * Note we don't actually enable the device many times if we call
862 * this function repeatedly (we just increment the count).
864 int pci_enable_device(struct pci_dev
*dev
)
866 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
870 * Managed PCI resources. This manages device on/off, intx/msi/msix
871 * on/off and BAR regions. pci_dev itself records msi/msix status, so
872 * there's no need to track it separately. pci_devres is initialized
873 * when a device is enabled using managed PCI device enable interface.
876 unsigned int enabled
:1;
877 unsigned int pinned
:1;
878 unsigned int orig_intx
:1;
879 unsigned int restore_intx
:1;
883 static void pcim_release(struct device
*gendev
, void *res
)
885 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
886 struct pci_devres
*this = res
;
889 if (dev
->msi_enabled
)
890 pci_disable_msi(dev
);
891 if (dev
->msix_enabled
)
892 pci_disable_msix(dev
);
894 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
895 if (this->region_mask
& (1 << i
))
896 pci_release_region(dev
, i
);
898 if (this->restore_intx
)
899 pci_intx(dev
, this->orig_intx
);
901 if (this->enabled
&& !this->pinned
)
902 pci_disable_device(dev
);
905 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
907 struct pci_devres
*dr
, *new_dr
;
909 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
913 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
916 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
919 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
921 if (pci_is_managed(pdev
))
922 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
927 * pcim_enable_device - Managed pci_enable_device()
928 * @pdev: PCI device to be initialized
930 * Managed pci_enable_device().
932 int pcim_enable_device(struct pci_dev
*pdev
)
934 struct pci_devres
*dr
;
937 dr
= get_pci_dr(pdev
);
943 rc
= pci_enable_device(pdev
);
945 pdev
->is_managed
= 1;
952 * pcim_pin_device - Pin managed PCI device
953 * @pdev: PCI device to pin
955 * Pin managed PCI device @pdev. Pinned device won't be disabled on
956 * driver detach. @pdev must have been enabled with
957 * pcim_enable_device().
959 void pcim_pin_device(struct pci_dev
*pdev
)
961 struct pci_devres
*dr
;
963 dr
= find_pci_dr(pdev
);
964 WARN_ON(!dr
|| !dr
->enabled
);
970 * pcibios_disable_device - disable arch specific PCI resources for device dev
971 * @dev: the PCI device to disable
973 * Disables architecture specific PCI resources for the device. This
974 * is the default implementation. Architecture implementations can
977 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
979 static void do_pci_disable_device(struct pci_dev
*dev
)
983 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
984 if (pci_command
& PCI_COMMAND_MASTER
) {
985 pci_command
&= ~PCI_COMMAND_MASTER
;
986 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
989 pcibios_disable_device(dev
);
993 * pci_disable_enabled_device - Disable device without updating enable_cnt
994 * @dev: PCI device to disable
996 * NOTE: This function is a backend of PCI power management routines and is
997 * not supposed to be called drivers.
999 void pci_disable_enabled_device(struct pci_dev
*dev
)
1001 if (atomic_read(&dev
->enable_cnt
))
1002 do_pci_disable_device(dev
);
1006 * pci_disable_device - Disable PCI device after use
1007 * @dev: PCI device to be disabled
1009 * Signal to the system that the PCI device is not in use by the system
1010 * anymore. This only involves disabling PCI bus-mastering, if active.
1012 * Note we don't actually disable the device until all callers of
1013 * pci_device_enable() have called pci_device_disable().
1016 pci_disable_device(struct pci_dev
*dev
)
1018 struct pci_devres
*dr
;
1020 dr
= find_pci_dr(dev
);
1024 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1027 do_pci_disable_device(dev
);
1029 dev
->is_busmaster
= 0;
1033 * pcibios_set_pcie_reset_state - set reset state for device dev
1034 * @dev: the PCI-E device reset
1035 * @state: Reset state to enter into
1038 * Sets the PCI-E reset state for the device. This is the default
1039 * implementation. Architecture implementations can override this.
1041 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1042 enum pcie_reset_state state
)
1048 * pci_set_pcie_reset_state - set reset state for device dev
1049 * @dev: the PCI-E device reset
1050 * @state: Reset state to enter into
1053 * Sets the PCI reset state for the device.
1055 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1057 return pcibios_set_pcie_reset_state(dev
, state
);
1061 * pci_pme_capable - check the capability of PCI device to generate PME#
1062 * @dev: PCI device to handle.
1063 * @state: PCI state from which device will issue PME#.
1065 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1070 return !!(dev
->pme_support
& (1 << state
));
1074 * pci_pme_active - enable or disable PCI device's PME# function
1075 * @dev: PCI device to handle.
1076 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1078 * The caller must verify that the device is capable of generating PME# before
1079 * calling this function with @enable equal to 'true'.
1081 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1088 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1089 /* Clear PME_Status by writing 1 to it and enable PME# */
1090 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1092 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1094 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1096 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1097 enable
? "enabled" : "disabled");
1101 * pci_enable_wake - enable PCI device as wakeup event source
1102 * @dev: PCI device affected
1103 * @state: PCI state from which device will issue wakeup events
1104 * @enable: True to enable event generation; false to disable
1106 * This enables the device as a wakeup event source, or disables it.
1107 * When such events involves platform-specific hooks, those hooks are
1108 * called automatically by this routine.
1110 * Devices with legacy power management (no standard PCI PM capabilities)
1111 * always require such platform hooks.
1114 * 0 is returned on success
1115 * -EINVAL is returned if device is not supposed to wake up the system
1116 * Error code depending on the platform is returned if both the platform and
1117 * the native mechanism fail to enable the generation of wake-up events
1119 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1122 bool pme_done
= false;
1124 if (enable
&& !device_may_wakeup(&dev
->dev
))
1128 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1129 * Anderson we should be doing PME# wake enable followed by ACPI wake
1130 * enable. To disable wake-up we call the platform first, for symmetry.
1133 if (!enable
&& platform_pci_can_wakeup(dev
))
1134 error
= platform_pci_sleep_wake(dev
, false);
1136 if (!enable
|| pci_pme_capable(dev
, state
)) {
1137 pci_pme_active(dev
, enable
);
1141 if (enable
&& platform_pci_can_wakeup(dev
))
1142 error
= platform_pci_sleep_wake(dev
, true);
1144 return pme_done
? 0 : error
;
1148 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1149 * @dev: PCI device to prepare
1150 * @enable: True to enable wake-up event generation; false to disable
1152 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1153 * and this function allows them to set that up cleanly - pci_enable_wake()
1154 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1155 * ordering constraints.
1157 * This function only returns error code if the device is not capable of
1158 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1159 * enable wake-up power for it.
1161 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1163 return pci_pme_capable(dev
, PCI_D3cold
) ?
1164 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1165 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1169 * pci_target_state - find an appropriate low power state for a given PCI dev
1172 * Use underlying platform code to find a supported low power state for @dev.
1173 * If the platform can't manage @dev, return the deepest state from which it
1174 * can generate wake events, based on any available PME info.
1176 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1178 pci_power_t target_state
= PCI_D3hot
;
1180 if (platform_pci_power_manageable(dev
)) {
1182 * Call the platform to choose the target state of the device
1183 * and enable wake-up from this state if supported.
1185 pci_power_t state
= platform_pci_choose_state(dev
);
1188 case PCI_POWER_ERROR
:
1193 if (pci_no_d1d2(dev
))
1196 target_state
= state
;
1198 } else if (device_may_wakeup(&dev
->dev
)) {
1200 * Find the deepest state from which the device can generate
1201 * wake-up events, make it the target state and enable device
1205 return PCI_POWER_ERROR
;
1207 if (dev
->pme_support
) {
1209 && !(dev
->pme_support
& (1 << target_state
)))
1214 return target_state
;
1218 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1219 * @dev: Device to handle.
1221 * Choose the power state appropriate for the device depending on whether
1222 * it can wake up the system and/or is power manageable by the platform
1223 * (PCI_D3hot is the default) and put the device into that state.
1225 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1227 pci_power_t target_state
= pci_target_state(dev
);
1230 if (target_state
== PCI_POWER_ERROR
)
1233 pci_enable_wake(dev
, target_state
, true);
1235 error
= pci_set_power_state(dev
, target_state
);
1238 pci_enable_wake(dev
, target_state
, false);
1244 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1245 * @dev: Device to handle.
1247 * Disable device's sytem wake-up capability and put it into D0.
1249 int pci_back_from_sleep(struct pci_dev
*dev
)
1251 pci_enable_wake(dev
, PCI_D0
, false);
1252 return pci_set_power_state(dev
, PCI_D0
);
1256 * pci_pm_init - Initialize PM functions of given PCI device
1257 * @dev: PCI device to handle.
1259 void pci_pm_init(struct pci_dev
*dev
)
1266 /* find PCI PM capability in list */
1267 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1270 /* Check device's ability to generate PME# */
1271 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1273 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1274 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1275 pmc
& PCI_PM_CAP_VER_MASK
);
1281 dev
->d1_support
= false;
1282 dev
->d2_support
= false;
1283 if (!pci_no_d1d2(dev
)) {
1284 if (pmc
& PCI_PM_CAP_D1
)
1285 dev
->d1_support
= true;
1286 if (pmc
& PCI_PM_CAP_D2
)
1287 dev
->d2_support
= true;
1289 if (dev
->d1_support
|| dev
->d2_support
)
1290 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1291 dev
->d1_support
? " D1" : "",
1292 dev
->d2_support
? " D2" : "");
1295 pmc
&= PCI_PM_CAP_PME_MASK
;
1297 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1298 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1299 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1300 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1301 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1302 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1303 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1305 * Make device's PM flags reflect the wake-up capability, but
1306 * let the user space enable it to wake up the system as needed.
1308 device_set_wakeup_capable(&dev
->dev
, true);
1309 device_set_wakeup_enable(&dev
->dev
, false);
1310 /* Disable the PME# generation functionality */
1311 pci_pme_active(dev
, false);
1313 dev
->pme_support
= 0;
1318 * platform_pci_wakeup_init - init platform wakeup if present
1321 * Some devices don't have PCI PM caps but can still generate wakeup
1322 * events through platform methods (like ACPI events). If @dev supports
1323 * platform wakeup events, set the device flag to indicate as much. This
1324 * may be redundant if the device also supports PCI PM caps, but double
1325 * initialization should be safe in that case.
1327 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1329 if (!platform_pci_can_wakeup(dev
))
1332 device_set_wakeup_capable(&dev
->dev
, true);
1333 device_set_wakeup_enable(&dev
->dev
, false);
1334 platform_pci_sleep_wake(dev
, false);
1338 * pci_add_save_buffer - allocate buffer for saving given capability registers
1339 * @dev: the PCI device
1340 * @cap: the capability to allocate the buffer for
1341 * @size: requested size of the buffer
1343 static int pci_add_cap_save_buffer(
1344 struct pci_dev
*dev
, char cap
, unsigned int size
)
1347 struct pci_cap_saved_state
*save_state
;
1349 pos
= pci_find_capability(dev
, cap
);
1353 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1357 save_state
->cap_nr
= cap
;
1358 pci_add_saved_cap(dev
, save_state
);
1364 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1365 * @dev: the PCI device
1367 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1371 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
, 4 * sizeof(u16
));
1374 "unable to preallocate PCI Express save buffer\n");
1376 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1379 "unable to preallocate PCI-X save buffer\n");
1383 * pci_enable_ari - enable ARI forwarding if hardware support it
1384 * @dev: the PCI device
1386 void pci_enable_ari(struct pci_dev
*dev
)
1391 struct pci_dev
*bridge
;
1393 if (!dev
->is_pcie
|| dev
->devfn
)
1396 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1400 bridge
= dev
->bus
->self
;
1401 if (!bridge
|| !bridge
->is_pcie
)
1404 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1408 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1409 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1412 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1413 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1414 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1416 bridge
->ari_enabled
= 1;
1420 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1421 * @dev: the PCI device
1422 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1424 * Perform INTx swizzling for a device behind one level of bridge. This is
1425 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1426 * behind bridges on add-in cards.
1428 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1430 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1434 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1442 while (dev
->bus
->self
) {
1443 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1444 dev
= dev
->bus
->self
;
1451 * pci_common_swizzle - swizzle INTx all the way to root bridge
1452 * @dev: the PCI device
1453 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1455 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1456 * bridges all the way up to a PCI root bus.
1458 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1462 while (dev
->bus
->self
) {
1463 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1464 dev
= dev
->bus
->self
;
1467 return PCI_SLOT(dev
->devfn
);
1471 * pci_release_region - Release a PCI bar
1472 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1473 * @bar: BAR to release
1475 * Releases the PCI I/O and memory resources previously reserved by a
1476 * successful call to pci_request_region. Call this function only
1477 * after all use of the PCI regions has ceased.
1479 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1481 struct pci_devres
*dr
;
1483 if (pci_resource_len(pdev
, bar
) == 0)
1485 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1486 release_region(pci_resource_start(pdev
, bar
),
1487 pci_resource_len(pdev
, bar
));
1488 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1489 release_mem_region(pci_resource_start(pdev
, bar
),
1490 pci_resource_len(pdev
, bar
));
1492 dr
= find_pci_dr(pdev
);
1494 dr
->region_mask
&= ~(1 << bar
);
1498 * __pci_request_region - Reserved PCI I/O and memory resource
1499 * @pdev: PCI device whose resources are to be reserved
1500 * @bar: BAR to be reserved
1501 * @res_name: Name to be associated with resource.
1502 * @exclusive: whether the region access is exclusive or not
1504 * Mark the PCI region associated with PCI device @pdev BR @bar as
1505 * being reserved by owner @res_name. Do not access any
1506 * address inside the PCI regions unless this call returns
1509 * If @exclusive is set, then the region is marked so that userspace
1510 * is explicitly not allowed to map the resource via /dev/mem or
1511 * sysfs MMIO access.
1513 * Returns 0 on success, or %EBUSY on error. A warning
1514 * message is also printed on failure.
1516 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1519 struct pci_devres
*dr
;
1521 if (pci_resource_len(pdev
, bar
) == 0)
1524 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1525 if (!request_region(pci_resource_start(pdev
, bar
),
1526 pci_resource_len(pdev
, bar
), res_name
))
1529 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1530 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1531 pci_resource_len(pdev
, bar
), res_name
,
1536 dr
= find_pci_dr(pdev
);
1538 dr
->region_mask
|= 1 << bar
;
1543 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1545 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1546 &pdev
->resource
[bar
]);
1551 * pci_request_region - Reserve PCI I/O and memory resource
1552 * @pdev: PCI device whose resources are to be reserved
1553 * @bar: BAR to be reserved
1554 * @res_name: Name to be associated with resource
1556 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1557 * being reserved by owner @res_name. Do not access any
1558 * address inside the PCI regions unless this call returns
1561 * Returns 0 on success, or %EBUSY on error. A warning
1562 * message is also printed on failure.
1564 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1566 return __pci_request_region(pdev
, bar
, res_name
, 0);
1570 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1571 * @pdev: PCI device whose resources are to be reserved
1572 * @bar: BAR to be reserved
1573 * @res_name: Name to be associated with resource.
1575 * Mark the PCI region associated with PCI device @pdev BR @bar as
1576 * being reserved by owner @res_name. Do not access any
1577 * address inside the PCI regions unless this call returns
1580 * Returns 0 on success, or %EBUSY on error. A warning
1581 * message is also printed on failure.
1583 * The key difference that _exclusive makes it that userspace is
1584 * explicitly not allowed to map the resource via /dev/mem or
1587 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1589 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1592 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1593 * @pdev: PCI device whose resources were previously reserved
1594 * @bars: Bitmask of BARs to be released
1596 * Release selected PCI I/O and memory resources previously reserved.
1597 * Call this function only after all use of the PCI regions has ceased.
1599 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1603 for (i
= 0; i
< 6; i
++)
1604 if (bars
& (1 << i
))
1605 pci_release_region(pdev
, i
);
1608 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1609 const char *res_name
, int excl
)
1613 for (i
= 0; i
< 6; i
++)
1614 if (bars
& (1 << i
))
1615 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1621 if (bars
& (1 << i
))
1622 pci_release_region(pdev
, i
);
1629 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1630 * @pdev: PCI device whose resources are to be reserved
1631 * @bars: Bitmask of BARs to be requested
1632 * @res_name: Name to be associated with resource
1634 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1635 const char *res_name
)
1637 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1640 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1641 int bars
, const char *res_name
)
1643 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1644 IORESOURCE_EXCLUSIVE
);
1648 * pci_release_regions - Release reserved PCI I/O and memory resources
1649 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1651 * Releases all PCI I/O and memory resources previously reserved by a
1652 * successful call to pci_request_regions. Call this function only
1653 * after all use of the PCI regions has ceased.
1656 void pci_release_regions(struct pci_dev
*pdev
)
1658 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1662 * pci_request_regions - Reserved PCI I/O and memory resources
1663 * @pdev: PCI device whose resources are to be reserved
1664 * @res_name: Name to be associated with resource.
1666 * Mark all PCI regions associated with PCI device @pdev as
1667 * being reserved by owner @res_name. Do not access any
1668 * address inside the PCI regions unless this call returns
1671 * Returns 0 on success, or %EBUSY on error. A warning
1672 * message is also printed on failure.
1674 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1676 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1680 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1681 * @pdev: PCI device whose resources are to be reserved
1682 * @res_name: Name to be associated with resource.
1684 * Mark all PCI regions associated with PCI device @pdev as
1685 * being reserved by owner @res_name. Do not access any
1686 * address inside the PCI regions unless this call returns
1689 * pci_request_regions_exclusive() will mark the region so that
1690 * /dev/mem and the sysfs MMIO access will not be allowed.
1692 * Returns 0 on success, or %EBUSY on error. A warning
1693 * message is also printed on failure.
1695 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1697 return pci_request_selected_regions_exclusive(pdev
,
1698 ((1 << 6) - 1), res_name
);
1701 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1705 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1707 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1709 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1710 if (cmd
!= old_cmd
) {
1711 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1712 enable
? "enabling" : "disabling");
1713 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1715 dev
->is_busmaster
= enable
;
1719 * pci_set_master - enables bus-mastering for device dev
1720 * @dev: the PCI device to enable
1722 * Enables bus-mastering on the device and calls pcibios_set_master()
1723 * to do the needed arch specific settings.
1725 void pci_set_master(struct pci_dev
*dev
)
1727 __pci_set_master(dev
, true);
1728 pcibios_set_master(dev
);
1732 * pci_clear_master - disables bus-mastering for device dev
1733 * @dev: the PCI device to disable
1735 void pci_clear_master(struct pci_dev
*dev
)
1737 __pci_set_master(dev
, false);
1740 #ifdef PCI_DISABLE_MWI
1741 int pci_set_mwi(struct pci_dev
*dev
)
1746 int pci_try_set_mwi(struct pci_dev
*dev
)
1751 void pci_clear_mwi(struct pci_dev
*dev
)
1757 #ifndef PCI_CACHE_LINE_BYTES
1758 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1761 /* This can be overridden by arch code. */
1762 /* Don't forget this is measured in 32-bit words, not bytes */
1763 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1766 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1767 * @dev: the PCI device for which MWI is to be enabled
1769 * Helper function for pci_set_mwi.
1770 * Originally copied from drivers/net/acenic.c.
1771 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1773 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1776 pci_set_cacheline_size(struct pci_dev
*dev
)
1780 if (!pci_cache_line_size
)
1781 return -EINVAL
; /* The system doesn't support MWI. */
1783 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1784 equal to or multiple of the right value. */
1785 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1786 if (cacheline_size
>= pci_cache_line_size
&&
1787 (cacheline_size
% pci_cache_line_size
) == 0)
1790 /* Write the correct value. */
1791 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1793 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1794 if (cacheline_size
== pci_cache_line_size
)
1797 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1798 "supported\n", pci_cache_line_size
<< 2);
1804 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1805 * @dev: the PCI device for which MWI is enabled
1807 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1809 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1812 pci_set_mwi(struct pci_dev
*dev
)
1817 rc
= pci_set_cacheline_size(dev
);
1821 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1822 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1823 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1824 cmd
|= PCI_COMMAND_INVALIDATE
;
1825 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1832 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1833 * @dev: the PCI device for which MWI is enabled
1835 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1836 * Callers are not required to check the return value.
1838 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1840 int pci_try_set_mwi(struct pci_dev
*dev
)
1842 int rc
= pci_set_mwi(dev
);
1847 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1848 * @dev: the PCI device to disable
1850 * Disables PCI Memory-Write-Invalidate transaction on the device
1853 pci_clear_mwi(struct pci_dev
*dev
)
1857 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1858 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1859 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1860 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1863 #endif /* ! PCI_DISABLE_MWI */
1866 * pci_intx - enables/disables PCI INTx for device dev
1867 * @pdev: the PCI device to operate on
1868 * @enable: boolean: whether to enable or disable PCI INTx
1870 * Enables/disables PCI INTx for device dev
1873 pci_intx(struct pci_dev
*pdev
, int enable
)
1875 u16 pci_command
, new;
1877 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1880 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1882 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1885 if (new != pci_command
) {
1886 struct pci_devres
*dr
;
1888 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1890 dr
= find_pci_dr(pdev
);
1891 if (dr
&& !dr
->restore_intx
) {
1892 dr
->restore_intx
= 1;
1893 dr
->orig_intx
= !enable
;
1899 * pci_msi_off - disables any msi or msix capabilities
1900 * @dev: the PCI device to operate on
1902 * If you want to use msi see pci_enable_msi and friends.
1903 * This is a lower level primitive that allows us to disable
1904 * msi operation at the device level.
1906 void pci_msi_off(struct pci_dev
*dev
)
1911 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1913 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1914 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1915 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1917 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1919 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1920 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1921 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1925 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1927 * These can be overridden by arch-specific implementations
1930 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1932 if (!pci_dma_supported(dev
, mask
))
1935 dev
->dma_mask
= mask
;
1941 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1943 if (!pci_dma_supported(dev
, mask
))
1946 dev
->dev
.coherent_dma_mask
= mask
;
1952 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1953 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1955 return dma_set_max_seg_size(&dev
->dev
, size
);
1957 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1960 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1961 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1963 return dma_set_seg_boundary(&dev
->dev
, mask
);
1965 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1968 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
1972 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1976 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
1977 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
1983 pci_block_user_cfg_access(dev
);
1985 /* Wait for Transaction Pending bit clean */
1987 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1988 if (status
& PCI_EXP_DEVSTA_TRPND
) {
1989 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
1990 "sleeping for 1 second\n");
1992 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1993 if (status
& PCI_EXP_DEVSTA_TRPND
)
1994 dev_info(&dev
->dev
, "Still busy after 1s; "
1995 "proceeding with reset anyway\n");
1998 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
1999 PCI_EXP_DEVCTL_BCR_FLR
);
2002 pci_unblock_user_cfg_access(dev
);
2006 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
2008 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2014 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
2015 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2021 pci_block_user_cfg_access(dev
);
2023 /* Wait for Transaction Pending bit clean */
2025 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2026 if (status
& PCI_AF_STATUS_TP
) {
2027 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
2028 " reset; sleeping for 1 second\n");
2030 pci_read_config_byte(dev
,
2031 cappos
+ PCI_AF_STATUS
, &status
);
2032 if (status
& PCI_AF_STATUS_TP
)
2033 dev_info(&dev
->dev
, "Still busy after 1s; "
2034 "proceeding with reset anyway\n");
2036 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2039 pci_unblock_user_cfg_access(dev
);
2043 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
2047 res
= __pcie_flr(pdev
, probe
);
2051 res
= __pci_af_flr(pdev
, probe
);
2059 * pci_execute_reset_function() - Reset a PCI device function
2060 * @dev: Device function to reset
2062 * Some devices allow an individual function to be reset without affecting
2063 * other functions in the same device. The PCI device must be responsive
2064 * to PCI config space in order to use this function.
2066 * The device function is presumed to be unused when this function is called.
2067 * Resetting the device will make the contents of PCI configuration space
2068 * random, so any caller of this must be prepared to reinitialise the
2069 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2072 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2073 * device doesn't support resetting a single function.
2075 int pci_execute_reset_function(struct pci_dev
*dev
)
2077 return __pci_reset_function(dev
, 0);
2079 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
2082 * pci_reset_function() - quiesce and reset a PCI device function
2083 * @dev: Device function to reset
2085 * Some devices allow an individual function to be reset without affecting
2086 * other functions in the same device. The PCI device must be responsive
2087 * to PCI config space in order to use this function.
2089 * This function does not just reset the PCI portion of a device, but
2090 * clears all the state associated with the device. This function differs
2091 * from pci_execute_reset_function in that it saves and restores device state
2094 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2095 * device doesn't support resetting a single function.
2097 int pci_reset_function(struct pci_dev
*dev
)
2099 int r
= __pci_reset_function(dev
, 1);
2104 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2105 disable_irq(dev
->irq
);
2106 pci_save_state(dev
);
2108 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2110 r
= pci_execute_reset_function(dev
);
2112 pci_restore_state(dev
);
2113 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2114 enable_irq(dev
->irq
);
2118 EXPORT_SYMBOL_GPL(pci_reset_function
);
2121 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2122 * @dev: PCI device to query
2124 * Returns mmrbc: maximum designed memory read count in bytes
2125 * or appropriate error value.
2127 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2132 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2136 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2140 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2142 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2145 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2146 * @dev: PCI device to query
2148 * Returns mmrbc: maximum memory read count in bytes
2149 * or appropriate error value.
2151 int pcix_get_mmrbc(struct pci_dev
*dev
)
2156 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2160 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2162 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2166 EXPORT_SYMBOL(pcix_get_mmrbc
);
2169 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2170 * @dev: PCI device to query
2171 * @mmrbc: maximum memory read count in bytes
2172 * valid values are 512, 1024, 2048, 4096
2174 * If possible sets maximum memory read byte count, some bridges have erratas
2175 * that prevent this.
2177 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2179 int cap
, err
= -EINVAL
;
2180 u32 stat
, cmd
, v
, o
;
2182 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2185 v
= ffs(mmrbc
) - 10;
2187 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2191 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2195 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2198 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2202 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2204 if (v
> o
&& dev
->bus
&&
2205 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2208 cmd
&= ~PCI_X_CMD_MAX_READ
;
2210 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2215 EXPORT_SYMBOL(pcix_set_mmrbc
);
2218 * pcie_get_readrq - get PCI Express read request size
2219 * @dev: PCI device to query
2221 * Returns maximum memory read request in bytes
2222 * or appropriate error value.
2224 int pcie_get_readrq(struct pci_dev
*dev
)
2229 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2233 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2235 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2239 EXPORT_SYMBOL(pcie_get_readrq
);
2242 * pcie_set_readrq - set PCI Express maximum memory read request
2243 * @dev: PCI device to query
2244 * @rq: maximum memory read count in bytes
2245 * valid values are 128, 256, 512, 1024, 2048, 4096
2247 * If possible sets maximum read byte count
2249 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2251 int cap
, err
= -EINVAL
;
2254 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2257 v
= (ffs(rq
) - 8) << 12;
2259 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2263 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2267 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2268 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2270 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2276 EXPORT_SYMBOL(pcie_set_readrq
);
2279 * pci_select_bars - Make BAR mask from the type of resource
2280 * @dev: the PCI device for which BAR mask is made
2281 * @flags: resource type mask to be selected
2283 * This helper routine makes bar mask from the type of resource.
2285 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2288 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2289 if (pci_resource_flags(dev
, i
) & flags
)
2295 * pci_resource_bar - get position of the BAR associated with a resource
2296 * @dev: the PCI device
2297 * @resno: the resource number
2298 * @type: the BAR type to be filled in
2300 * Returns BAR position in config space, or 0 if the BAR is invalid.
2302 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2304 if (resno
< PCI_ROM_RESOURCE
) {
2305 *type
= pci_bar_unknown
;
2306 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2307 } else if (resno
== PCI_ROM_RESOURCE
) {
2308 *type
= pci_bar_mem32
;
2309 return dev
->rom_base_reg
;
2312 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2316 static void __devinit
pci_no_domains(void)
2318 #ifdef CONFIG_PCI_DOMAINS
2319 pci_domains_supported
= 0;
2324 * pci_ext_cfg_enabled - can we access extended PCI config space?
2325 * @dev: The PCI device of the root bridge.
2327 * Returns 1 if we can access PCI extended config space (offsets
2328 * greater than 0xff). This is the default implementation. Architecture
2329 * implementations can override this.
2331 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2336 static int __devinit
pci_init(void)
2338 struct pci_dev
*dev
= NULL
;
2340 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2341 pci_fixup_device(pci_fixup_final
, dev
);
2347 static int __init
pci_setup(char *str
)
2350 char *k
= strchr(str
, ',');
2353 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2354 if (!strcmp(str
, "nomsi")) {
2356 } else if (!strcmp(str
, "noaer")) {
2358 } else if (!strcmp(str
, "nodomains")) {
2360 } else if (!strncmp(str
, "cbiosize=", 9)) {
2361 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2362 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2363 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2365 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2373 early_param("pci", pci_setup
);
2375 device_initcall(pci_init
);
2377 EXPORT_SYMBOL(pci_reenable_device
);
2378 EXPORT_SYMBOL(pci_enable_device_io
);
2379 EXPORT_SYMBOL(pci_enable_device_mem
);
2380 EXPORT_SYMBOL(pci_enable_device
);
2381 EXPORT_SYMBOL(pcim_enable_device
);
2382 EXPORT_SYMBOL(pcim_pin_device
);
2383 EXPORT_SYMBOL(pci_disable_device
);
2384 EXPORT_SYMBOL(pci_find_capability
);
2385 EXPORT_SYMBOL(pci_bus_find_capability
);
2386 EXPORT_SYMBOL(pci_release_regions
);
2387 EXPORT_SYMBOL(pci_request_regions
);
2388 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2389 EXPORT_SYMBOL(pci_release_region
);
2390 EXPORT_SYMBOL(pci_request_region
);
2391 EXPORT_SYMBOL(pci_request_region_exclusive
);
2392 EXPORT_SYMBOL(pci_release_selected_regions
);
2393 EXPORT_SYMBOL(pci_request_selected_regions
);
2394 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2395 EXPORT_SYMBOL(pci_set_master
);
2396 EXPORT_SYMBOL(pci_clear_master
);
2397 EXPORT_SYMBOL(pci_set_mwi
);
2398 EXPORT_SYMBOL(pci_try_set_mwi
);
2399 EXPORT_SYMBOL(pci_clear_mwi
);
2400 EXPORT_SYMBOL_GPL(pci_intx
);
2401 EXPORT_SYMBOL(pci_set_dma_mask
);
2402 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2403 EXPORT_SYMBOL(pci_assign_resource
);
2404 EXPORT_SYMBOL(pci_find_parent_resource
);
2405 EXPORT_SYMBOL(pci_select_bars
);
2407 EXPORT_SYMBOL(pci_set_power_state
);
2408 EXPORT_SYMBOL(pci_save_state
);
2409 EXPORT_SYMBOL(pci_restore_state
);
2410 EXPORT_SYMBOL(pci_pme_capable
);
2411 EXPORT_SYMBOL(pci_pme_active
);
2412 EXPORT_SYMBOL(pci_enable_wake
);
2413 EXPORT_SYMBOL(pci_wake_from_d3
);
2414 EXPORT_SYMBOL(pci_target_state
);
2415 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2416 EXPORT_SYMBOL(pci_back_from_sleep
);
2417 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);