2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
29 #ifdef CONFIG_PCI_DOMAINS
30 int pci_domains_supported
= 1;
33 #define DEFAULT_CARDBUS_IO_SIZE (256)
34 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
35 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
36 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
37 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
40 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
41 * @bus: pointer to PCI bus structure to search
43 * Given a PCI bus, returns the highest PCI bus number present in the set
44 * including the given PCI bus and its list of child PCI buses.
46 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
48 struct list_head
*tmp
;
51 max
= bus
->subordinate
;
52 list_for_each(tmp
, &bus
->children
) {
53 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
59 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
61 #ifdef CONFIG_HAS_IOMEM
62 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
65 * Make sure the BAR is actually a memory resource, not an IO resource
67 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
71 return ioremap_nocache(pci_resource_start(pdev
, bar
),
72 pci_resource_len(pdev
, bar
));
74 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
79 * pci_max_busnr - returns maximum PCI bus number
81 * Returns the highest PCI bus number present in the system global list of
84 unsigned char __devinit
87 struct pci_bus
*bus
= NULL
;
91 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
92 n
= pci_bus_max_busnr(bus
);
101 #define PCI_FIND_CAP_TTL 48
103 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
104 u8 pos
, int cap
, int *ttl
)
109 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
113 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
119 pos
+= PCI_CAP_LIST_NEXT
;
124 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
127 int ttl
= PCI_FIND_CAP_TTL
;
129 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
132 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
134 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
135 pos
+ PCI_CAP_LIST_NEXT
, cap
);
137 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
139 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
140 unsigned int devfn
, u8 hdr_type
)
144 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
145 if (!(status
& PCI_STATUS_CAP_LIST
))
149 case PCI_HEADER_TYPE_NORMAL
:
150 case PCI_HEADER_TYPE_BRIDGE
:
151 return PCI_CAPABILITY_LIST
;
152 case PCI_HEADER_TYPE_CARDBUS
:
153 return PCI_CB_CAPABILITY_LIST
;
162 * pci_find_capability - query for devices' capabilities
163 * @dev: PCI device to query
164 * @cap: capability code
166 * Tell if a device supports a given PCI capability.
167 * Returns the address of the requested capability structure within the
168 * device's PCI configuration space or 0 in case the device does not
169 * support it. Possible values for @cap:
171 * %PCI_CAP_ID_PM Power Management
172 * %PCI_CAP_ID_AGP Accelerated Graphics Port
173 * %PCI_CAP_ID_VPD Vital Product Data
174 * %PCI_CAP_ID_SLOTID Slot Identification
175 * %PCI_CAP_ID_MSI Message Signalled Interrupts
176 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
177 * %PCI_CAP_ID_PCIX PCI-X
178 * %PCI_CAP_ID_EXP PCI Express
180 int pci_find_capability(struct pci_dev
*dev
, int cap
)
184 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
186 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
192 * pci_bus_find_capability - query for devices' capabilities
193 * @bus: the PCI bus to query
194 * @devfn: PCI device to query
195 * @cap: capability code
197 * Like pci_find_capability() but works for pci devices that do not have a
198 * pci_dev structure set up yet.
200 * Returns the address of the requested capability structure within the
201 * device's PCI configuration space or 0 in case the device does not
204 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
209 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
211 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
213 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
219 * pci_find_ext_capability - Find an extended capability
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Returns the address of the requested extended capability structure
224 * within the device's PCI configuration space or 0 if the device does
225 * not support it. Possible values for @cap:
227 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
228 * %PCI_EXT_CAP_ID_VC Virtual Channel
229 * %PCI_EXT_CAP_ID_DSN Device Serial Number
230 * %PCI_EXT_CAP_ID_PWR Power Budgeting
232 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
236 int pos
= PCI_CFG_SPACE_SIZE
;
238 /* minimum 8 bytes per capability */
239 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
241 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
244 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
248 * If we have no capabilities, this is indicated by cap ID,
249 * cap version and next pointer all being 0.
255 if (PCI_EXT_CAP_ID(header
) == cap
)
258 pos
= PCI_EXT_CAP_NEXT(header
);
259 if (pos
< PCI_CFG_SPACE_SIZE
)
262 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
268 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
270 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
272 int rc
, ttl
= PCI_FIND_CAP_TTL
;
275 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
276 mask
= HT_3BIT_CAP_MASK
;
278 mask
= HT_5BIT_CAP_MASK
;
280 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
281 PCI_CAP_ID_HT
, &ttl
);
283 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
284 if (rc
!= PCIBIOS_SUCCESSFUL
)
287 if ((cap
& mask
) == ht_cap
)
290 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
291 pos
+ PCI_CAP_LIST_NEXT
,
292 PCI_CAP_ID_HT
, &ttl
);
298 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
299 * @dev: PCI device to query
300 * @pos: Position from which to continue searching
301 * @ht_cap: Hypertransport capability code
303 * To be used in conjunction with pci_find_ht_capability() to search for
304 * all capabilities matching @ht_cap. @pos should always be a value returned
305 * from pci_find_ht_capability().
307 * NB. To be 100% safe against broken PCI devices, the caller should take
308 * steps to avoid an infinite loop.
310 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
312 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
314 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
317 * pci_find_ht_capability - query a device's Hypertransport capabilities
318 * @dev: PCI device to query
319 * @ht_cap: Hypertransport capability code
321 * Tell if a device supports a given Hypertransport capability.
322 * Returns an address within the device's PCI configuration space
323 * or 0 in case the device does not support the request capability.
324 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
325 * which has a Hypertransport capability matching @ht_cap.
327 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
331 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
333 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
337 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
340 * pci_find_parent_resource - return resource region of parent bus of given region
341 * @dev: PCI device structure contains resources to be searched
342 * @res: child resource record for which parent is sought
344 * For given resource region of given device, return the resource
345 * region of parent bus the given region is contained in or where
346 * it should be allocated from.
349 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
351 const struct pci_bus
*bus
= dev
->bus
;
353 struct resource
*best
= NULL
;
355 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
356 struct resource
*r
= bus
->resource
[i
];
359 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
360 continue; /* Not contained */
361 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
362 continue; /* Wrong type */
363 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
364 return r
; /* Exact match */
365 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
366 best
= r
; /* Approximating prefetchable by non-prefetchable */
372 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
373 * @dev: PCI device to have its BARs restored
375 * Restore the BAR values for a given device, so as to make it
376 * accessible by its driver.
379 pci_restore_bars(struct pci_dev
*dev
)
383 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
384 pci_update_resource(dev
, i
);
387 static struct pci_platform_pm_ops
*pci_platform_pm
;
389 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
391 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
392 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
394 pci_platform_pm
= ops
;
398 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
400 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
403 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
406 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
409 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
411 return pci_platform_pm
?
412 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
415 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
417 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
420 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
422 return pci_platform_pm
?
423 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
427 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
429 * @dev: PCI device to handle.
430 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
431 * @wait: If 'true', wait for the device to change its power state
434 * -EINVAL if the requested state is invalid.
435 * -EIO if device does not support PCI PM or its PM capabilities register has a
436 * wrong version, or device doesn't support the requested state.
437 * 0 if device already is in the requested state.
438 * 0 if device's power state has been successfully changed.
441 pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
, bool wait
)
444 bool need_restore
= false;
449 if (state
< PCI_D0
|| state
> PCI_D3hot
)
452 /* Validate current state:
453 * Can enter D0 from any state, but if we can only go deeper
454 * to sleep if we're already in a low power state
456 if (dev
->current_state
== state
) {
457 /* we're already there */
459 } else if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
460 && dev
->current_state
> state
) {
461 dev_err(&dev
->dev
, "invalid power transition "
462 "(from state %d to %d)\n", dev
->current_state
, state
);
466 /* check if this device supports the desired state */
467 if ((state
== PCI_D1
&& !dev
->d1_support
)
468 || (state
== PCI_D2
&& !dev
->d2_support
))
471 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
473 /* If we're (effectively) in D3, force entire word to 0.
474 * This doesn't affect PME_Status, disables PME_En, and
475 * sets PowerState to 0.
477 switch (dev
->current_state
) {
481 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
484 case PCI_UNKNOWN
: /* Boot-up */
485 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
486 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
)) {
490 /* Fall-through: force to D0 */
496 /* enter specified state */
497 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
502 /* Mandatory power management transition delays */
503 /* see PCI PM 1.1 5.6.1 table 18 */
504 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
505 msleep(pci_pm_d3_delay
);
506 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
507 udelay(PCI_PM_D2_DELAY
);
509 dev
->current_state
= state
;
511 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
512 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
513 * from D3hot to D0 _may_ perform an internal reset, thereby
514 * going to "D0 Uninitialized" rather than "D0 Initialized".
515 * For example, at least some versions of the 3c905B and the
516 * 3c556B exhibit this behaviour.
518 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
519 * devices in a D3hot state at boot. Consequently, we need to
520 * restore at least the BARs so that the device will be
521 * accessible to its driver.
524 pci_restore_bars(dev
);
526 if (wait
&& dev
->bus
->self
)
527 pcie_aspm_pm_state_change(dev
->bus
->self
);
533 * pci_update_current_state - Read PCI power state of given device from its
534 * PCI PM registers and cache it
535 * @dev: PCI device to handle.
536 * @state: State to cache in case the device doesn't have the PM capability
538 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
543 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
544 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
546 dev
->current_state
= state
;
551 * pci_set_power_state - Set the power state of a PCI device
552 * @dev: PCI device to handle.
553 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
555 * Transition a device to a new power state, using the platform formware and/or
556 * the device's PCI PM registers.
559 * -EINVAL if the requested state is invalid.
560 * -EIO if device does not support PCI PM or its PM capabilities register has a
561 * wrong version, or device doesn't support the requested state.
562 * 0 if device already is in the requested state.
563 * 0 if device's power state has been successfully changed.
565 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
569 /* bound the state we're entering */
570 if (state
> PCI_D3hot
)
572 else if (state
< PCI_D0
)
574 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
576 * If the device or the parent bridge do not support PCI PM,
577 * ignore the request if we're doing anything other than putting
578 * it into D0 (which would only happen on boot).
582 if (state
== PCI_D0
&& platform_pci_power_manageable(dev
)) {
584 * Allow the platform to change the state, for example via ACPI
585 * _PR0, _PS0 and some such, but do not trust it.
587 int ret
= platform_pci_set_power_state(dev
, PCI_D0
);
589 pci_update_current_state(dev
, PCI_D0
);
591 /* This device is quirked not to be put into D3, so
592 don't put it in D3 */
593 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
596 error
= pci_raw_set_power_state(dev
, state
, true);
598 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
599 /* Allow the platform to finalize the transition */
600 int ret
= platform_pci_set_power_state(dev
, state
);
602 pci_update_current_state(dev
, state
);
611 * pci_choose_state - Choose the power state of a PCI device
612 * @dev: PCI device to be suspended
613 * @state: target sleep state for the whole system. This is the value
614 * that is passed to suspend() function.
616 * Returns PCI power state suitable for given device and given system
620 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
624 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
627 ret
= platform_pci_choose_state(dev
);
628 if (ret
!= PCI_POWER_ERROR
)
631 switch (state
.event
) {
634 case PM_EVENT_FREEZE
:
635 case PM_EVENT_PRETHAW
:
636 /* REVISIT both freeze and pre-thaw "should" use D0 */
637 case PM_EVENT_SUSPEND
:
638 case PM_EVENT_HIBERNATE
:
641 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
648 EXPORT_SYMBOL(pci_choose_state
);
650 static int pci_save_pcie_state(struct pci_dev
*dev
)
653 struct pci_cap_saved_state
*save_state
;
656 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
660 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
662 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
665 cap
= (u16
*)&save_state
->data
[0];
667 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
668 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
669 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
670 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
675 static void pci_restore_pcie_state(struct pci_dev
*dev
)
678 struct pci_cap_saved_state
*save_state
;
681 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
682 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
683 if (!save_state
|| pos
<= 0)
685 cap
= (u16
*)&save_state
->data
[0];
687 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
688 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
689 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
690 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
694 static int pci_save_pcix_state(struct pci_dev
*dev
)
697 struct pci_cap_saved_state
*save_state
;
699 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
703 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
705 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
709 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
714 static void pci_restore_pcix_state(struct pci_dev
*dev
)
717 struct pci_cap_saved_state
*save_state
;
720 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
721 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
722 if (!save_state
|| pos
<= 0)
724 cap
= (u16
*)&save_state
->data
[0];
726 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
731 * pci_save_state - save the PCI configuration space of a device before suspending
732 * @dev: - PCI device that we're dealing with
735 pci_save_state(struct pci_dev
*dev
)
738 /* XXX: 100% dword access ok here? */
739 for (i
= 0; i
< 16; i
++)
740 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
741 dev
->state_saved
= true;
742 if ((i
= pci_save_pcie_state(dev
)) != 0)
744 if ((i
= pci_save_pcix_state(dev
)) != 0)
750 * pci_restore_state - Restore the saved state of a PCI device
751 * @dev: - PCI device that we're dealing with
754 pci_restore_state(struct pci_dev
*dev
)
759 /* PCI Express register must be restored first */
760 pci_restore_pcie_state(dev
);
763 * The Base Address register should be programmed before the command
766 for (i
= 15; i
>= 0; i
--) {
767 pci_read_config_dword(dev
, i
* 4, &val
);
768 if (val
!= dev
->saved_config_space
[i
]) {
769 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
770 "space at offset %#x (was %#x, writing %#x)\n",
771 i
, val
, (int)dev
->saved_config_space
[i
]);
772 pci_write_config_dword(dev
,i
* 4,
773 dev
->saved_config_space
[i
]);
776 pci_restore_pcix_state(dev
);
777 pci_restore_msi_state(dev
);
782 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
786 err
= pci_set_power_state(dev
, PCI_D0
);
787 if (err
< 0 && err
!= -EIO
)
789 err
= pcibios_enable_device(dev
, bars
);
792 pci_fixup_device(pci_fixup_enable
, dev
);
798 * pci_reenable_device - Resume abandoned device
799 * @dev: PCI device to be resumed
801 * Note this function is a backend of pci_default_resume and is not supposed
802 * to be called by normal code, write proper resume handler and use it instead.
804 int pci_reenable_device(struct pci_dev
*dev
)
806 if (atomic_read(&dev
->enable_cnt
))
807 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
811 static int __pci_enable_device_flags(struct pci_dev
*dev
,
812 resource_size_t flags
)
817 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
818 return 0; /* already enabled */
820 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
821 if (dev
->resource
[i
].flags
& flags
)
824 err
= do_pci_enable_device(dev
, bars
);
826 atomic_dec(&dev
->enable_cnt
);
831 * pci_enable_device_io - Initialize a device for use with IO space
832 * @dev: PCI device to be initialized
834 * Initialize device before it's used by a driver. Ask low-level code
835 * to enable I/O resources. Wake up the device if it was suspended.
836 * Beware, this function can fail.
838 int pci_enable_device_io(struct pci_dev
*dev
)
840 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
844 * pci_enable_device_mem - Initialize a device for use with Memory space
845 * @dev: PCI device to be initialized
847 * Initialize device before it's used by a driver. Ask low-level code
848 * to enable Memory resources. Wake up the device if it was suspended.
849 * Beware, this function can fail.
851 int pci_enable_device_mem(struct pci_dev
*dev
)
853 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
857 * pci_enable_device - Initialize device before it's used by a driver.
858 * @dev: PCI device to be initialized
860 * Initialize device before it's used by a driver. Ask low-level code
861 * to enable I/O and memory. Wake up the device if it was suspended.
862 * Beware, this function can fail.
864 * Note we don't actually enable the device many times if we call
865 * this function repeatedly (we just increment the count).
867 int pci_enable_device(struct pci_dev
*dev
)
869 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
873 * Managed PCI resources. This manages device on/off, intx/msi/msix
874 * on/off and BAR regions. pci_dev itself records msi/msix status, so
875 * there's no need to track it separately. pci_devres is initialized
876 * when a device is enabled using managed PCI device enable interface.
879 unsigned int enabled
:1;
880 unsigned int pinned
:1;
881 unsigned int orig_intx
:1;
882 unsigned int restore_intx
:1;
886 static void pcim_release(struct device
*gendev
, void *res
)
888 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
889 struct pci_devres
*this = res
;
892 if (dev
->msi_enabled
)
893 pci_disable_msi(dev
);
894 if (dev
->msix_enabled
)
895 pci_disable_msix(dev
);
897 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
898 if (this->region_mask
& (1 << i
))
899 pci_release_region(dev
, i
);
901 if (this->restore_intx
)
902 pci_intx(dev
, this->orig_intx
);
904 if (this->enabled
&& !this->pinned
)
905 pci_disable_device(dev
);
908 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
910 struct pci_devres
*dr
, *new_dr
;
912 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
916 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
919 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
922 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
924 if (pci_is_managed(pdev
))
925 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
930 * pcim_enable_device - Managed pci_enable_device()
931 * @pdev: PCI device to be initialized
933 * Managed pci_enable_device().
935 int pcim_enable_device(struct pci_dev
*pdev
)
937 struct pci_devres
*dr
;
940 dr
= get_pci_dr(pdev
);
946 rc
= pci_enable_device(pdev
);
948 pdev
->is_managed
= 1;
955 * pcim_pin_device - Pin managed PCI device
956 * @pdev: PCI device to pin
958 * Pin managed PCI device @pdev. Pinned device won't be disabled on
959 * driver detach. @pdev must have been enabled with
960 * pcim_enable_device().
962 void pcim_pin_device(struct pci_dev
*pdev
)
964 struct pci_devres
*dr
;
966 dr
= find_pci_dr(pdev
);
967 WARN_ON(!dr
|| !dr
->enabled
);
973 * pcibios_disable_device - disable arch specific PCI resources for device dev
974 * @dev: the PCI device to disable
976 * Disables architecture specific PCI resources for the device. This
977 * is the default implementation. Architecture implementations can
980 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
982 static void do_pci_disable_device(struct pci_dev
*dev
)
986 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
987 if (pci_command
& PCI_COMMAND_MASTER
) {
988 pci_command
&= ~PCI_COMMAND_MASTER
;
989 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
992 pcibios_disable_device(dev
);
996 * pci_disable_enabled_device - Disable device without updating enable_cnt
997 * @dev: PCI device to disable
999 * NOTE: This function is a backend of PCI power management routines and is
1000 * not supposed to be called drivers.
1002 void pci_disable_enabled_device(struct pci_dev
*dev
)
1004 if (atomic_read(&dev
->enable_cnt
))
1005 do_pci_disable_device(dev
);
1009 * pci_disable_device - Disable PCI device after use
1010 * @dev: PCI device to be disabled
1012 * Signal to the system that the PCI device is not in use by the system
1013 * anymore. This only involves disabling PCI bus-mastering, if active.
1015 * Note we don't actually disable the device until all callers of
1016 * pci_device_enable() have called pci_device_disable().
1019 pci_disable_device(struct pci_dev
*dev
)
1021 struct pci_devres
*dr
;
1023 dr
= find_pci_dr(dev
);
1027 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1030 do_pci_disable_device(dev
);
1032 dev
->is_busmaster
= 0;
1036 * pcibios_set_pcie_reset_state - set reset state for device dev
1037 * @dev: the PCI-E device reset
1038 * @state: Reset state to enter into
1041 * Sets the PCI-E reset state for the device. This is the default
1042 * implementation. Architecture implementations can override this.
1044 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1045 enum pcie_reset_state state
)
1051 * pci_set_pcie_reset_state - set reset state for device dev
1052 * @dev: the PCI-E device reset
1053 * @state: Reset state to enter into
1056 * Sets the PCI reset state for the device.
1058 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1060 return pcibios_set_pcie_reset_state(dev
, state
);
1064 * pci_pme_capable - check the capability of PCI device to generate PME#
1065 * @dev: PCI device to handle.
1066 * @state: PCI state from which device will issue PME#.
1068 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1073 return !!(dev
->pme_support
& (1 << state
));
1077 * pci_pme_active - enable or disable PCI device's PME# function
1078 * @dev: PCI device to handle.
1079 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1081 * The caller must verify that the device is capable of generating PME# before
1082 * calling this function with @enable equal to 'true'.
1084 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1091 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1092 /* Clear PME_Status by writing 1 to it and enable PME# */
1093 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1095 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1097 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1099 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1100 enable
? "enabled" : "disabled");
1104 * pci_enable_wake - enable PCI device as wakeup event source
1105 * @dev: PCI device affected
1106 * @state: PCI state from which device will issue wakeup events
1107 * @enable: True to enable event generation; false to disable
1109 * This enables the device as a wakeup event source, or disables it.
1110 * When such events involves platform-specific hooks, those hooks are
1111 * called automatically by this routine.
1113 * Devices with legacy power management (no standard PCI PM capabilities)
1114 * always require such platform hooks.
1117 * 0 is returned on success
1118 * -EINVAL is returned if device is not supposed to wake up the system
1119 * Error code depending on the platform is returned if both the platform and
1120 * the native mechanism fail to enable the generation of wake-up events
1122 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1125 bool pme_done
= false;
1127 if (enable
&& !device_may_wakeup(&dev
->dev
))
1131 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1132 * Anderson we should be doing PME# wake enable followed by ACPI wake
1133 * enable. To disable wake-up we call the platform first, for symmetry.
1136 if (!enable
&& platform_pci_can_wakeup(dev
))
1137 error
= platform_pci_sleep_wake(dev
, false);
1139 if (!enable
|| pci_pme_capable(dev
, state
)) {
1140 pci_pme_active(dev
, enable
);
1144 if (enable
&& platform_pci_can_wakeup(dev
))
1145 error
= platform_pci_sleep_wake(dev
, true);
1147 return pme_done
? 0 : error
;
1151 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1152 * @dev: PCI device to prepare
1153 * @enable: True to enable wake-up event generation; false to disable
1155 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1156 * and this function allows them to set that up cleanly - pci_enable_wake()
1157 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1158 * ordering constraints.
1160 * This function only returns error code if the device is not capable of
1161 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1162 * enable wake-up power for it.
1164 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1166 return pci_pme_capable(dev
, PCI_D3cold
) ?
1167 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1168 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1172 * pci_target_state - find an appropriate low power state for a given PCI dev
1175 * Use underlying platform code to find a supported low power state for @dev.
1176 * If the platform can't manage @dev, return the deepest state from which it
1177 * can generate wake events, based on any available PME info.
1179 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1181 pci_power_t target_state
= PCI_D3hot
;
1183 if (platform_pci_power_manageable(dev
)) {
1185 * Call the platform to choose the target state of the device
1186 * and enable wake-up from this state if supported.
1188 pci_power_t state
= platform_pci_choose_state(dev
);
1191 case PCI_POWER_ERROR
:
1196 if (pci_no_d1d2(dev
))
1199 target_state
= state
;
1201 } else if (device_may_wakeup(&dev
->dev
)) {
1203 * Find the deepest state from which the device can generate
1204 * wake-up events, make it the target state and enable device
1208 return PCI_POWER_ERROR
;
1210 if (dev
->pme_support
) {
1212 && !(dev
->pme_support
& (1 << target_state
)))
1217 return target_state
;
1221 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1222 * @dev: Device to handle.
1224 * Choose the power state appropriate for the device depending on whether
1225 * it can wake up the system and/or is power manageable by the platform
1226 * (PCI_D3hot is the default) and put the device into that state.
1228 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1230 pci_power_t target_state
= pci_target_state(dev
);
1233 if (target_state
== PCI_POWER_ERROR
)
1236 pci_enable_wake(dev
, target_state
, true);
1238 error
= pci_set_power_state(dev
, target_state
);
1241 pci_enable_wake(dev
, target_state
, false);
1247 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1248 * @dev: Device to handle.
1250 * Disable device's sytem wake-up capability and put it into D0.
1252 int pci_back_from_sleep(struct pci_dev
*dev
)
1254 pci_enable_wake(dev
, PCI_D0
, false);
1255 return pci_set_power_state(dev
, PCI_D0
);
1259 * pci_pm_init - Initialize PM functions of given PCI device
1260 * @dev: PCI device to handle.
1262 void pci_pm_init(struct pci_dev
*dev
)
1269 /* find PCI PM capability in list */
1270 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1273 /* Check device's ability to generate PME# */
1274 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1276 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1277 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1278 pmc
& PCI_PM_CAP_VER_MASK
);
1284 dev
->d1_support
= false;
1285 dev
->d2_support
= false;
1286 if (!pci_no_d1d2(dev
)) {
1287 if (pmc
& PCI_PM_CAP_D1
)
1288 dev
->d1_support
= true;
1289 if (pmc
& PCI_PM_CAP_D2
)
1290 dev
->d2_support
= true;
1292 if (dev
->d1_support
|| dev
->d2_support
)
1293 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1294 dev
->d1_support
? " D1" : "",
1295 dev
->d2_support
? " D2" : "");
1298 pmc
&= PCI_PM_CAP_PME_MASK
;
1300 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1301 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1302 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1303 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1304 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1305 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1306 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1308 * Make device's PM flags reflect the wake-up capability, but
1309 * let the user space enable it to wake up the system as needed.
1311 device_set_wakeup_capable(&dev
->dev
, true);
1312 device_set_wakeup_enable(&dev
->dev
, false);
1313 /* Disable the PME# generation functionality */
1314 pci_pme_active(dev
, false);
1316 dev
->pme_support
= 0;
1321 * platform_pci_wakeup_init - init platform wakeup if present
1324 * Some devices don't have PCI PM caps but can still generate wakeup
1325 * events through platform methods (like ACPI events). If @dev supports
1326 * platform wakeup events, set the device flag to indicate as much. This
1327 * may be redundant if the device also supports PCI PM caps, but double
1328 * initialization should be safe in that case.
1330 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1332 if (!platform_pci_can_wakeup(dev
))
1335 device_set_wakeup_capable(&dev
->dev
, true);
1336 device_set_wakeup_enable(&dev
->dev
, false);
1337 platform_pci_sleep_wake(dev
, false);
1341 * pci_add_save_buffer - allocate buffer for saving given capability registers
1342 * @dev: the PCI device
1343 * @cap: the capability to allocate the buffer for
1344 * @size: requested size of the buffer
1346 static int pci_add_cap_save_buffer(
1347 struct pci_dev
*dev
, char cap
, unsigned int size
)
1350 struct pci_cap_saved_state
*save_state
;
1352 pos
= pci_find_capability(dev
, cap
);
1356 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1360 save_state
->cap_nr
= cap
;
1361 pci_add_saved_cap(dev
, save_state
);
1367 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1368 * @dev: the PCI device
1370 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1374 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
, 4 * sizeof(u16
));
1377 "unable to preallocate PCI Express save buffer\n");
1379 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1382 "unable to preallocate PCI-X save buffer\n");
1386 * pci_restore_standard_config - restore standard config registers of PCI device
1387 * @dev: PCI device to handle
1389 * This function assumes that the device's configuration space is accessible.
1390 * If the device needs to be powered up, the function will wait for it to
1393 int pci_restore_standard_config(struct pci_dev
*dev
)
1395 pci_power_t prev_state
;
1398 pci_update_current_state(dev
, PCI_D0
);
1400 prev_state
= dev
->current_state
;
1401 if (prev_state
== PCI_D0
)
1404 error
= pci_raw_set_power_state(dev
, PCI_D0
, false);
1409 * This assumes that we won't get a bus in B2 or B3 from the BIOS, but
1410 * we've made this assumption forever and it appears to be universally
1413 switch(prev_state
) {
1416 mdelay(pci_pm_d3_delay
);
1419 udelay(PCI_PM_D2_DELAY
);
1423 pci_update_current_state(dev
, PCI_D0
);
1426 return dev
->state_saved
? pci_restore_state(dev
) : 0;
1430 * pci_enable_ari - enable ARI forwarding if hardware support it
1431 * @dev: the PCI device
1433 void pci_enable_ari(struct pci_dev
*dev
)
1438 struct pci_dev
*bridge
;
1440 if (!dev
->is_pcie
|| dev
->devfn
)
1443 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1447 bridge
= dev
->bus
->self
;
1448 if (!bridge
|| !bridge
->is_pcie
)
1451 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1455 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1456 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1459 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1460 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1461 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1463 bridge
->ari_enabled
= 1;
1467 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1468 * @dev: the PCI device
1469 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1471 * Perform INTx swizzling for a device behind one level of bridge. This is
1472 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1473 * behind bridges on add-in cards.
1475 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1477 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1481 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1489 while (dev
->bus
->parent
) {
1490 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1491 dev
= dev
->bus
->self
;
1498 * pci_common_swizzle - swizzle INTx all the way to root bridge
1499 * @dev: the PCI device
1500 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1502 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1503 * bridges all the way up to a PCI root bus.
1505 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1509 while (dev
->bus
->parent
) {
1510 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1511 dev
= dev
->bus
->self
;
1514 return PCI_SLOT(dev
->devfn
);
1518 * pci_release_region - Release a PCI bar
1519 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1520 * @bar: BAR to release
1522 * Releases the PCI I/O and memory resources previously reserved by a
1523 * successful call to pci_request_region. Call this function only
1524 * after all use of the PCI regions has ceased.
1526 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1528 struct pci_devres
*dr
;
1530 if (pci_resource_len(pdev
, bar
) == 0)
1532 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1533 release_region(pci_resource_start(pdev
, bar
),
1534 pci_resource_len(pdev
, bar
));
1535 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1536 release_mem_region(pci_resource_start(pdev
, bar
),
1537 pci_resource_len(pdev
, bar
));
1539 dr
= find_pci_dr(pdev
);
1541 dr
->region_mask
&= ~(1 << bar
);
1545 * __pci_request_region - Reserved PCI I/O and memory resource
1546 * @pdev: PCI device whose resources are to be reserved
1547 * @bar: BAR to be reserved
1548 * @res_name: Name to be associated with resource.
1549 * @exclusive: whether the region access is exclusive or not
1551 * Mark the PCI region associated with PCI device @pdev BR @bar as
1552 * being reserved by owner @res_name. Do not access any
1553 * address inside the PCI regions unless this call returns
1556 * If @exclusive is set, then the region is marked so that userspace
1557 * is explicitly not allowed to map the resource via /dev/mem or
1558 * sysfs MMIO access.
1560 * Returns 0 on success, or %EBUSY on error. A warning
1561 * message is also printed on failure.
1563 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1566 struct pci_devres
*dr
;
1568 if (pci_resource_len(pdev
, bar
) == 0)
1571 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1572 if (!request_region(pci_resource_start(pdev
, bar
),
1573 pci_resource_len(pdev
, bar
), res_name
))
1576 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1577 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1578 pci_resource_len(pdev
, bar
), res_name
,
1583 dr
= find_pci_dr(pdev
);
1585 dr
->region_mask
|= 1 << bar
;
1590 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1592 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1593 &pdev
->resource
[bar
]);
1598 * pci_request_region - Reserve PCI I/O and memory resource
1599 * @pdev: PCI device whose resources are to be reserved
1600 * @bar: BAR to be reserved
1601 * @res_name: Name to be associated with resource
1603 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1604 * being reserved by owner @res_name. Do not access any
1605 * address inside the PCI regions unless this call returns
1608 * Returns 0 on success, or %EBUSY on error. A warning
1609 * message is also printed on failure.
1611 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1613 return __pci_request_region(pdev
, bar
, res_name
, 0);
1617 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1618 * @pdev: PCI device whose resources are to be reserved
1619 * @bar: BAR to be reserved
1620 * @res_name: Name to be associated with resource.
1622 * Mark the PCI region associated with PCI device @pdev BR @bar as
1623 * being reserved by owner @res_name. Do not access any
1624 * address inside the PCI regions unless this call returns
1627 * Returns 0 on success, or %EBUSY on error. A warning
1628 * message is also printed on failure.
1630 * The key difference that _exclusive makes it that userspace is
1631 * explicitly not allowed to map the resource via /dev/mem or
1634 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1636 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1639 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1640 * @pdev: PCI device whose resources were previously reserved
1641 * @bars: Bitmask of BARs to be released
1643 * Release selected PCI I/O and memory resources previously reserved.
1644 * Call this function only after all use of the PCI regions has ceased.
1646 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1650 for (i
= 0; i
< 6; i
++)
1651 if (bars
& (1 << i
))
1652 pci_release_region(pdev
, i
);
1655 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1656 const char *res_name
, int excl
)
1660 for (i
= 0; i
< 6; i
++)
1661 if (bars
& (1 << i
))
1662 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1668 if (bars
& (1 << i
))
1669 pci_release_region(pdev
, i
);
1676 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1677 * @pdev: PCI device whose resources are to be reserved
1678 * @bars: Bitmask of BARs to be requested
1679 * @res_name: Name to be associated with resource
1681 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1682 const char *res_name
)
1684 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1687 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1688 int bars
, const char *res_name
)
1690 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1691 IORESOURCE_EXCLUSIVE
);
1695 * pci_release_regions - Release reserved PCI I/O and memory resources
1696 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1698 * Releases all PCI I/O and memory resources previously reserved by a
1699 * successful call to pci_request_regions. Call this function only
1700 * after all use of the PCI regions has ceased.
1703 void pci_release_regions(struct pci_dev
*pdev
)
1705 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1709 * pci_request_regions - Reserved PCI I/O and memory resources
1710 * @pdev: PCI device whose resources are to be reserved
1711 * @res_name: Name to be associated with resource.
1713 * Mark all PCI regions associated with PCI device @pdev as
1714 * being reserved by owner @res_name. Do not access any
1715 * address inside the PCI regions unless this call returns
1718 * Returns 0 on success, or %EBUSY on error. A warning
1719 * message is also printed on failure.
1721 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1723 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1727 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1728 * @pdev: PCI device whose resources are to be reserved
1729 * @res_name: Name to be associated with resource.
1731 * Mark all PCI regions associated with PCI device @pdev as
1732 * being reserved by owner @res_name. Do not access any
1733 * address inside the PCI regions unless this call returns
1736 * pci_request_regions_exclusive() will mark the region so that
1737 * /dev/mem and the sysfs MMIO access will not be allowed.
1739 * Returns 0 on success, or %EBUSY on error. A warning
1740 * message is also printed on failure.
1742 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1744 return pci_request_selected_regions_exclusive(pdev
,
1745 ((1 << 6) - 1), res_name
);
1748 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1752 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1754 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1756 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1757 if (cmd
!= old_cmd
) {
1758 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1759 enable
? "enabling" : "disabling");
1760 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1762 dev
->is_busmaster
= enable
;
1766 * pci_set_master - enables bus-mastering for device dev
1767 * @dev: the PCI device to enable
1769 * Enables bus-mastering on the device and calls pcibios_set_master()
1770 * to do the needed arch specific settings.
1772 void pci_set_master(struct pci_dev
*dev
)
1774 __pci_set_master(dev
, true);
1775 pcibios_set_master(dev
);
1779 * pci_clear_master - disables bus-mastering for device dev
1780 * @dev: the PCI device to disable
1782 void pci_clear_master(struct pci_dev
*dev
)
1784 __pci_set_master(dev
, false);
1787 #ifdef PCI_DISABLE_MWI
1788 int pci_set_mwi(struct pci_dev
*dev
)
1793 int pci_try_set_mwi(struct pci_dev
*dev
)
1798 void pci_clear_mwi(struct pci_dev
*dev
)
1804 #ifndef PCI_CACHE_LINE_BYTES
1805 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1808 /* This can be overridden by arch code. */
1809 /* Don't forget this is measured in 32-bit words, not bytes */
1810 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1813 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1814 * @dev: the PCI device for which MWI is to be enabled
1816 * Helper function for pci_set_mwi.
1817 * Originally copied from drivers/net/acenic.c.
1818 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1820 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1823 pci_set_cacheline_size(struct pci_dev
*dev
)
1827 if (!pci_cache_line_size
)
1828 return -EINVAL
; /* The system doesn't support MWI. */
1830 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1831 equal to or multiple of the right value. */
1832 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1833 if (cacheline_size
>= pci_cache_line_size
&&
1834 (cacheline_size
% pci_cache_line_size
) == 0)
1837 /* Write the correct value. */
1838 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1840 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1841 if (cacheline_size
== pci_cache_line_size
)
1844 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1845 "supported\n", pci_cache_line_size
<< 2);
1851 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1852 * @dev: the PCI device for which MWI is enabled
1854 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1856 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1859 pci_set_mwi(struct pci_dev
*dev
)
1864 rc
= pci_set_cacheline_size(dev
);
1868 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1869 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1870 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1871 cmd
|= PCI_COMMAND_INVALIDATE
;
1872 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1879 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1880 * @dev: the PCI device for which MWI is enabled
1882 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1883 * Callers are not required to check the return value.
1885 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1887 int pci_try_set_mwi(struct pci_dev
*dev
)
1889 int rc
= pci_set_mwi(dev
);
1894 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1895 * @dev: the PCI device to disable
1897 * Disables PCI Memory-Write-Invalidate transaction on the device
1900 pci_clear_mwi(struct pci_dev
*dev
)
1904 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1905 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1906 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1907 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1910 #endif /* ! PCI_DISABLE_MWI */
1913 * pci_intx - enables/disables PCI INTx for device dev
1914 * @pdev: the PCI device to operate on
1915 * @enable: boolean: whether to enable or disable PCI INTx
1917 * Enables/disables PCI INTx for device dev
1920 pci_intx(struct pci_dev
*pdev
, int enable
)
1922 u16 pci_command
, new;
1924 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1927 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1929 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1932 if (new != pci_command
) {
1933 struct pci_devres
*dr
;
1935 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1937 dr
= find_pci_dr(pdev
);
1938 if (dr
&& !dr
->restore_intx
) {
1939 dr
->restore_intx
= 1;
1940 dr
->orig_intx
= !enable
;
1946 * pci_msi_off - disables any msi or msix capabilities
1947 * @dev: the PCI device to operate on
1949 * If you want to use msi see pci_enable_msi and friends.
1950 * This is a lower level primitive that allows us to disable
1951 * msi operation at the device level.
1953 void pci_msi_off(struct pci_dev
*dev
)
1958 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1960 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1961 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1962 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1964 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1966 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1967 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1968 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1972 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1974 * These can be overridden by arch-specific implementations
1977 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1979 if (!pci_dma_supported(dev
, mask
))
1982 dev
->dma_mask
= mask
;
1988 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1990 if (!pci_dma_supported(dev
, mask
))
1993 dev
->dev
.coherent_dma_mask
= mask
;
1999 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2000 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2002 return dma_set_max_seg_size(&dev
->dev
, size
);
2004 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2007 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2008 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2010 return dma_set_seg_boundary(&dev
->dev
, mask
);
2012 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2015 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
2019 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2023 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
2024 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2030 pci_block_user_cfg_access(dev
);
2032 /* Wait for Transaction Pending bit clean */
2033 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2034 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2035 goto transaction_done
;
2038 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2039 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2040 goto transaction_done
;
2042 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
2043 "sleeping for 1 second\n");
2045 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2046 if (status
& PCI_EXP_DEVSTA_TRPND
)
2047 dev_info(&dev
->dev
, "Still busy after 1s; "
2048 "proceeding with reset anyway\n");
2051 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
2052 PCI_EXP_DEVCTL_BCR_FLR
);
2055 pci_unblock_user_cfg_access(dev
);
2059 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
2061 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2067 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
2068 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2074 pci_block_user_cfg_access(dev
);
2076 /* Wait for Transaction Pending bit clean */
2077 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2078 if (!(status
& PCI_AF_STATUS_TP
))
2079 goto transaction_done
;
2082 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2083 if (!(status
& PCI_AF_STATUS_TP
))
2084 goto transaction_done
;
2086 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
2087 " reset; sleeping for 1 second\n");
2089 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2090 if (status
& PCI_AF_STATUS_TP
)
2091 dev_info(&dev
->dev
, "Still busy after 1s; "
2092 "proceeding with reset anyway\n");
2095 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2098 pci_unblock_user_cfg_access(dev
);
2102 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
2106 res
= __pcie_flr(pdev
, probe
);
2110 res
= __pci_af_flr(pdev
, probe
);
2118 * pci_execute_reset_function() - Reset a PCI device function
2119 * @dev: Device function to reset
2121 * Some devices allow an individual function to be reset without affecting
2122 * other functions in the same device. The PCI device must be responsive
2123 * to PCI config space in order to use this function.
2125 * The device function is presumed to be unused when this function is called.
2126 * Resetting the device will make the contents of PCI configuration space
2127 * random, so any caller of this must be prepared to reinitialise the
2128 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2131 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2132 * device doesn't support resetting a single function.
2134 int pci_execute_reset_function(struct pci_dev
*dev
)
2136 return __pci_reset_function(dev
, 0);
2138 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
2141 * pci_reset_function() - quiesce and reset a PCI device function
2142 * @dev: Device function to reset
2144 * Some devices allow an individual function to be reset without affecting
2145 * other functions in the same device. The PCI device must be responsive
2146 * to PCI config space in order to use this function.
2148 * This function does not just reset the PCI portion of a device, but
2149 * clears all the state associated with the device. This function differs
2150 * from pci_execute_reset_function in that it saves and restores device state
2153 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2154 * device doesn't support resetting a single function.
2156 int pci_reset_function(struct pci_dev
*dev
)
2158 int r
= __pci_reset_function(dev
, 1);
2163 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2164 disable_irq(dev
->irq
);
2165 pci_save_state(dev
);
2167 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2169 r
= pci_execute_reset_function(dev
);
2171 pci_restore_state(dev
);
2172 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2173 enable_irq(dev
->irq
);
2177 EXPORT_SYMBOL_GPL(pci_reset_function
);
2180 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2181 * @dev: PCI device to query
2183 * Returns mmrbc: maximum designed memory read count in bytes
2184 * or appropriate error value.
2186 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2191 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2195 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2199 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2201 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2204 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2205 * @dev: PCI device to query
2207 * Returns mmrbc: maximum memory read count in bytes
2208 * or appropriate error value.
2210 int pcix_get_mmrbc(struct pci_dev
*dev
)
2215 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2219 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2221 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2225 EXPORT_SYMBOL(pcix_get_mmrbc
);
2228 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2229 * @dev: PCI device to query
2230 * @mmrbc: maximum memory read count in bytes
2231 * valid values are 512, 1024, 2048, 4096
2233 * If possible sets maximum memory read byte count, some bridges have erratas
2234 * that prevent this.
2236 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2238 int cap
, err
= -EINVAL
;
2239 u32 stat
, cmd
, v
, o
;
2241 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2244 v
= ffs(mmrbc
) - 10;
2246 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2250 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2254 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2257 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2261 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2263 if (v
> o
&& dev
->bus
&&
2264 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2267 cmd
&= ~PCI_X_CMD_MAX_READ
;
2269 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2274 EXPORT_SYMBOL(pcix_set_mmrbc
);
2277 * pcie_get_readrq - get PCI Express read request size
2278 * @dev: PCI device to query
2280 * Returns maximum memory read request in bytes
2281 * or appropriate error value.
2283 int pcie_get_readrq(struct pci_dev
*dev
)
2288 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2292 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2294 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2298 EXPORT_SYMBOL(pcie_get_readrq
);
2301 * pcie_set_readrq - set PCI Express maximum memory read request
2302 * @dev: PCI device to query
2303 * @rq: maximum memory read count in bytes
2304 * valid values are 128, 256, 512, 1024, 2048, 4096
2306 * If possible sets maximum read byte count
2308 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2310 int cap
, err
= -EINVAL
;
2313 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2316 v
= (ffs(rq
) - 8) << 12;
2318 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2322 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2326 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2327 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2329 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2335 EXPORT_SYMBOL(pcie_set_readrq
);
2338 * pci_select_bars - Make BAR mask from the type of resource
2339 * @dev: the PCI device for which BAR mask is made
2340 * @flags: resource type mask to be selected
2342 * This helper routine makes bar mask from the type of resource.
2344 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2347 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2348 if (pci_resource_flags(dev
, i
) & flags
)
2354 * pci_resource_bar - get position of the BAR associated with a resource
2355 * @dev: the PCI device
2356 * @resno: the resource number
2357 * @type: the BAR type to be filled in
2359 * Returns BAR position in config space, or 0 if the BAR is invalid.
2361 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2363 if (resno
< PCI_ROM_RESOURCE
) {
2364 *type
= pci_bar_unknown
;
2365 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2366 } else if (resno
== PCI_ROM_RESOURCE
) {
2367 *type
= pci_bar_mem32
;
2368 return dev
->rom_base_reg
;
2371 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2375 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2376 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2377 spinlock_t resource_alignment_lock
= SPIN_LOCK_UNLOCKED
;
2380 * pci_specified_resource_alignment - get resource alignment specified by user.
2381 * @dev: the PCI device to get
2383 * RETURNS: Resource alignment if it is specified.
2384 * Zero if it is not specified.
2386 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2388 int seg
, bus
, slot
, func
, align_order
, count
;
2389 resource_size_t align
= 0;
2392 spin_lock(&resource_alignment_lock
);
2393 p
= resource_alignment_param
;
2396 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2402 if (sscanf(p
, "%x:%x:%x.%x%n",
2403 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2405 if (sscanf(p
, "%x:%x.%x%n",
2406 &bus
, &slot
, &func
, &count
) != 3) {
2407 /* Invalid format */
2408 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2414 if (seg
== pci_domain_nr(dev
->bus
) &&
2415 bus
== dev
->bus
->number
&&
2416 slot
== PCI_SLOT(dev
->devfn
) &&
2417 func
== PCI_FUNC(dev
->devfn
)) {
2418 if (align_order
== -1) {
2421 align
= 1 << align_order
;
2426 if (*p
!= ';' && *p
!= ',') {
2427 /* End of param or invalid format */
2432 spin_unlock(&resource_alignment_lock
);
2437 * pci_is_reassigndev - check if specified PCI is target device to reassign
2438 * @dev: the PCI device to check
2440 * RETURNS: non-zero for PCI device is a target device to reassign,
2443 int pci_is_reassigndev(struct pci_dev
*dev
)
2445 return (pci_specified_resource_alignment(dev
) != 0);
2448 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2450 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2451 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2452 spin_lock(&resource_alignment_lock
);
2453 strncpy(resource_alignment_param
, buf
, count
);
2454 resource_alignment_param
[count
] = '\0';
2455 spin_unlock(&resource_alignment_lock
);
2459 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2462 spin_lock(&resource_alignment_lock
);
2463 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2464 spin_unlock(&resource_alignment_lock
);
2468 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2470 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2473 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2474 const char *buf
, size_t count
)
2476 return pci_set_resource_alignment_param(buf
, count
);
2479 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2480 pci_resource_alignment_store
);
2482 static int __init
pci_resource_alignment_sysfs_init(void)
2484 return bus_create_file(&pci_bus_type
,
2485 &bus_attr_resource_alignment
);
2488 late_initcall(pci_resource_alignment_sysfs_init
);
2490 static void __devinit
pci_no_domains(void)
2492 #ifdef CONFIG_PCI_DOMAINS
2493 pci_domains_supported
= 0;
2498 * pci_ext_cfg_enabled - can we access extended PCI config space?
2499 * @dev: The PCI device of the root bridge.
2501 * Returns 1 if we can access PCI extended config space (offsets
2502 * greater than 0xff). This is the default implementation. Architecture
2503 * implementations can override this.
2505 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2510 static int __devinit
pci_init(void)
2512 struct pci_dev
*dev
= NULL
;
2514 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2515 pci_fixup_device(pci_fixup_final
, dev
);
2521 static int __init
pci_setup(char *str
)
2524 char *k
= strchr(str
, ',');
2527 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2528 if (!strcmp(str
, "nomsi")) {
2530 } else if (!strcmp(str
, "noaer")) {
2532 } else if (!strcmp(str
, "nodomains")) {
2534 } else if (!strncmp(str
, "cbiosize=", 9)) {
2535 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2536 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2537 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2538 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2539 pci_set_resource_alignment_param(str
+ 19,
2542 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2550 early_param("pci", pci_setup
);
2552 device_initcall(pci_init
);
2554 EXPORT_SYMBOL(pci_reenable_device
);
2555 EXPORT_SYMBOL(pci_enable_device_io
);
2556 EXPORT_SYMBOL(pci_enable_device_mem
);
2557 EXPORT_SYMBOL(pci_enable_device
);
2558 EXPORT_SYMBOL(pcim_enable_device
);
2559 EXPORT_SYMBOL(pcim_pin_device
);
2560 EXPORT_SYMBOL(pci_disable_device
);
2561 EXPORT_SYMBOL(pci_find_capability
);
2562 EXPORT_SYMBOL(pci_bus_find_capability
);
2563 EXPORT_SYMBOL(pci_release_regions
);
2564 EXPORT_SYMBOL(pci_request_regions
);
2565 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2566 EXPORT_SYMBOL(pci_release_region
);
2567 EXPORT_SYMBOL(pci_request_region
);
2568 EXPORT_SYMBOL(pci_request_region_exclusive
);
2569 EXPORT_SYMBOL(pci_release_selected_regions
);
2570 EXPORT_SYMBOL(pci_request_selected_regions
);
2571 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2572 EXPORT_SYMBOL(pci_set_master
);
2573 EXPORT_SYMBOL(pci_clear_master
);
2574 EXPORT_SYMBOL(pci_set_mwi
);
2575 EXPORT_SYMBOL(pci_try_set_mwi
);
2576 EXPORT_SYMBOL(pci_clear_mwi
);
2577 EXPORT_SYMBOL_GPL(pci_intx
);
2578 EXPORT_SYMBOL(pci_set_dma_mask
);
2579 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2580 EXPORT_SYMBOL(pci_assign_resource
);
2581 EXPORT_SYMBOL(pci_find_parent_resource
);
2582 EXPORT_SYMBOL(pci_select_bars
);
2584 EXPORT_SYMBOL(pci_set_power_state
);
2585 EXPORT_SYMBOL(pci_save_state
);
2586 EXPORT_SYMBOL(pci_restore_state
);
2587 EXPORT_SYMBOL(pci_pme_capable
);
2588 EXPORT_SYMBOL(pci_pme_active
);
2589 EXPORT_SYMBOL(pci_enable_wake
);
2590 EXPORT_SYMBOL(pci_wake_from_d3
);
2591 EXPORT_SYMBOL(pci_target_state
);
2592 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2593 EXPORT_SYMBOL(pci_back_from_sleep
);
2594 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);