2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21 #include <linux/log2.h>
22 #include <linux/pci-aspm.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pci_hotplug.h>
28 #include <asm-generic/pci-bridge.h>
29 #include <asm/setup.h>
32 const char *pci_power_names
[] = {
33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
35 EXPORT_SYMBOL_GPL(pci_power_names
);
37 int isa_dma_bridge_buggy
;
38 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
41 EXPORT_SYMBOL(pci_pci_problems
);
43 unsigned int pci_pm_d3_delay
;
45 static void pci_pme_list_scan(struct work_struct
*work
);
47 static LIST_HEAD(pci_pme_list
);
48 static DEFINE_MUTEX(pci_pme_list_mutex
);
49 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
51 struct pci_pme_device
{
52 struct list_head list
;
56 #define PME_TIMEOUT 1000 /* How long between PME checks */
58 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
60 unsigned int delay
= dev
->d3_delay
;
62 if (delay
< pci_pm_d3_delay
)
63 delay
= pci_pm_d3_delay
;
68 #ifdef CONFIG_PCI_DOMAINS
69 int pci_domains_supported
= 1;
72 #define DEFAULT_CARDBUS_IO_SIZE (256)
73 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
74 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
75 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
76 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
78 #define DEFAULT_HOTPLUG_IO_SIZE (256)
79 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
80 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
81 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
82 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
84 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
87 * The default CLS is used if arch didn't set CLS explicitly and not
88 * all pci devices agree on the same value. Arch can override either
89 * the dfl or actual value as it sees fit. Don't forget this is
90 * measured in 32-bit words, not bytes.
92 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
93 u8 pci_cache_line_size
;
96 * If we set up a device for bus mastering, we need to check the latency
97 * timer as certain BIOSes forget to set it properly.
99 unsigned int pcibios_max_latency
= 255;
101 /* If set, the PCIe ARI capability will not be used. */
102 static bool pcie_ari_disabled
;
105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
106 * @bus: pointer to PCI bus structure to search
108 * Given a PCI bus, returns the highest PCI bus number present in the set
109 * including the given PCI bus and its list of child PCI buses.
111 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
114 unsigned char max
, n
;
116 max
= bus
->busn_res
.end
;
117 list_for_each_entry(tmp
, &bus
->children
, node
) {
118 n
= pci_bus_max_busnr(tmp
);
124 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
126 #ifdef CONFIG_HAS_IOMEM
127 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
129 struct resource
*res
= &pdev
->resource
[bar
];
132 * Make sure the BAR is actually a memory resource, not an IO resource
134 if (!(res
->flags
& IORESOURCE_MEM
)) {
135 dev_warn(&pdev
->dev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
138 return ioremap_nocache(res
->start
, resource_size(res
));
140 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
143 #define PCI_FIND_CAP_TTL 48
145 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
146 u8 pos
, int cap
, int *ttl
)
151 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
155 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
161 pos
+= PCI_CAP_LIST_NEXT
;
166 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
169 int ttl
= PCI_FIND_CAP_TTL
;
171 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
174 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
176 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
177 pos
+ PCI_CAP_LIST_NEXT
, cap
);
179 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
181 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
182 unsigned int devfn
, u8 hdr_type
)
186 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
187 if (!(status
& PCI_STATUS_CAP_LIST
))
191 case PCI_HEADER_TYPE_NORMAL
:
192 case PCI_HEADER_TYPE_BRIDGE
:
193 return PCI_CAPABILITY_LIST
;
194 case PCI_HEADER_TYPE_CARDBUS
:
195 return PCI_CB_CAPABILITY_LIST
;
204 * pci_find_capability - query for devices' capabilities
205 * @dev: PCI device to query
206 * @cap: capability code
208 * Tell if a device supports a given PCI capability.
209 * Returns the address of the requested capability structure within the
210 * device's PCI configuration space or 0 in case the device does not
211 * support it. Possible values for @cap:
213 * %PCI_CAP_ID_PM Power Management
214 * %PCI_CAP_ID_AGP Accelerated Graphics Port
215 * %PCI_CAP_ID_VPD Vital Product Data
216 * %PCI_CAP_ID_SLOTID Slot Identification
217 * %PCI_CAP_ID_MSI Message Signalled Interrupts
218 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
219 * %PCI_CAP_ID_PCIX PCI-X
220 * %PCI_CAP_ID_EXP PCI Express
222 int pci_find_capability(struct pci_dev
*dev
, int cap
)
226 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
228 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
232 EXPORT_SYMBOL(pci_find_capability
);
235 * pci_bus_find_capability - query for devices' capabilities
236 * @bus: the PCI bus to query
237 * @devfn: PCI device to query
238 * @cap: capability code
240 * Like pci_find_capability() but works for pci devices that do not have a
241 * pci_dev structure set up yet.
243 * Returns the address of the requested capability structure within the
244 * device's PCI configuration space or 0 in case the device does not
247 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
252 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
254 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
256 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
260 EXPORT_SYMBOL(pci_bus_find_capability
);
263 * pci_find_next_ext_capability - Find an extended capability
264 * @dev: PCI device to query
265 * @start: address at which to start looking (0 to start at beginning of list)
266 * @cap: capability code
268 * Returns the address of the next matching extended capability structure
269 * within the device's PCI configuration space or 0 if the device does
270 * not support it. Some capabilities can occur several times, e.g., the
271 * vendor-specific capability, and this provides a way to find them all.
273 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
277 int pos
= PCI_CFG_SPACE_SIZE
;
279 /* minimum 8 bytes per capability */
280 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
282 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
288 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
292 * If we have no capabilities, this is indicated by cap ID,
293 * cap version and next pointer all being 0.
299 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
302 pos
= PCI_EXT_CAP_NEXT(header
);
303 if (pos
< PCI_CFG_SPACE_SIZE
)
306 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
312 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
315 * pci_find_ext_capability - Find an extended capability
316 * @dev: PCI device to query
317 * @cap: capability code
319 * Returns the address of the requested extended capability structure
320 * within the device's PCI configuration space or 0 if the device does
321 * not support it. Possible values for @cap:
323 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
324 * %PCI_EXT_CAP_ID_VC Virtual Channel
325 * %PCI_EXT_CAP_ID_DSN Device Serial Number
326 * %PCI_EXT_CAP_ID_PWR Power Budgeting
328 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
330 return pci_find_next_ext_capability(dev
, 0, cap
);
332 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
334 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
336 int rc
, ttl
= PCI_FIND_CAP_TTL
;
339 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
340 mask
= HT_3BIT_CAP_MASK
;
342 mask
= HT_5BIT_CAP_MASK
;
344 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
345 PCI_CAP_ID_HT
, &ttl
);
347 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
348 if (rc
!= PCIBIOS_SUCCESSFUL
)
351 if ((cap
& mask
) == ht_cap
)
354 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
355 pos
+ PCI_CAP_LIST_NEXT
,
356 PCI_CAP_ID_HT
, &ttl
);
362 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
363 * @dev: PCI device to query
364 * @pos: Position from which to continue searching
365 * @ht_cap: Hypertransport capability code
367 * To be used in conjunction with pci_find_ht_capability() to search for
368 * all capabilities matching @ht_cap. @pos should always be a value returned
369 * from pci_find_ht_capability().
371 * NB. To be 100% safe against broken PCI devices, the caller should take
372 * steps to avoid an infinite loop.
374 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
376 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
378 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
381 * pci_find_ht_capability - query a device's Hypertransport capabilities
382 * @dev: PCI device to query
383 * @ht_cap: Hypertransport capability code
385 * Tell if a device supports a given Hypertransport capability.
386 * Returns an address within the device's PCI configuration space
387 * or 0 in case the device does not support the request capability.
388 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
389 * which has a Hypertransport capability matching @ht_cap.
391 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
395 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
397 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
401 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
404 * pci_find_parent_resource - return resource region of parent bus of given region
405 * @dev: PCI device structure contains resources to be searched
406 * @res: child resource record for which parent is sought
408 * For given resource region of given device, return the resource
409 * region of parent bus the given region is contained in.
411 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
412 struct resource
*res
)
414 const struct pci_bus
*bus
= dev
->bus
;
418 pci_bus_for_each_resource(bus
, r
, i
) {
421 if (res
->start
&& resource_contains(r
, res
)) {
424 * If the window is prefetchable but the BAR is
425 * not, the allocator made a mistake.
427 if (r
->flags
& IORESOURCE_PREFETCH
&&
428 !(res
->flags
& IORESOURCE_PREFETCH
))
432 * If we're below a transparent bridge, there may
433 * be both a positively-decoded aperture and a
434 * subtractively-decoded region that contain the BAR.
435 * We want the positively-decoded one, so this depends
436 * on pci_bus_for_each_resource() giving us those
444 EXPORT_SYMBOL(pci_find_parent_resource
);
447 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
448 * @dev: the PCI device to operate on
449 * @pos: config space offset of status word
450 * @mask: mask of bit(s) to care about in status word
452 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
454 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
458 /* Wait for Transaction Pending bit clean */
459 for (i
= 0; i
< 4; i
++) {
462 msleep((1 << (i
- 1)) * 100);
464 pci_read_config_word(dev
, pos
, &status
);
465 if (!(status
& mask
))
473 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
474 * @dev: PCI device to have its BARs restored
476 * Restore the BAR values for a given device, so as to make it
477 * accessible by its driver.
479 static void pci_restore_bars(struct pci_dev
*dev
)
483 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
484 pci_update_resource(dev
, i
);
487 static struct pci_platform_pm_ops
*pci_platform_pm
;
489 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
491 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
494 pci_platform_pm
= ops
;
498 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
500 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
503 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
506 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
509 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
511 return pci_platform_pm
?
512 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
515 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
517 return pci_platform_pm
?
518 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
521 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
523 return pci_platform_pm
?
524 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
527 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
529 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
533 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
535 * @dev: PCI device to handle.
536 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
539 * -EINVAL if the requested state is invalid.
540 * -EIO if device does not support PCI PM or its PM capabilities register has a
541 * wrong version, or device doesn't support the requested state.
542 * 0 if device already is in the requested state.
543 * 0 if device's power state has been successfully changed.
545 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
548 bool need_restore
= false;
550 /* Check if we're already there */
551 if (dev
->current_state
== state
)
557 if (state
< PCI_D0
|| state
> PCI_D3hot
)
560 /* Validate current state:
561 * Can enter D0 from any state, but if we can only go deeper
562 * to sleep if we're already in a low power state
564 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
565 && dev
->current_state
> state
) {
566 dev_err(&dev
->dev
, "invalid power transition (from state %d to %d)\n",
567 dev
->current_state
, state
);
571 /* check if this device supports the desired state */
572 if ((state
== PCI_D1
&& !dev
->d1_support
)
573 || (state
== PCI_D2
&& !dev
->d2_support
))
576 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
578 /* If we're (effectively) in D3, force entire word to 0.
579 * This doesn't affect PME_Status, disables PME_En, and
580 * sets PowerState to 0.
582 switch (dev
->current_state
) {
586 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
591 case PCI_UNKNOWN
: /* Boot-up */
592 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
593 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
595 /* Fall-through: force to D0 */
601 /* enter specified state */
602 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
604 /* Mandatory power management transition delays */
605 /* see PCI PM 1.1 5.6.1 table 18 */
606 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
607 pci_dev_d3_sleep(dev
);
608 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
609 udelay(PCI_PM_D2_DELAY
);
611 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
612 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
613 if (dev
->current_state
!= state
&& printk_ratelimit())
614 dev_info(&dev
->dev
, "Refused to change power state, currently in D%d\n",
618 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
619 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
620 * from D3hot to D0 _may_ perform an internal reset, thereby
621 * going to "D0 Uninitialized" rather than "D0 Initialized".
622 * For example, at least some versions of the 3c905B and the
623 * 3c556B exhibit this behaviour.
625 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
626 * devices in a D3hot state at boot. Consequently, we need to
627 * restore at least the BARs so that the device will be
628 * accessible to its driver.
631 pci_restore_bars(dev
);
634 pcie_aspm_pm_state_change(dev
->bus
->self
);
640 * pci_update_current_state - Read PCI power state of given device from its
641 * PCI PM registers and cache it
642 * @dev: PCI device to handle.
643 * @state: State to cache in case the device doesn't have the PM capability
645 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
651 * Configuration space is not accessible for device in
652 * D3cold, so just keep or set D3cold for safety
654 if (dev
->current_state
== PCI_D3cold
)
656 if (state
== PCI_D3cold
) {
657 dev
->current_state
= PCI_D3cold
;
660 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
661 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
663 dev
->current_state
= state
;
668 * pci_power_up - Put the given device into D0 forcibly
669 * @dev: PCI device to power up
671 void pci_power_up(struct pci_dev
*dev
)
673 if (platform_pci_power_manageable(dev
))
674 platform_pci_set_power_state(dev
, PCI_D0
);
676 pci_raw_set_power_state(dev
, PCI_D0
);
677 pci_update_current_state(dev
, PCI_D0
);
681 * pci_platform_power_transition - Use platform to change device power state
682 * @dev: PCI device to handle.
683 * @state: State to put the device into.
685 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
689 if (platform_pci_power_manageable(dev
)) {
690 error
= platform_pci_set_power_state(dev
, state
);
692 pci_update_current_state(dev
, state
);
696 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
697 dev
->current_state
= PCI_D0
;
703 * pci_wakeup - Wake up a PCI device
704 * @pci_dev: Device to handle.
705 * @ign: ignored parameter
707 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
709 pci_wakeup_event(pci_dev
);
710 pm_request_resume(&pci_dev
->dev
);
715 * pci_wakeup_bus - Walk given bus and wake up devices on it
716 * @bus: Top bus of the subtree to walk.
718 static void pci_wakeup_bus(struct pci_bus
*bus
)
721 pci_walk_bus(bus
, pci_wakeup
, NULL
);
725 * __pci_start_power_transition - Start power transition of a PCI device
726 * @dev: PCI device to handle.
727 * @state: State to put the device into.
729 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
731 if (state
== PCI_D0
) {
732 pci_platform_power_transition(dev
, PCI_D0
);
734 * Mandatory power management transition delays, see
735 * PCI Express Base Specification Revision 2.0 Section
736 * 6.6.1: Conventional Reset. Do not delay for
737 * devices powered on/off by corresponding bridge,
738 * because have already delayed for the bridge.
740 if (dev
->runtime_d3cold
) {
741 msleep(dev
->d3cold_delay
);
743 * When powering on a bridge from D3cold, the
744 * whole hierarchy may be powered on into
745 * D0uninitialized state, resume them to give
746 * them a chance to suspend again
748 pci_wakeup_bus(dev
->subordinate
);
754 * __pci_dev_set_current_state - Set current state of a PCI device
755 * @dev: Device to handle
756 * @data: pointer to state to be set
758 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
760 pci_power_t state
= *(pci_power_t
*)data
;
762 dev
->current_state
= state
;
767 * __pci_bus_set_current_state - Walk given bus and set current state of devices
768 * @bus: Top bus of the subtree to walk.
769 * @state: state to be set
771 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
774 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
778 * __pci_complete_power_transition - Complete power transition of a PCI device
779 * @dev: PCI device to handle.
780 * @state: State to put the device into.
782 * This function should not be called directly by device drivers.
784 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
790 ret
= pci_platform_power_transition(dev
, state
);
791 /* Power off the bridge may power off the whole hierarchy */
792 if (!ret
&& state
== PCI_D3cold
)
793 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
796 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
799 * pci_set_power_state - Set the power state of a PCI device
800 * @dev: PCI device to handle.
801 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
803 * Transition a device to a new power state, using the platform firmware and/or
804 * the device's PCI PM registers.
807 * -EINVAL if the requested state is invalid.
808 * -EIO if device does not support PCI PM or its PM capabilities register has a
809 * wrong version, or device doesn't support the requested state.
810 * 0 if device already is in the requested state.
811 * 0 if device's power state has been successfully changed.
813 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
817 /* bound the state we're entering */
818 if (state
> PCI_D3cold
)
820 else if (state
< PCI_D0
)
822 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
824 * If the device or the parent bridge do not support PCI PM,
825 * ignore the request if we're doing anything other than putting
826 * it into D0 (which would only happen on boot).
830 /* Check if we're already there */
831 if (dev
->current_state
== state
)
834 __pci_start_power_transition(dev
, state
);
836 /* This device is quirked not to be put into D3, so
837 don't put it in D3 */
838 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
842 * To put device in D3cold, we put device into D3hot in native
843 * way, then put device into D3cold with platform ops
845 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
848 if (!__pci_complete_power_transition(dev
, state
))
853 EXPORT_SYMBOL(pci_set_power_state
);
856 * pci_choose_state - Choose the power state of a PCI device
857 * @dev: PCI device to be suspended
858 * @state: target sleep state for the whole system. This is the value
859 * that is passed to suspend() function.
861 * Returns PCI power state suitable for given device and given system
865 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
872 ret
= platform_pci_choose_state(dev
);
873 if (ret
!= PCI_POWER_ERROR
)
876 switch (state
.event
) {
879 case PM_EVENT_FREEZE
:
880 case PM_EVENT_PRETHAW
:
881 /* REVISIT both freeze and pre-thaw "should" use D0 */
882 case PM_EVENT_SUSPEND
:
883 case PM_EVENT_HIBERNATE
:
886 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
892 EXPORT_SYMBOL(pci_choose_state
);
894 #define PCI_EXP_SAVE_REGS 7
896 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
897 u16 cap
, bool extended
)
899 struct pci_cap_saved_state
*tmp
;
901 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
902 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
908 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
910 return _pci_find_saved_cap(dev
, cap
, false);
913 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
915 return _pci_find_saved_cap(dev
, cap
, true);
918 static int pci_save_pcie_state(struct pci_dev
*dev
)
921 struct pci_cap_saved_state
*save_state
;
924 if (!pci_is_pcie(dev
))
927 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
929 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
933 cap
= (u16
*)&save_state
->cap
.data
[0];
934 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
935 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
936 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
937 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
938 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
939 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
940 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
945 static void pci_restore_pcie_state(struct pci_dev
*dev
)
948 struct pci_cap_saved_state
*save_state
;
951 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
955 cap
= (u16
*)&save_state
->cap
.data
[0];
956 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
957 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
958 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
959 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
960 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
961 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
962 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
966 static int pci_save_pcix_state(struct pci_dev
*dev
)
969 struct pci_cap_saved_state
*save_state
;
971 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
975 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
977 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
981 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
982 (u16
*)save_state
->cap
.data
);
987 static void pci_restore_pcix_state(struct pci_dev
*dev
)
990 struct pci_cap_saved_state
*save_state
;
993 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
994 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
995 if (!save_state
|| pos
<= 0)
997 cap
= (u16
*)&save_state
->cap
.data
[0];
999 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1004 * pci_save_state - save the PCI configuration space of a device before suspending
1005 * @dev: - PCI device that we're dealing with
1007 int pci_save_state(struct pci_dev
*dev
)
1010 /* XXX: 100% dword access ok here? */
1011 for (i
= 0; i
< 16; i
++)
1012 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1013 dev
->state_saved
= true;
1015 i
= pci_save_pcie_state(dev
);
1019 i
= pci_save_pcix_state(dev
);
1023 return pci_save_vc_state(dev
);
1025 EXPORT_SYMBOL(pci_save_state
);
1027 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1028 u32 saved_val
, int retry
)
1032 pci_read_config_dword(pdev
, offset
, &val
);
1033 if (val
== saved_val
)
1037 dev_dbg(&pdev
->dev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1038 offset
, val
, saved_val
);
1039 pci_write_config_dword(pdev
, offset
, saved_val
);
1043 pci_read_config_dword(pdev
, offset
, &val
);
1044 if (val
== saved_val
)
1051 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1052 int start
, int end
, int retry
)
1056 for (index
= end
; index
>= start
; index
--)
1057 pci_restore_config_dword(pdev
, 4 * index
,
1058 pdev
->saved_config_space
[index
],
1062 static void pci_restore_config_space(struct pci_dev
*pdev
)
1064 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1065 pci_restore_config_space_range(pdev
, 10, 15, 0);
1066 /* Restore BARs before the command register. */
1067 pci_restore_config_space_range(pdev
, 4, 9, 10);
1068 pci_restore_config_space_range(pdev
, 0, 3, 0);
1070 pci_restore_config_space_range(pdev
, 0, 15, 0);
1075 * pci_restore_state - Restore the saved state of a PCI device
1076 * @dev: - PCI device that we're dealing with
1078 void pci_restore_state(struct pci_dev
*dev
)
1080 if (!dev
->state_saved
)
1083 /* PCI Express register must be restored first */
1084 pci_restore_pcie_state(dev
);
1085 pci_restore_ats_state(dev
);
1086 pci_restore_vc_state(dev
);
1088 pci_restore_config_space(dev
);
1090 pci_restore_pcix_state(dev
);
1091 pci_restore_msi_state(dev
);
1092 pci_restore_iov_state(dev
);
1094 dev
->state_saved
= false;
1096 EXPORT_SYMBOL(pci_restore_state
);
1098 struct pci_saved_state
{
1099 u32 config_space
[16];
1100 struct pci_cap_saved_data cap
[0];
1104 * pci_store_saved_state - Allocate and return an opaque struct containing
1105 * the device saved state.
1106 * @dev: PCI device that we're dealing with
1108 * Return NULL if no state or error.
1110 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1112 struct pci_saved_state
*state
;
1113 struct pci_cap_saved_state
*tmp
;
1114 struct pci_cap_saved_data
*cap
;
1117 if (!dev
->state_saved
)
1120 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1122 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1123 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1125 state
= kzalloc(size
, GFP_KERNEL
);
1129 memcpy(state
->config_space
, dev
->saved_config_space
,
1130 sizeof(state
->config_space
));
1133 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1134 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1135 memcpy(cap
, &tmp
->cap
, len
);
1136 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1138 /* Empty cap_save terminates list */
1142 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1145 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1146 * @dev: PCI device that we're dealing with
1147 * @state: Saved state returned from pci_store_saved_state()
1149 int pci_load_saved_state(struct pci_dev
*dev
,
1150 struct pci_saved_state
*state
)
1152 struct pci_cap_saved_data
*cap
;
1154 dev
->state_saved
= false;
1159 memcpy(dev
->saved_config_space
, state
->config_space
,
1160 sizeof(state
->config_space
));
1164 struct pci_cap_saved_state
*tmp
;
1166 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1167 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1170 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1171 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1172 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1175 dev
->state_saved
= true;
1178 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1181 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1182 * and free the memory allocated for it.
1183 * @dev: PCI device that we're dealing with
1184 * @state: Pointer to saved state returned from pci_store_saved_state()
1186 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1187 struct pci_saved_state
**state
)
1189 int ret
= pci_load_saved_state(dev
, *state
);
1194 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1196 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1198 return pci_enable_resources(dev
, bars
);
1201 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1204 struct pci_dev
*bridge
;
1208 err
= pci_set_power_state(dev
, PCI_D0
);
1209 if (err
< 0 && err
!= -EIO
)
1212 bridge
= pci_upstream_bridge(dev
);
1214 pcie_aspm_powersave_config_link(bridge
);
1216 err
= pcibios_enable_device(dev
, bars
);
1219 pci_fixup_device(pci_fixup_enable
, dev
);
1221 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1224 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1226 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1227 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1228 pci_write_config_word(dev
, PCI_COMMAND
,
1229 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1236 * pci_reenable_device - Resume abandoned device
1237 * @dev: PCI device to be resumed
1239 * Note this function is a backend of pci_default_resume and is not supposed
1240 * to be called by normal code, write proper resume handler and use it instead.
1242 int pci_reenable_device(struct pci_dev
*dev
)
1244 if (pci_is_enabled(dev
))
1245 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1248 EXPORT_SYMBOL(pci_reenable_device
);
1250 static void pci_enable_bridge(struct pci_dev
*dev
)
1252 struct pci_dev
*bridge
;
1255 bridge
= pci_upstream_bridge(dev
);
1257 pci_enable_bridge(bridge
);
1259 if (pci_is_enabled(dev
)) {
1260 if (!dev
->is_busmaster
)
1261 pci_set_master(dev
);
1265 retval
= pci_enable_device(dev
);
1267 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1269 pci_set_master(dev
);
1272 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1274 struct pci_dev
*bridge
;
1279 * Power state could be unknown at this point, either due to a fresh
1280 * boot or a device removal call. So get the current power state
1281 * so that things like MSI message writing will behave as expected
1282 * (e.g. if the device really is in D0 at enable time).
1286 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1287 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1290 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1291 return 0; /* already enabled */
1293 bridge
= pci_upstream_bridge(dev
);
1295 pci_enable_bridge(bridge
);
1297 /* only skip sriov related */
1298 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1299 if (dev
->resource
[i
].flags
& flags
)
1301 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1302 if (dev
->resource
[i
].flags
& flags
)
1305 err
= do_pci_enable_device(dev
, bars
);
1307 atomic_dec(&dev
->enable_cnt
);
1312 * pci_enable_device_io - Initialize a device for use with IO space
1313 * @dev: PCI device to be initialized
1315 * Initialize device before it's used by a driver. Ask low-level code
1316 * to enable I/O resources. Wake up the device if it was suspended.
1317 * Beware, this function can fail.
1319 int pci_enable_device_io(struct pci_dev
*dev
)
1321 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1323 EXPORT_SYMBOL(pci_enable_device_io
);
1326 * pci_enable_device_mem - Initialize a device for use with Memory space
1327 * @dev: PCI device to be initialized
1329 * Initialize device before it's used by a driver. Ask low-level code
1330 * to enable Memory resources. Wake up the device if it was suspended.
1331 * Beware, this function can fail.
1333 int pci_enable_device_mem(struct pci_dev
*dev
)
1335 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1337 EXPORT_SYMBOL(pci_enable_device_mem
);
1340 * pci_enable_device - Initialize device before it's used by a driver.
1341 * @dev: PCI device to be initialized
1343 * Initialize device before it's used by a driver. Ask low-level code
1344 * to enable I/O and memory. Wake up the device if it was suspended.
1345 * Beware, this function can fail.
1347 * Note we don't actually enable the device many times if we call
1348 * this function repeatedly (we just increment the count).
1350 int pci_enable_device(struct pci_dev
*dev
)
1352 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1354 EXPORT_SYMBOL(pci_enable_device
);
1357 * Managed PCI resources. This manages device on/off, intx/msi/msix
1358 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1359 * there's no need to track it separately. pci_devres is initialized
1360 * when a device is enabled using managed PCI device enable interface.
1363 unsigned int enabled
:1;
1364 unsigned int pinned
:1;
1365 unsigned int orig_intx
:1;
1366 unsigned int restore_intx
:1;
1370 static void pcim_release(struct device
*gendev
, void *res
)
1372 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1373 struct pci_devres
*this = res
;
1376 if (dev
->msi_enabled
)
1377 pci_disable_msi(dev
);
1378 if (dev
->msix_enabled
)
1379 pci_disable_msix(dev
);
1381 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1382 if (this->region_mask
& (1 << i
))
1383 pci_release_region(dev
, i
);
1385 if (this->restore_intx
)
1386 pci_intx(dev
, this->orig_intx
);
1388 if (this->enabled
&& !this->pinned
)
1389 pci_disable_device(dev
);
1392 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1394 struct pci_devres
*dr
, *new_dr
;
1396 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1400 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1403 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1406 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
1408 if (pci_is_managed(pdev
))
1409 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1414 * pcim_enable_device - Managed pci_enable_device()
1415 * @pdev: PCI device to be initialized
1417 * Managed pci_enable_device().
1419 int pcim_enable_device(struct pci_dev
*pdev
)
1421 struct pci_devres
*dr
;
1424 dr
= get_pci_dr(pdev
);
1430 rc
= pci_enable_device(pdev
);
1432 pdev
->is_managed
= 1;
1437 EXPORT_SYMBOL(pcim_enable_device
);
1440 * pcim_pin_device - Pin managed PCI device
1441 * @pdev: PCI device to pin
1443 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1444 * driver detach. @pdev must have been enabled with
1445 * pcim_enable_device().
1447 void pcim_pin_device(struct pci_dev
*pdev
)
1449 struct pci_devres
*dr
;
1451 dr
= find_pci_dr(pdev
);
1452 WARN_ON(!dr
|| !dr
->enabled
);
1456 EXPORT_SYMBOL(pcim_pin_device
);
1459 * pcibios_add_device - provide arch specific hooks when adding device dev
1460 * @dev: the PCI device being added
1462 * Permits the platform to provide architecture specific functionality when
1463 * devices are added. This is the default implementation. Architecture
1464 * implementations can override this.
1466 int __weak
pcibios_add_device(struct pci_dev
*dev
)
1472 * pcibios_release_device - provide arch specific hooks when releasing device dev
1473 * @dev: the PCI device being released
1475 * Permits the platform to provide architecture specific functionality when
1476 * devices are released. This is the default implementation. Architecture
1477 * implementations can override this.
1479 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1482 * pcibios_disable_device - disable arch specific PCI resources for device dev
1483 * @dev: the PCI device to disable
1485 * Disables architecture specific PCI resources for the device. This
1486 * is the default implementation. Architecture implementations can
1489 void __weak
pcibios_disable_device (struct pci_dev
*dev
) {}
1492 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1493 * @irq: ISA IRQ to penalize
1494 * @active: IRQ active or not
1496 * Permits the platform to provide architecture-specific functionality when
1497 * penalizing ISA IRQs. This is the default implementation. Architecture
1498 * implementations can override this.
1500 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
1502 static void do_pci_disable_device(struct pci_dev
*dev
)
1506 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1507 if (pci_command
& PCI_COMMAND_MASTER
) {
1508 pci_command
&= ~PCI_COMMAND_MASTER
;
1509 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1512 pcibios_disable_device(dev
);
1516 * pci_disable_enabled_device - Disable device without updating enable_cnt
1517 * @dev: PCI device to disable
1519 * NOTE: This function is a backend of PCI power management routines and is
1520 * not supposed to be called drivers.
1522 void pci_disable_enabled_device(struct pci_dev
*dev
)
1524 if (pci_is_enabled(dev
))
1525 do_pci_disable_device(dev
);
1529 * pci_disable_device - Disable PCI device after use
1530 * @dev: PCI device to be disabled
1532 * Signal to the system that the PCI device is not in use by the system
1533 * anymore. This only involves disabling PCI bus-mastering, if active.
1535 * Note we don't actually disable the device until all callers of
1536 * pci_enable_device() have called pci_disable_device().
1538 void pci_disable_device(struct pci_dev
*dev
)
1540 struct pci_devres
*dr
;
1542 dr
= find_pci_dr(dev
);
1546 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1547 "disabling already-disabled device");
1549 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1552 do_pci_disable_device(dev
);
1554 dev
->is_busmaster
= 0;
1556 EXPORT_SYMBOL(pci_disable_device
);
1559 * pcibios_set_pcie_reset_state - set reset state for device dev
1560 * @dev: the PCIe device reset
1561 * @state: Reset state to enter into
1564 * Sets the PCIe reset state for the device. This is the default
1565 * implementation. Architecture implementations can override this.
1567 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1568 enum pcie_reset_state state
)
1574 * pci_set_pcie_reset_state - set reset state for device dev
1575 * @dev: the PCIe device reset
1576 * @state: Reset state to enter into
1579 * Sets the PCI reset state for the device.
1581 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1583 return pcibios_set_pcie_reset_state(dev
, state
);
1585 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
1588 * pci_check_pme_status - Check if given device has generated PME.
1589 * @dev: Device to check.
1591 * Check the PME status of the device and if set, clear it and clear PME enable
1592 * (if set). Return 'true' if PME status and PME enable were both set or
1593 * 'false' otherwise.
1595 bool pci_check_pme_status(struct pci_dev
*dev
)
1604 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1605 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1606 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1609 /* Clear PME status. */
1610 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1611 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1612 /* Disable PME to avoid interrupt flood. */
1613 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1617 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1623 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1624 * @dev: Device to handle.
1625 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1627 * Check if @dev has generated PME and queue a resume request for it in that
1630 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1632 if (pme_poll_reset
&& dev
->pme_poll
)
1633 dev
->pme_poll
= false;
1635 if (pci_check_pme_status(dev
)) {
1636 pci_wakeup_event(dev
);
1637 pm_request_resume(&dev
->dev
);
1643 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1644 * @bus: Top bus of the subtree to walk.
1646 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1649 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1654 * pci_pme_capable - check the capability of PCI device to generate PME#
1655 * @dev: PCI device to handle.
1656 * @state: PCI state from which device will issue PME#.
1658 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1663 return !!(dev
->pme_support
& (1 << state
));
1665 EXPORT_SYMBOL(pci_pme_capable
);
1667 static void pci_pme_list_scan(struct work_struct
*work
)
1669 struct pci_pme_device
*pme_dev
, *n
;
1671 mutex_lock(&pci_pme_list_mutex
);
1672 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1673 if (pme_dev
->dev
->pme_poll
) {
1674 struct pci_dev
*bridge
;
1676 bridge
= pme_dev
->dev
->bus
->self
;
1678 * If bridge is in low power state, the
1679 * configuration space of subordinate devices
1680 * may be not accessible
1682 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1684 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1686 list_del(&pme_dev
->list
);
1690 if (!list_empty(&pci_pme_list
))
1691 schedule_delayed_work(&pci_pme_work
,
1692 msecs_to_jiffies(PME_TIMEOUT
));
1693 mutex_unlock(&pci_pme_list_mutex
);
1697 * pci_pme_active - enable or disable PCI device's PME# function
1698 * @dev: PCI device to handle.
1699 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1701 * The caller must verify that the device is capable of generating PME# before
1702 * calling this function with @enable equal to 'true'.
1704 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1708 if (!dev
->pme_support
)
1711 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1712 /* Clear PME_Status by writing 1 to it and enable PME# */
1713 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1715 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1717 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1720 * PCI (as opposed to PCIe) PME requires that the device have
1721 * its PME# line hooked up correctly. Not all hardware vendors
1722 * do this, so the PME never gets delivered and the device
1723 * remains asleep. The easiest way around this is to
1724 * periodically walk the list of suspended devices and check
1725 * whether any have their PME flag set. The assumption is that
1726 * we'll wake up often enough anyway that this won't be a huge
1727 * hit, and the power savings from the devices will still be a
1730 * Although PCIe uses in-band PME message instead of PME# line
1731 * to report PME, PME does not work for some PCIe devices in
1732 * reality. For example, there are devices that set their PME
1733 * status bits, but don't really bother to send a PME message;
1734 * there are PCI Express Root Ports that don't bother to
1735 * trigger interrupts when they receive PME messages from the
1736 * devices below. So PME poll is used for PCIe devices too.
1739 if (dev
->pme_poll
) {
1740 struct pci_pme_device
*pme_dev
;
1742 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1745 dev_warn(&dev
->dev
, "can't enable PME#\n");
1749 mutex_lock(&pci_pme_list_mutex
);
1750 list_add(&pme_dev
->list
, &pci_pme_list
);
1751 if (list_is_singular(&pci_pme_list
))
1752 schedule_delayed_work(&pci_pme_work
,
1753 msecs_to_jiffies(PME_TIMEOUT
));
1754 mutex_unlock(&pci_pme_list_mutex
);
1756 mutex_lock(&pci_pme_list_mutex
);
1757 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1758 if (pme_dev
->dev
== dev
) {
1759 list_del(&pme_dev
->list
);
1764 mutex_unlock(&pci_pme_list_mutex
);
1768 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1770 EXPORT_SYMBOL(pci_pme_active
);
1773 * __pci_enable_wake - enable PCI device as wakeup event source
1774 * @dev: PCI device affected
1775 * @state: PCI state from which device will issue wakeup events
1776 * @runtime: True if the events are to be generated at run time
1777 * @enable: True to enable event generation; false to disable
1779 * This enables the device as a wakeup event source, or disables it.
1780 * When such events involves platform-specific hooks, those hooks are
1781 * called automatically by this routine.
1783 * Devices with legacy power management (no standard PCI PM capabilities)
1784 * always require such platform hooks.
1787 * 0 is returned on success
1788 * -EINVAL is returned if device is not supposed to wake up the system
1789 * Error code depending on the platform is returned if both the platform and
1790 * the native mechanism fail to enable the generation of wake-up events
1792 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1793 bool runtime
, bool enable
)
1797 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1800 /* Don't do the same thing twice in a row for one device. */
1801 if (!!enable
== !!dev
->wakeup_prepared
)
1805 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1806 * Anderson we should be doing PME# wake enable followed by ACPI wake
1807 * enable. To disable wake-up we call the platform first, for symmetry.
1813 if (pci_pme_capable(dev
, state
))
1814 pci_pme_active(dev
, true);
1817 error
= runtime
? platform_pci_run_wake(dev
, true) :
1818 platform_pci_sleep_wake(dev
, true);
1822 dev
->wakeup_prepared
= true;
1825 platform_pci_run_wake(dev
, false);
1827 platform_pci_sleep_wake(dev
, false);
1828 pci_pme_active(dev
, false);
1829 dev
->wakeup_prepared
= false;
1834 EXPORT_SYMBOL(__pci_enable_wake
);
1837 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1838 * @dev: PCI device to prepare
1839 * @enable: True to enable wake-up event generation; false to disable
1841 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1842 * and this function allows them to set that up cleanly - pci_enable_wake()
1843 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1844 * ordering constraints.
1846 * This function only returns error code if the device is not capable of
1847 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1848 * enable wake-up power for it.
1850 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1852 return pci_pme_capable(dev
, PCI_D3cold
) ?
1853 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1854 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1856 EXPORT_SYMBOL(pci_wake_from_d3
);
1859 * pci_target_state - find an appropriate low power state for a given PCI dev
1862 * Use underlying platform code to find a supported low power state for @dev.
1863 * If the platform can't manage @dev, return the deepest state from which it
1864 * can generate wake events, based on any available PME info.
1866 static pci_power_t
pci_target_state(struct pci_dev
*dev
)
1868 pci_power_t target_state
= PCI_D3hot
;
1870 if (platform_pci_power_manageable(dev
)) {
1872 * Call the platform to choose the target state of the device
1873 * and enable wake-up from this state if supported.
1875 pci_power_t state
= platform_pci_choose_state(dev
);
1878 case PCI_POWER_ERROR
:
1883 if (pci_no_d1d2(dev
))
1886 target_state
= state
;
1888 } else if (!dev
->pm_cap
) {
1889 target_state
= PCI_D0
;
1890 } else if (device_may_wakeup(&dev
->dev
)) {
1892 * Find the deepest state from which the device can generate
1893 * wake-up events, make it the target state and enable device
1896 if (dev
->pme_support
) {
1898 && !(dev
->pme_support
& (1 << target_state
)))
1903 return target_state
;
1907 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1908 * @dev: Device to handle.
1910 * Choose the power state appropriate for the device depending on whether
1911 * it can wake up the system and/or is power manageable by the platform
1912 * (PCI_D3hot is the default) and put the device into that state.
1914 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1916 pci_power_t target_state
= pci_target_state(dev
);
1919 if (target_state
== PCI_POWER_ERROR
)
1922 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1924 error
= pci_set_power_state(dev
, target_state
);
1927 pci_enable_wake(dev
, target_state
, false);
1931 EXPORT_SYMBOL(pci_prepare_to_sleep
);
1934 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1935 * @dev: Device to handle.
1937 * Disable device's system wake-up capability and put it into D0.
1939 int pci_back_from_sleep(struct pci_dev
*dev
)
1941 pci_enable_wake(dev
, PCI_D0
, false);
1942 return pci_set_power_state(dev
, PCI_D0
);
1944 EXPORT_SYMBOL(pci_back_from_sleep
);
1947 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1948 * @dev: PCI device being suspended.
1950 * Prepare @dev to generate wake-up events at run time and put it into a low
1953 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1955 pci_power_t target_state
= pci_target_state(dev
);
1958 if (target_state
== PCI_POWER_ERROR
)
1961 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
1963 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1965 error
= pci_set_power_state(dev
, target_state
);
1968 __pci_enable_wake(dev
, target_state
, true, false);
1969 dev
->runtime_d3cold
= false;
1976 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1977 * @dev: Device to check.
1979 * Return true if the device itself is capable of generating wake-up events
1980 * (through the platform or using the native PCIe PME) or if the device supports
1981 * PME and one of its upstream bridges can generate wake-up events.
1983 bool pci_dev_run_wake(struct pci_dev
*dev
)
1985 struct pci_bus
*bus
= dev
->bus
;
1987 if (device_run_wake(&dev
->dev
))
1990 if (!dev
->pme_support
)
1993 while (bus
->parent
) {
1994 struct pci_dev
*bridge
= bus
->self
;
1996 if (device_run_wake(&bridge
->dev
))
2002 /* We have reached the root bus. */
2004 return device_run_wake(bus
->bridge
);
2008 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2011 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2012 * @pci_dev: Device to check.
2014 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2015 * reconfigured due to wakeup settings difference between system and runtime
2016 * suspend and the current power state of it is suitable for the upcoming
2017 * (system) transition.
2019 bool pci_dev_keep_suspended(struct pci_dev
*pci_dev
)
2021 struct device
*dev
= &pci_dev
->dev
;
2023 if (!pm_runtime_suspended(dev
)
2024 || (device_can_wakeup(dev
) && !device_may_wakeup(dev
))
2025 || platform_pci_need_resume(pci_dev
))
2028 return pci_target_state(pci_dev
) == pci_dev
->current_state
;
2031 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2033 struct device
*dev
= &pdev
->dev
;
2034 struct device
*parent
= dev
->parent
;
2037 pm_runtime_get_sync(parent
);
2038 pm_runtime_get_noresume(dev
);
2040 * pdev->current_state is set to PCI_D3cold during suspending,
2041 * so wait until suspending completes
2043 pm_runtime_barrier(dev
);
2045 * Only need to resume devices in D3cold, because config
2046 * registers are still accessible for devices suspended but
2049 if (pdev
->current_state
== PCI_D3cold
)
2050 pm_runtime_resume(dev
);
2053 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2055 struct device
*dev
= &pdev
->dev
;
2056 struct device
*parent
= dev
->parent
;
2058 pm_runtime_put(dev
);
2060 pm_runtime_put_sync(parent
);
2064 * pci_pm_init - Initialize PM functions of given PCI device
2065 * @dev: PCI device to handle.
2067 void pci_pm_init(struct pci_dev
*dev
)
2072 pm_runtime_forbid(&dev
->dev
);
2073 pm_runtime_set_active(&dev
->dev
);
2074 pm_runtime_enable(&dev
->dev
);
2075 device_enable_async_suspend(&dev
->dev
);
2076 dev
->wakeup_prepared
= false;
2079 dev
->pme_support
= 0;
2081 /* find PCI PM capability in list */
2082 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2085 /* Check device's ability to generate PME# */
2086 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2088 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2089 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2090 pmc
& PCI_PM_CAP_VER_MASK
);
2095 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2096 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2097 dev
->d3cold_allowed
= true;
2099 dev
->d1_support
= false;
2100 dev
->d2_support
= false;
2101 if (!pci_no_d1d2(dev
)) {
2102 if (pmc
& PCI_PM_CAP_D1
)
2103 dev
->d1_support
= true;
2104 if (pmc
& PCI_PM_CAP_D2
)
2105 dev
->d2_support
= true;
2107 if (dev
->d1_support
|| dev
->d2_support
)
2108 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2109 dev
->d1_support
? " D1" : "",
2110 dev
->d2_support
? " D2" : "");
2113 pmc
&= PCI_PM_CAP_PME_MASK
;
2115 dev_printk(KERN_DEBUG
, &dev
->dev
,
2116 "PME# supported from%s%s%s%s%s\n",
2117 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2118 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2119 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2120 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2121 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2122 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2123 dev
->pme_poll
= true;
2125 * Make device's PM flags reflect the wake-up capability, but
2126 * let the user space enable it to wake up the system as needed.
2128 device_set_wakeup_capable(&dev
->dev
, true);
2129 /* Disable the PME# generation functionality */
2130 pci_pme_active(dev
, false);
2134 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2135 struct pci_cap_saved_state
*new_cap
)
2137 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2141 * _pci_add_cap_save_buffer - allocate buffer for saving given
2142 * capability registers
2143 * @dev: the PCI device
2144 * @cap: the capability to allocate the buffer for
2145 * @extended: Standard or Extended capability ID
2146 * @size: requested size of the buffer
2148 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2149 bool extended
, unsigned int size
)
2152 struct pci_cap_saved_state
*save_state
;
2155 pos
= pci_find_ext_capability(dev
, cap
);
2157 pos
= pci_find_capability(dev
, cap
);
2162 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2166 save_state
->cap
.cap_nr
= cap
;
2167 save_state
->cap
.cap_extended
= extended
;
2168 save_state
->cap
.size
= size
;
2169 pci_add_saved_cap(dev
, save_state
);
2174 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2176 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2179 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2181 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2185 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2186 * @dev: the PCI device
2188 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2192 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2193 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2196 "unable to preallocate PCI Express save buffer\n");
2198 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2201 "unable to preallocate PCI-X save buffer\n");
2203 pci_allocate_vc_save_buffers(dev
);
2206 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2208 struct pci_cap_saved_state
*tmp
;
2209 struct hlist_node
*n
;
2211 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2216 * pci_configure_ari - enable or disable ARI forwarding
2217 * @dev: the PCI device
2219 * If @dev and its upstream bridge both support ARI, enable ARI in the
2220 * bridge. Otherwise, disable ARI in the bridge.
2222 void pci_configure_ari(struct pci_dev
*dev
)
2225 struct pci_dev
*bridge
;
2227 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2230 bridge
= dev
->bus
->self
;
2234 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2235 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2238 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2239 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2240 PCI_EXP_DEVCTL2_ARI
);
2241 bridge
->ari_enabled
= 1;
2243 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2244 PCI_EXP_DEVCTL2_ARI
);
2245 bridge
->ari_enabled
= 0;
2249 static int pci_acs_enable
;
2252 * pci_request_acs - ask for ACS to be enabled if supported
2254 void pci_request_acs(void)
2260 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2261 * @dev: the PCI device
2263 static int pci_std_enable_acs(struct pci_dev
*dev
)
2269 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2273 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2274 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2276 /* Source Validation */
2277 ctrl
|= (cap
& PCI_ACS_SV
);
2279 /* P2P Request Redirect */
2280 ctrl
|= (cap
& PCI_ACS_RR
);
2282 /* P2P Completion Redirect */
2283 ctrl
|= (cap
& PCI_ACS_CR
);
2285 /* Upstream Forwarding */
2286 ctrl
|= (cap
& PCI_ACS_UF
);
2288 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2294 * pci_enable_acs - enable ACS if hardware support it
2295 * @dev: the PCI device
2297 void pci_enable_acs(struct pci_dev
*dev
)
2299 if (!pci_acs_enable
)
2302 if (!pci_std_enable_acs(dev
))
2305 pci_dev_specific_enable_acs(dev
);
2308 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2313 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2318 * Except for egress control, capabilities are either required
2319 * or only required if controllable. Features missing from the
2320 * capability field can therefore be assumed as hard-wired enabled.
2322 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2323 acs_flags
&= (cap
| PCI_ACS_EC
);
2325 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2326 return (ctrl
& acs_flags
) == acs_flags
;
2330 * pci_acs_enabled - test ACS against required flags for a given device
2331 * @pdev: device to test
2332 * @acs_flags: required PCI ACS flags
2334 * Return true if the device supports the provided flags. Automatically
2335 * filters out flags that are not implemented on multifunction devices.
2337 * Note that this interface checks the effective ACS capabilities of the
2338 * device rather than the actual capabilities. For instance, most single
2339 * function endpoints are not required to support ACS because they have no
2340 * opportunity for peer-to-peer access. We therefore return 'true'
2341 * regardless of whether the device exposes an ACS capability. This makes
2342 * it much easier for callers of this function to ignore the actual type
2343 * or topology of the device when testing ACS support.
2345 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2349 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2354 * Conventional PCI and PCI-X devices never support ACS, either
2355 * effectively or actually. The shared bus topology implies that
2356 * any device on the bus can receive or snoop DMA.
2358 if (!pci_is_pcie(pdev
))
2361 switch (pci_pcie_type(pdev
)) {
2363 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2364 * but since their primary interface is PCI/X, we conservatively
2365 * handle them as we would a non-PCIe device.
2367 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2369 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2370 * applicable... must never implement an ACS Extended Capability...".
2371 * This seems arbitrary, but we take a conservative interpretation
2372 * of this statement.
2374 case PCI_EXP_TYPE_PCI_BRIDGE
:
2375 case PCI_EXP_TYPE_RC_EC
:
2378 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2379 * implement ACS in order to indicate their peer-to-peer capabilities,
2380 * regardless of whether they are single- or multi-function devices.
2382 case PCI_EXP_TYPE_DOWNSTREAM
:
2383 case PCI_EXP_TYPE_ROOT_PORT
:
2384 return pci_acs_flags_enabled(pdev
, acs_flags
);
2386 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2387 * implemented by the remaining PCIe types to indicate peer-to-peer
2388 * capabilities, but only when they are part of a multifunction
2389 * device. The footnote for section 6.12 indicates the specific
2390 * PCIe types included here.
2392 case PCI_EXP_TYPE_ENDPOINT
:
2393 case PCI_EXP_TYPE_UPSTREAM
:
2394 case PCI_EXP_TYPE_LEG_END
:
2395 case PCI_EXP_TYPE_RC_END
:
2396 if (!pdev
->multifunction
)
2399 return pci_acs_flags_enabled(pdev
, acs_flags
);
2403 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2404 * to single function devices with the exception of downstream ports.
2410 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2411 * @start: starting downstream device
2412 * @end: ending upstream device or NULL to search to the root bus
2413 * @acs_flags: required flags
2415 * Walk up a device tree from start to end testing PCI ACS support. If
2416 * any step along the way does not support the required flags, return false.
2418 bool pci_acs_path_enabled(struct pci_dev
*start
,
2419 struct pci_dev
*end
, u16 acs_flags
)
2421 struct pci_dev
*pdev
, *parent
= start
;
2426 if (!pci_acs_enabled(pdev
, acs_flags
))
2429 if (pci_is_root_bus(pdev
->bus
))
2430 return (end
== NULL
);
2432 parent
= pdev
->bus
->self
;
2433 } while (pdev
!= end
);
2439 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2440 * @dev: the PCI device
2441 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2443 * Perform INTx swizzling for a device behind one level of bridge. This is
2444 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2445 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2446 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2447 * the PCI Express Base Specification, Revision 2.1)
2449 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
2453 if (pci_ari_enabled(dev
->bus
))
2456 slot
= PCI_SLOT(dev
->devfn
);
2458 return (((pin
- 1) + slot
) % 4) + 1;
2461 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2469 while (!pci_is_root_bus(dev
->bus
)) {
2470 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2471 dev
= dev
->bus
->self
;
2478 * pci_common_swizzle - swizzle INTx all the way to root bridge
2479 * @dev: the PCI device
2480 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2482 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2483 * bridges all the way up to a PCI root bus.
2485 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2489 while (!pci_is_root_bus(dev
->bus
)) {
2490 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2491 dev
= dev
->bus
->self
;
2494 return PCI_SLOT(dev
->devfn
);
2498 * pci_release_region - Release a PCI bar
2499 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2500 * @bar: BAR to release
2502 * Releases the PCI I/O and memory resources previously reserved by a
2503 * successful call to pci_request_region. Call this function only
2504 * after all use of the PCI regions has ceased.
2506 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2508 struct pci_devres
*dr
;
2510 if (pci_resource_len(pdev
, bar
) == 0)
2512 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2513 release_region(pci_resource_start(pdev
, bar
),
2514 pci_resource_len(pdev
, bar
));
2515 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2516 release_mem_region(pci_resource_start(pdev
, bar
),
2517 pci_resource_len(pdev
, bar
));
2519 dr
= find_pci_dr(pdev
);
2521 dr
->region_mask
&= ~(1 << bar
);
2523 EXPORT_SYMBOL(pci_release_region
);
2526 * __pci_request_region - Reserved PCI I/O and memory resource
2527 * @pdev: PCI device whose resources are to be reserved
2528 * @bar: BAR to be reserved
2529 * @res_name: Name to be associated with resource.
2530 * @exclusive: whether the region access is exclusive or not
2532 * Mark the PCI region associated with PCI device @pdev BR @bar as
2533 * being reserved by owner @res_name. Do not access any
2534 * address inside the PCI regions unless this call returns
2537 * If @exclusive is set, then the region is marked so that userspace
2538 * is explicitly not allowed to map the resource via /dev/mem or
2539 * sysfs MMIO access.
2541 * Returns 0 on success, or %EBUSY on error. A warning
2542 * message is also printed on failure.
2544 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
2545 const char *res_name
, int exclusive
)
2547 struct pci_devres
*dr
;
2549 if (pci_resource_len(pdev
, bar
) == 0)
2552 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2553 if (!request_region(pci_resource_start(pdev
, bar
),
2554 pci_resource_len(pdev
, bar
), res_name
))
2556 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2557 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2558 pci_resource_len(pdev
, bar
), res_name
,
2563 dr
= find_pci_dr(pdev
);
2565 dr
->region_mask
|= 1 << bar
;
2570 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2571 &pdev
->resource
[bar
]);
2576 * pci_request_region - Reserve PCI I/O and memory resource
2577 * @pdev: PCI device whose resources are to be reserved
2578 * @bar: BAR to be reserved
2579 * @res_name: Name to be associated with resource
2581 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2582 * being reserved by owner @res_name. Do not access any
2583 * address inside the PCI regions unless this call returns
2586 * Returns 0 on success, or %EBUSY on error. A warning
2587 * message is also printed on failure.
2589 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2591 return __pci_request_region(pdev
, bar
, res_name
, 0);
2593 EXPORT_SYMBOL(pci_request_region
);
2596 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2597 * @pdev: PCI device whose resources are to be reserved
2598 * @bar: BAR to be reserved
2599 * @res_name: Name to be associated with resource.
2601 * Mark the PCI region associated with PCI device @pdev BR @bar as
2602 * being reserved by owner @res_name. Do not access any
2603 * address inside the PCI regions unless this call returns
2606 * Returns 0 on success, or %EBUSY on error. A warning
2607 * message is also printed on failure.
2609 * The key difference that _exclusive makes it that userspace is
2610 * explicitly not allowed to map the resource via /dev/mem or
2613 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
,
2614 const char *res_name
)
2616 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2618 EXPORT_SYMBOL(pci_request_region_exclusive
);
2621 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2622 * @pdev: PCI device whose resources were previously reserved
2623 * @bars: Bitmask of BARs to be released
2625 * Release selected PCI I/O and memory resources previously reserved.
2626 * Call this function only after all use of the PCI regions has ceased.
2628 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2632 for (i
= 0; i
< 6; i
++)
2633 if (bars
& (1 << i
))
2634 pci_release_region(pdev
, i
);
2636 EXPORT_SYMBOL(pci_release_selected_regions
);
2638 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2639 const char *res_name
, int excl
)
2643 for (i
= 0; i
< 6; i
++)
2644 if (bars
& (1 << i
))
2645 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2651 if (bars
& (1 << i
))
2652 pci_release_region(pdev
, i
);
2659 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2660 * @pdev: PCI device whose resources are to be reserved
2661 * @bars: Bitmask of BARs to be requested
2662 * @res_name: Name to be associated with resource
2664 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2665 const char *res_name
)
2667 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2669 EXPORT_SYMBOL(pci_request_selected_regions
);
2671 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
2672 const char *res_name
)
2674 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2675 IORESOURCE_EXCLUSIVE
);
2677 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2680 * pci_release_regions - Release reserved PCI I/O and memory resources
2681 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2683 * Releases all PCI I/O and memory resources previously reserved by a
2684 * successful call to pci_request_regions. Call this function only
2685 * after all use of the PCI regions has ceased.
2688 void pci_release_regions(struct pci_dev
*pdev
)
2690 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2692 EXPORT_SYMBOL(pci_release_regions
);
2695 * pci_request_regions - Reserved PCI I/O and memory resources
2696 * @pdev: PCI device whose resources are to be reserved
2697 * @res_name: Name to be associated with resource.
2699 * Mark all PCI regions associated with PCI device @pdev as
2700 * being reserved by owner @res_name. Do not access any
2701 * address inside the PCI regions unless this call returns
2704 * Returns 0 on success, or %EBUSY on error. A warning
2705 * message is also printed on failure.
2707 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2709 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2711 EXPORT_SYMBOL(pci_request_regions
);
2714 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2715 * @pdev: PCI device whose resources are to be reserved
2716 * @res_name: Name to be associated with resource.
2718 * Mark all PCI regions associated with PCI device @pdev as
2719 * being reserved by owner @res_name. Do not access any
2720 * address inside the PCI regions unless this call returns
2723 * pci_request_regions_exclusive() will mark the region so that
2724 * /dev/mem and the sysfs MMIO access will not be allowed.
2726 * Returns 0 on success, or %EBUSY on error. A warning
2727 * message is also printed on failure.
2729 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2731 return pci_request_selected_regions_exclusive(pdev
,
2732 ((1 << 6) - 1), res_name
);
2734 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2737 * pci_remap_iospace - Remap the memory mapped I/O space
2738 * @res: Resource describing the I/O space
2739 * @phys_addr: physical address of range to be mapped
2741 * Remap the memory mapped I/O space described by the @res
2742 * and the CPU physical address @phys_addr into virtual address space.
2743 * Only architectures that have memory mapped IO functions defined
2744 * (and the PCI_IOBASE value defined) should call this function.
2746 int __weak
pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
2748 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
2749 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
2751 if (!(res
->flags
& IORESOURCE_IO
))
2754 if (res
->end
> IO_SPACE_LIMIT
)
2757 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
2758 pgprot_device(PAGE_KERNEL
));
2760 /* this architecture does not have memory mapped I/O space,
2761 so this function should never be called */
2762 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
2767 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2771 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2773 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2775 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2776 if (cmd
!= old_cmd
) {
2777 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2778 enable
? "enabling" : "disabling");
2779 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2781 dev
->is_busmaster
= enable
;
2785 * pcibios_setup - process "pci=" kernel boot arguments
2786 * @str: string used to pass in "pci=" kernel boot arguments
2788 * Process kernel boot arguments. This is the default implementation.
2789 * Architecture specific implementations can override this as necessary.
2791 char * __weak __init
pcibios_setup(char *str
)
2797 * pcibios_set_master - enable PCI bus-mastering for device dev
2798 * @dev: the PCI device to enable
2800 * Enables PCI bus-mastering for the device. This is the default
2801 * implementation. Architecture specific implementations can override
2802 * this if necessary.
2804 void __weak
pcibios_set_master(struct pci_dev
*dev
)
2808 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2809 if (pci_is_pcie(dev
))
2812 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
2814 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
2815 else if (lat
> pcibios_max_latency
)
2816 lat
= pcibios_max_latency
;
2820 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
2824 * pci_set_master - enables bus-mastering for device dev
2825 * @dev: the PCI device to enable
2827 * Enables bus-mastering on the device and calls pcibios_set_master()
2828 * to do the needed arch specific settings.
2830 void pci_set_master(struct pci_dev
*dev
)
2832 __pci_set_master(dev
, true);
2833 pcibios_set_master(dev
);
2835 EXPORT_SYMBOL(pci_set_master
);
2838 * pci_clear_master - disables bus-mastering for device dev
2839 * @dev: the PCI device to disable
2841 void pci_clear_master(struct pci_dev
*dev
)
2843 __pci_set_master(dev
, false);
2845 EXPORT_SYMBOL(pci_clear_master
);
2848 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2849 * @dev: the PCI device for which MWI is to be enabled
2851 * Helper function for pci_set_mwi.
2852 * Originally copied from drivers/net/acenic.c.
2853 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2855 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2857 int pci_set_cacheline_size(struct pci_dev
*dev
)
2861 if (!pci_cache_line_size
)
2864 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2865 equal to or multiple of the right value. */
2866 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2867 if (cacheline_size
>= pci_cache_line_size
&&
2868 (cacheline_size
% pci_cache_line_size
) == 0)
2871 /* Write the correct value. */
2872 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2874 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2875 if (cacheline_size
== pci_cache_line_size
)
2878 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not supported\n",
2879 pci_cache_line_size
<< 2);
2883 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2886 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2887 * @dev: the PCI device for which MWI is enabled
2889 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2891 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2893 int pci_set_mwi(struct pci_dev
*dev
)
2895 #ifdef PCI_DISABLE_MWI
2901 rc
= pci_set_cacheline_size(dev
);
2905 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2906 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
2907 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2908 cmd
|= PCI_COMMAND_INVALIDATE
;
2909 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2914 EXPORT_SYMBOL(pci_set_mwi
);
2917 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2918 * @dev: the PCI device for which MWI is enabled
2920 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2921 * Callers are not required to check the return value.
2923 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2925 int pci_try_set_mwi(struct pci_dev
*dev
)
2927 #ifdef PCI_DISABLE_MWI
2930 return pci_set_mwi(dev
);
2933 EXPORT_SYMBOL(pci_try_set_mwi
);
2936 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2937 * @dev: the PCI device to disable
2939 * Disables PCI Memory-Write-Invalidate transaction on the device
2941 void pci_clear_mwi(struct pci_dev
*dev
)
2943 #ifndef PCI_DISABLE_MWI
2946 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2947 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2948 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2949 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2953 EXPORT_SYMBOL(pci_clear_mwi
);
2956 * pci_intx - enables/disables PCI INTx for device dev
2957 * @pdev: the PCI device to operate on
2958 * @enable: boolean: whether to enable or disable PCI INTx
2960 * Enables/disables PCI INTx for device dev
2962 void pci_intx(struct pci_dev
*pdev
, int enable
)
2964 u16 pci_command
, new;
2966 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2969 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2971 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2973 if (new != pci_command
) {
2974 struct pci_devres
*dr
;
2976 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2978 dr
= find_pci_dr(pdev
);
2979 if (dr
&& !dr
->restore_intx
) {
2980 dr
->restore_intx
= 1;
2981 dr
->orig_intx
= !enable
;
2985 EXPORT_SYMBOL_GPL(pci_intx
);
2988 * pci_intx_mask_supported - probe for INTx masking support
2989 * @dev: the PCI device to operate on
2991 * Check if the device dev support INTx masking via the config space
2994 bool pci_intx_mask_supported(struct pci_dev
*dev
)
2996 bool mask_supported
= false;
2999 if (dev
->broken_intx_masking
)
3002 pci_cfg_access_lock(dev
);
3004 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
3005 pci_write_config_word(dev
, PCI_COMMAND
,
3006 orig
^ PCI_COMMAND_INTX_DISABLE
);
3007 pci_read_config_word(dev
, PCI_COMMAND
, &new);
3010 * There's no way to protect against hardware bugs or detect them
3011 * reliably, but as long as we know what the value should be, let's
3012 * go ahead and check it.
3014 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
3015 dev_err(&dev
->dev
, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3017 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
3018 mask_supported
= true;
3019 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
3022 pci_cfg_access_unlock(dev
);
3023 return mask_supported
;
3025 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
3027 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3029 struct pci_bus
*bus
= dev
->bus
;
3030 bool mask_updated
= true;
3031 u32 cmd_status_dword
;
3032 u16 origcmd
, newcmd
;
3033 unsigned long flags
;
3037 * We do a single dword read to retrieve both command and status.
3038 * Document assumptions that make this possible.
3040 BUILD_BUG_ON(PCI_COMMAND
% 4);
3041 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3043 raw_spin_lock_irqsave(&pci_lock
, flags
);
3045 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3047 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3050 * Check interrupt status register to see whether our device
3051 * triggered the interrupt (when masking) or the next IRQ is
3052 * already pending (when unmasking).
3054 if (mask
!= irq_pending
) {
3055 mask_updated
= false;
3059 origcmd
= cmd_status_dword
;
3060 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3062 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3063 if (newcmd
!= origcmd
)
3064 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3067 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3069 return mask_updated
;
3073 * pci_check_and_mask_intx - mask INTx on pending interrupt
3074 * @dev: the PCI device to operate on
3076 * Check if the device dev has its INTx line asserted, mask it and
3077 * return true in that case. False is returned if not interrupt was
3080 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3082 return pci_check_and_set_intx_mask(dev
, true);
3084 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3087 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3088 * @dev: the PCI device to operate on
3090 * Check if the device dev has its INTx line asserted, unmask it if not
3091 * and return true. False is returned and the mask remains active if
3092 * there was still an interrupt pending.
3094 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3096 return pci_check_and_set_intx_mask(dev
, false);
3098 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3101 * pci_msi_off - disables any MSI or MSI-X capabilities
3102 * @dev: the PCI device to operate on
3104 * If you want to use MSI, see pci_enable_msi() and friends.
3105 * This is a lower-level primitive that allows us to disable
3106 * MSI operation at the device level.
3108 void pci_msi_off(struct pci_dev
*dev
)
3114 * This looks like it could go in msi.c, but we need it even when
3115 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3116 * dev->msi_cap or dev->msix_cap here.
3118 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
3120 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
3121 control
&= ~PCI_MSI_FLAGS_ENABLE
;
3122 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
3124 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
3126 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
3127 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
3128 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
3131 EXPORT_SYMBOL_GPL(pci_msi_off
);
3133 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
3135 return dma_set_max_seg_size(&dev
->dev
, size
);
3137 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
3139 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
3141 return dma_set_seg_boundary(&dev
->dev
, mask
);
3143 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
3146 * pci_wait_for_pending_transaction - waits for pending transaction
3147 * @dev: the PCI device to operate on
3149 * Return 0 if transaction is pending 1 otherwise.
3151 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3153 if (!pci_is_pcie(dev
))
3156 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
3157 PCI_EXP_DEVSTA_TRPND
);
3159 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3161 static int pcie_flr(struct pci_dev
*dev
, int probe
)
3165 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
3166 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3172 if (!pci_wait_for_pending_transaction(dev
))
3173 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
3175 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3180 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3185 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3189 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3190 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3197 * Wait for Transaction Pending bit to clear. A word-aligned test
3198 * is used, so we use the conrol offset rather than status and shift
3199 * the test bit to match.
3201 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
3202 PCI_AF_STATUS_TP
<< 8))
3203 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3205 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3211 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3212 * @dev: Device to reset.
3213 * @probe: If set, only check if the device can be reset this way.
3215 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3216 * unset, it will be reinitialized internally when going from PCI_D3hot to
3217 * PCI_D0. If that's the case and the device is not in a low-power state
3218 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3220 * NOTE: This causes the caller to sleep for twice the device power transition
3221 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3222 * by default (i.e. unless the @dev's d3_delay field has a different value).
3223 * Moreover, only devices in D0 can be reset by this function.
3225 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3229 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
3232 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3233 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3239 if (dev
->current_state
!= PCI_D0
)
3242 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3244 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3245 pci_dev_d3_sleep(dev
);
3247 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3249 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3250 pci_dev_d3_sleep(dev
);
3255 void pci_reset_secondary_bus(struct pci_dev
*dev
)
3259 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
3260 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3261 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3263 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3264 * this to 2ms to ensure that we meet the minimum requirement.
3268 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3269 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3272 * Trhfa for conventional PCI is 2^25 clock cycles.
3273 * Assuming a minimum 33MHz clock this results in a 1s
3274 * delay before we can consider subordinate devices to
3275 * be re-initialized. PCIe has some ways to shorten this,
3276 * but we don't make use of them yet.
3281 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
3283 pci_reset_secondary_bus(dev
);
3287 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3288 * @dev: Bridge device
3290 * Use the bridge control register to assert reset on the secondary bus.
3291 * Devices on the secondary bus are left in power-on state.
3293 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
3295 pcibios_reset_secondary_bus(dev
);
3297 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
3299 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3301 struct pci_dev
*pdev
;
3303 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
3304 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
3307 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3314 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
3319 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
3323 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
3326 if (hotplug
->ops
->reset_slot
)
3327 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
3329 module_put(hotplug
->ops
->owner
);
3334 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
3336 struct pci_dev
*pdev
;
3338 if (dev
->subordinate
|| !dev
->slot
||
3339 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
3342 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3343 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
3346 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
3349 static int __pci_dev_reset(struct pci_dev
*dev
, int probe
)
3355 rc
= pci_dev_specific_reset(dev
, probe
);
3359 rc
= pcie_flr(dev
, probe
);
3363 rc
= pci_af_flr(dev
, probe
);
3367 rc
= pci_pm_reset(dev
, probe
);
3371 rc
= pci_dev_reset_slot_function(dev
, probe
);
3375 rc
= pci_parent_bus_reset(dev
, probe
);
3380 static void pci_dev_lock(struct pci_dev
*dev
)
3382 pci_cfg_access_lock(dev
);
3383 /* block PM suspend, driver probe, etc. */
3384 device_lock(&dev
->dev
);
3387 /* Return 1 on successful lock, 0 on contention */
3388 static int pci_dev_trylock(struct pci_dev
*dev
)
3390 if (pci_cfg_access_trylock(dev
)) {
3391 if (device_trylock(&dev
->dev
))
3393 pci_cfg_access_unlock(dev
);
3399 static void pci_dev_unlock(struct pci_dev
*dev
)
3401 device_unlock(&dev
->dev
);
3402 pci_cfg_access_unlock(dev
);
3406 * pci_reset_notify - notify device driver of reset
3407 * @dev: device to be notified of reset
3408 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3411 * Must be called prior to device access being disabled and after device
3412 * access is restored.
3414 static void pci_reset_notify(struct pci_dev
*dev
, bool prepare
)
3416 const struct pci_error_handlers
*err_handler
=
3417 dev
->driver
? dev
->driver
->err_handler
: NULL
;
3418 if (err_handler
&& err_handler
->reset_notify
)
3419 err_handler
->reset_notify(dev
, prepare
);
3422 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
3424 pci_reset_notify(dev
, true);
3427 * Wake-up device prior to save. PM registers default to D0 after
3428 * reset and a simple register restore doesn't reliably return
3429 * to a non-D0 state anyway.
3431 pci_set_power_state(dev
, PCI_D0
);
3433 pci_save_state(dev
);
3435 * Disable the device by clearing the Command register, except for
3436 * INTx-disable which is set. This not only disables MMIO and I/O port
3437 * BARs, but also prevents the device from being Bus Master, preventing
3438 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3439 * compliant devices, INTx-disable prevents legacy interrupts.
3441 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3444 static void pci_dev_restore(struct pci_dev
*dev
)
3446 pci_restore_state(dev
);
3447 pci_reset_notify(dev
, false);
3450 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3457 rc
= __pci_dev_reset(dev
, probe
);
3460 pci_dev_unlock(dev
);
3466 * __pci_reset_function - reset a PCI device function
3467 * @dev: PCI device to reset
3469 * Some devices allow an individual function to be reset without affecting
3470 * other functions in the same device. The PCI device must be responsive
3471 * to PCI config space in order to use this function.
3473 * The device function is presumed to be unused when this function is called.
3474 * Resetting the device will make the contents of PCI configuration space
3475 * random, so any caller of this must be prepared to reinitialise the
3476 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3479 * Returns 0 if the device function was successfully reset or negative if the
3480 * device doesn't support resetting a single function.
3482 int __pci_reset_function(struct pci_dev
*dev
)
3484 return pci_dev_reset(dev
, 0);
3486 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3489 * __pci_reset_function_locked - reset a PCI device function while holding
3490 * the @dev mutex lock.
3491 * @dev: PCI device to reset
3493 * Some devices allow an individual function to be reset without affecting
3494 * other functions in the same device. The PCI device must be responsive
3495 * to PCI config space in order to use this function.
3497 * The device function is presumed to be unused and the caller is holding
3498 * the device mutex lock when this function is called.
3499 * Resetting the device will make the contents of PCI configuration space
3500 * random, so any caller of this must be prepared to reinitialise the
3501 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3504 * Returns 0 if the device function was successfully reset or negative if the
3505 * device doesn't support resetting a single function.
3507 int __pci_reset_function_locked(struct pci_dev
*dev
)
3509 return __pci_dev_reset(dev
, 0);
3511 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3514 * pci_probe_reset_function - check whether the device can be safely reset
3515 * @dev: PCI device to reset
3517 * Some devices allow an individual function to be reset without affecting
3518 * other functions in the same device. The PCI device must be responsive
3519 * to PCI config space in order to use this function.
3521 * Returns 0 if the device function can be reset or negative if the
3522 * device doesn't support resetting a single function.
3524 int pci_probe_reset_function(struct pci_dev
*dev
)
3526 return pci_dev_reset(dev
, 1);
3530 * pci_reset_function - quiesce and reset a PCI device function
3531 * @dev: PCI device to reset
3533 * Some devices allow an individual function to be reset without affecting
3534 * other functions in the same device. The PCI device must be responsive
3535 * to PCI config space in order to use this function.
3537 * This function does not just reset the PCI portion of a device, but
3538 * clears all the state associated with the device. This function differs
3539 * from __pci_reset_function in that it saves and restores device state
3542 * Returns 0 if the device function was successfully reset or negative if the
3543 * device doesn't support resetting a single function.
3545 int pci_reset_function(struct pci_dev
*dev
)
3549 rc
= pci_dev_reset(dev
, 1);
3553 pci_dev_save_and_disable(dev
);
3555 rc
= pci_dev_reset(dev
, 0);
3557 pci_dev_restore(dev
);
3561 EXPORT_SYMBOL_GPL(pci_reset_function
);
3564 * pci_try_reset_function - quiesce and reset a PCI device function
3565 * @dev: PCI device to reset
3567 * Same as above, except return -EAGAIN if unable to lock device.
3569 int pci_try_reset_function(struct pci_dev
*dev
)
3573 rc
= pci_dev_reset(dev
, 1);
3577 pci_dev_save_and_disable(dev
);
3579 if (pci_dev_trylock(dev
)) {
3580 rc
= __pci_dev_reset(dev
, 0);
3581 pci_dev_unlock(dev
);
3585 pci_dev_restore(dev
);
3589 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
3591 /* Do any devices on or below this bus prevent a bus reset? */
3592 static bool pci_bus_resetable(struct pci_bus
*bus
)
3594 struct pci_dev
*dev
;
3596 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3597 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
3598 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
3605 /* Lock devices from the top of the tree down */
3606 static void pci_bus_lock(struct pci_bus
*bus
)
3608 struct pci_dev
*dev
;
3610 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3612 if (dev
->subordinate
)
3613 pci_bus_lock(dev
->subordinate
);
3617 /* Unlock devices from the bottom of the tree up */
3618 static void pci_bus_unlock(struct pci_bus
*bus
)
3620 struct pci_dev
*dev
;
3622 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3623 if (dev
->subordinate
)
3624 pci_bus_unlock(dev
->subordinate
);
3625 pci_dev_unlock(dev
);
3629 /* Return 1 on successful lock, 0 on contention */
3630 static int pci_bus_trylock(struct pci_bus
*bus
)
3632 struct pci_dev
*dev
;
3634 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3635 if (!pci_dev_trylock(dev
))
3637 if (dev
->subordinate
) {
3638 if (!pci_bus_trylock(dev
->subordinate
)) {
3639 pci_dev_unlock(dev
);
3647 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
3648 if (dev
->subordinate
)
3649 pci_bus_unlock(dev
->subordinate
);
3650 pci_dev_unlock(dev
);
3655 /* Do any devices on or below this slot prevent a bus reset? */
3656 static bool pci_slot_resetable(struct pci_slot
*slot
)
3658 struct pci_dev
*dev
;
3660 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3661 if (!dev
->slot
|| dev
->slot
!= slot
)
3663 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
3664 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
3671 /* Lock devices from the top of the tree down */
3672 static void pci_slot_lock(struct pci_slot
*slot
)
3674 struct pci_dev
*dev
;
3676 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3677 if (!dev
->slot
|| dev
->slot
!= slot
)
3680 if (dev
->subordinate
)
3681 pci_bus_lock(dev
->subordinate
);
3685 /* Unlock devices from the bottom of the tree up */
3686 static void pci_slot_unlock(struct pci_slot
*slot
)
3688 struct pci_dev
*dev
;
3690 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3691 if (!dev
->slot
|| dev
->slot
!= slot
)
3693 if (dev
->subordinate
)
3694 pci_bus_unlock(dev
->subordinate
);
3695 pci_dev_unlock(dev
);
3699 /* Return 1 on successful lock, 0 on contention */
3700 static int pci_slot_trylock(struct pci_slot
*slot
)
3702 struct pci_dev
*dev
;
3704 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3705 if (!dev
->slot
|| dev
->slot
!= slot
)
3707 if (!pci_dev_trylock(dev
))
3709 if (dev
->subordinate
) {
3710 if (!pci_bus_trylock(dev
->subordinate
)) {
3711 pci_dev_unlock(dev
);
3719 list_for_each_entry_continue_reverse(dev
,
3720 &slot
->bus
->devices
, bus_list
) {
3721 if (!dev
->slot
|| dev
->slot
!= slot
)
3723 if (dev
->subordinate
)
3724 pci_bus_unlock(dev
->subordinate
);
3725 pci_dev_unlock(dev
);
3730 /* Save and disable devices from the top of the tree down */
3731 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
3733 struct pci_dev
*dev
;
3735 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3736 pci_dev_save_and_disable(dev
);
3737 if (dev
->subordinate
)
3738 pci_bus_save_and_disable(dev
->subordinate
);
3743 * Restore devices from top of the tree down - parent bridges need to be
3744 * restored before we can get to subordinate devices.
3746 static void pci_bus_restore(struct pci_bus
*bus
)
3748 struct pci_dev
*dev
;
3750 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3751 pci_dev_restore(dev
);
3752 if (dev
->subordinate
)
3753 pci_bus_restore(dev
->subordinate
);
3757 /* Save and disable devices from the top of the tree down */
3758 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
3760 struct pci_dev
*dev
;
3762 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3763 if (!dev
->slot
|| dev
->slot
!= slot
)
3765 pci_dev_save_and_disable(dev
);
3766 if (dev
->subordinate
)
3767 pci_bus_save_and_disable(dev
->subordinate
);
3772 * Restore devices from top of the tree down - parent bridges need to be
3773 * restored before we can get to subordinate devices.
3775 static void pci_slot_restore(struct pci_slot
*slot
)
3777 struct pci_dev
*dev
;
3779 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3780 if (!dev
->slot
|| dev
->slot
!= slot
)
3782 pci_dev_restore(dev
);
3783 if (dev
->subordinate
)
3784 pci_bus_restore(dev
->subordinate
);
3788 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
3792 if (!slot
|| !pci_slot_resetable(slot
))
3796 pci_slot_lock(slot
);
3800 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
3803 pci_slot_unlock(slot
);
3809 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3810 * @slot: PCI slot to probe
3812 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3814 int pci_probe_reset_slot(struct pci_slot
*slot
)
3816 return pci_slot_reset(slot
, 1);
3818 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
3821 * pci_reset_slot - reset a PCI slot
3822 * @slot: PCI slot to reset
3824 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3825 * independent of other slots. For instance, some slots may support slot power
3826 * control. In the case of a 1:1 bus to slot architecture, this function may
3827 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3828 * Generally a slot reset should be attempted before a bus reset. All of the
3829 * function of the slot and any subordinate buses behind the slot are reset
3830 * through this function. PCI config space of all devices in the slot and
3831 * behind the slot is saved before and restored after reset.
3833 * Return 0 on success, non-zero on error.
3835 int pci_reset_slot(struct pci_slot
*slot
)
3839 rc
= pci_slot_reset(slot
, 1);
3843 pci_slot_save_and_disable(slot
);
3845 rc
= pci_slot_reset(slot
, 0);
3847 pci_slot_restore(slot
);
3851 EXPORT_SYMBOL_GPL(pci_reset_slot
);
3854 * pci_try_reset_slot - Try to reset a PCI slot
3855 * @slot: PCI slot to reset
3857 * Same as above except return -EAGAIN if the slot cannot be locked
3859 int pci_try_reset_slot(struct pci_slot
*slot
)
3863 rc
= pci_slot_reset(slot
, 1);
3867 pci_slot_save_and_disable(slot
);
3869 if (pci_slot_trylock(slot
)) {
3871 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
3872 pci_slot_unlock(slot
);
3876 pci_slot_restore(slot
);
3880 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
3882 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
3884 if (!bus
->self
|| !pci_bus_resetable(bus
))
3894 pci_reset_bridge_secondary_bus(bus
->self
);
3896 pci_bus_unlock(bus
);
3902 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3903 * @bus: PCI bus to probe
3905 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3907 int pci_probe_reset_bus(struct pci_bus
*bus
)
3909 return pci_bus_reset(bus
, 1);
3911 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
3914 * pci_reset_bus - reset a PCI bus
3915 * @bus: top level PCI bus to reset
3917 * Do a bus reset on the given bus and any subordinate buses, saving
3918 * and restoring state of all devices.
3920 * Return 0 on success, non-zero on error.
3922 int pci_reset_bus(struct pci_bus
*bus
)
3926 rc
= pci_bus_reset(bus
, 1);
3930 pci_bus_save_and_disable(bus
);
3932 rc
= pci_bus_reset(bus
, 0);
3934 pci_bus_restore(bus
);
3938 EXPORT_SYMBOL_GPL(pci_reset_bus
);
3941 * pci_try_reset_bus - Try to reset a PCI bus
3942 * @bus: top level PCI bus to reset
3944 * Same as above except return -EAGAIN if the bus cannot be locked
3946 int pci_try_reset_bus(struct pci_bus
*bus
)
3950 rc
= pci_bus_reset(bus
, 1);
3954 pci_bus_save_and_disable(bus
);
3956 if (pci_bus_trylock(bus
)) {
3958 pci_reset_bridge_secondary_bus(bus
->self
);
3959 pci_bus_unlock(bus
);
3963 pci_bus_restore(bus
);
3967 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
3970 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3971 * @dev: PCI device to query
3973 * Returns mmrbc: maximum designed memory read count in bytes
3974 * or appropriate error value.
3976 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
3981 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3985 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3988 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
3990 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
3993 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3994 * @dev: PCI device to query
3996 * Returns mmrbc: maximum memory read count in bytes
3997 * or appropriate error value.
3999 int pcix_get_mmrbc(struct pci_dev
*dev
)
4004 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4008 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4011 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
4013 EXPORT_SYMBOL(pcix_get_mmrbc
);
4016 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4017 * @dev: PCI device to query
4018 * @mmrbc: maximum memory read count in bytes
4019 * valid values are 512, 1024, 2048, 4096
4021 * If possible sets maximum memory read byte count, some bridges have erratas
4022 * that prevent this.
4024 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
4030 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
4033 v
= ffs(mmrbc
) - 10;
4035 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4039 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4042 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
4045 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4048 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
4050 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
4053 cmd
&= ~PCI_X_CMD_MAX_READ
;
4055 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
4060 EXPORT_SYMBOL(pcix_set_mmrbc
);
4063 * pcie_get_readrq - get PCI Express read request size
4064 * @dev: PCI device to query
4066 * Returns maximum memory read request in bytes
4067 * or appropriate error value.
4069 int pcie_get_readrq(struct pci_dev
*dev
)
4073 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4075 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
4077 EXPORT_SYMBOL(pcie_get_readrq
);
4080 * pcie_set_readrq - set PCI Express maximum memory read request
4081 * @dev: PCI device to query
4082 * @rq: maximum memory read count in bytes
4083 * valid values are 128, 256, 512, 1024, 2048, 4096
4085 * If possible sets maximum memory read request in bytes
4087 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
4091 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
4095 * If using the "performance" PCIe config, we clamp the
4096 * read rq size to the max packet size to prevent the
4097 * host bridge generating requests larger than we can
4100 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
4101 int mps
= pcie_get_mps(dev
);
4107 v
= (ffs(rq
) - 8) << 12;
4109 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4110 PCI_EXP_DEVCTL_READRQ
, v
);
4112 EXPORT_SYMBOL(pcie_set_readrq
);
4115 * pcie_get_mps - get PCI Express maximum payload size
4116 * @dev: PCI device to query
4118 * Returns maximum payload size in bytes
4120 int pcie_get_mps(struct pci_dev
*dev
)
4124 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4126 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
4128 EXPORT_SYMBOL(pcie_get_mps
);
4131 * pcie_set_mps - set PCI Express maximum payload size
4132 * @dev: PCI device to query
4133 * @mps: maximum payload size in bytes
4134 * valid values are 128, 256, 512, 1024, 2048, 4096
4136 * If possible sets maximum payload size
4138 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
4142 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
4146 if (v
> dev
->pcie_mpss
)
4150 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4151 PCI_EXP_DEVCTL_PAYLOAD
, v
);
4153 EXPORT_SYMBOL(pcie_set_mps
);
4156 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4157 * @dev: PCI device to query
4158 * @speed: storage for minimum speed
4159 * @width: storage for minimum width
4161 * This function will walk up the PCI device chain and determine the minimum
4162 * link width and speed of the device.
4164 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
4165 enum pcie_link_width
*width
)
4169 *speed
= PCI_SPEED_UNKNOWN
;
4170 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
4174 enum pci_bus_speed next_speed
;
4175 enum pcie_link_width next_width
;
4177 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
4181 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
4182 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
4183 PCI_EXP_LNKSTA_NLW_SHIFT
;
4185 if (next_speed
< *speed
)
4186 *speed
= next_speed
;
4188 if (next_width
< *width
)
4189 *width
= next_width
;
4191 dev
= dev
->bus
->self
;
4196 EXPORT_SYMBOL(pcie_get_minimum_link
);
4199 * pci_select_bars - Make BAR mask from the type of resource
4200 * @dev: the PCI device for which BAR mask is made
4201 * @flags: resource type mask to be selected
4203 * This helper routine makes bar mask from the type of resource.
4205 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
4208 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
4209 if (pci_resource_flags(dev
, i
) & flags
)
4213 EXPORT_SYMBOL(pci_select_bars
);
4216 * pci_resource_bar - get position of the BAR associated with a resource
4217 * @dev: the PCI device
4218 * @resno: the resource number
4219 * @type: the BAR type to be filled in
4221 * Returns BAR position in config space, or 0 if the BAR is invalid.
4223 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
4227 if (resno
< PCI_ROM_RESOURCE
) {
4228 *type
= pci_bar_unknown
;
4229 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
4230 } else if (resno
== PCI_ROM_RESOURCE
) {
4231 *type
= pci_bar_mem32
;
4232 return dev
->rom_base_reg
;
4233 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
4234 /* device specific resource */
4235 *type
= pci_bar_unknown
;
4236 reg
= pci_iov_resource_bar(dev
, resno
);
4241 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
4245 /* Some architectures require additional programming to enable VGA */
4246 static arch_set_vga_state_t arch_set_vga_state
;
4248 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
4250 arch_set_vga_state
= func
; /* NULL disables */
4253 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
4254 unsigned int command_bits
, u32 flags
)
4256 if (arch_set_vga_state
)
4257 return arch_set_vga_state(dev
, decode
, command_bits
,
4263 * pci_set_vga_state - set VGA decode state on device and parents if requested
4264 * @dev: the PCI device
4265 * @decode: true = enable decoding, false = disable decoding
4266 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4267 * @flags: traverse ancestors and change bridges
4268 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4270 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
4271 unsigned int command_bits
, u32 flags
)
4273 struct pci_bus
*bus
;
4274 struct pci_dev
*bridge
;
4278 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
4280 /* ARCH specific VGA enables */
4281 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
4285 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
4286 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4288 cmd
|= command_bits
;
4290 cmd
&= ~command_bits
;
4291 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4294 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
4301 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4304 cmd
|= PCI_BRIDGE_CTL_VGA
;
4306 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
4307 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4315 bool pci_device_is_present(struct pci_dev
*pdev
)
4319 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
4321 EXPORT_SYMBOL_GPL(pci_device_is_present
);
4323 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4324 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
4325 static DEFINE_SPINLOCK(resource_alignment_lock
);
4328 * pci_specified_resource_alignment - get resource alignment specified by user.
4329 * @dev: the PCI device to get
4331 * RETURNS: Resource alignment if it is specified.
4332 * Zero if it is not specified.
4334 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
4336 int seg
, bus
, slot
, func
, align_order
, count
;
4337 resource_size_t align
= 0;
4340 spin_lock(&resource_alignment_lock
);
4341 p
= resource_alignment_param
;
4344 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
4350 if (sscanf(p
, "%x:%x:%x.%x%n",
4351 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
4353 if (sscanf(p
, "%x:%x.%x%n",
4354 &bus
, &slot
, &func
, &count
) != 3) {
4355 /* Invalid format */
4356 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
4362 if (seg
== pci_domain_nr(dev
->bus
) &&
4363 bus
== dev
->bus
->number
&&
4364 slot
== PCI_SLOT(dev
->devfn
) &&
4365 func
== PCI_FUNC(dev
->devfn
)) {
4366 if (align_order
== -1)
4369 align
= 1 << align_order
;
4373 if (*p
!= ';' && *p
!= ',') {
4374 /* End of param or invalid format */
4379 spin_unlock(&resource_alignment_lock
);
4384 * This function disables memory decoding and releases memory resources
4385 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4386 * It also rounds up size to specified alignment.
4387 * Later on, the kernel will assign page-aligned memory resource back
4390 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
4394 resource_size_t align
, size
;
4397 /* check if specified PCI is target device to reassign */
4398 align
= pci_specified_resource_alignment(dev
);
4402 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
4403 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
4405 "Can't reassign resources to host bridge.\n");
4410 "Disabling memory decoding and releasing memory resources.\n");
4411 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
4412 command
&= ~PCI_COMMAND_MEMORY
;
4413 pci_write_config_word(dev
, PCI_COMMAND
, command
);
4415 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
4416 r
= &dev
->resource
[i
];
4417 if (!(r
->flags
& IORESOURCE_MEM
))
4419 size
= resource_size(r
);
4423 "Rounding up size of resource #%d to %#llx.\n",
4424 i
, (unsigned long long)size
);
4426 r
->flags
|= IORESOURCE_UNSET
;
4430 /* Need to disable bridge's resource window,
4431 * to enable the kernel to reassign new resource
4434 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
4435 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
4436 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
4437 r
= &dev
->resource
[i
];
4438 if (!(r
->flags
& IORESOURCE_MEM
))
4440 r
->flags
|= IORESOURCE_UNSET
;
4441 r
->end
= resource_size(r
) - 1;
4444 pci_disable_bridge_window(dev
);
4448 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
4450 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
4451 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
4452 spin_lock(&resource_alignment_lock
);
4453 strncpy(resource_alignment_param
, buf
, count
);
4454 resource_alignment_param
[count
] = '\0';
4455 spin_unlock(&resource_alignment_lock
);
4459 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
4462 spin_lock(&resource_alignment_lock
);
4463 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
4464 spin_unlock(&resource_alignment_lock
);
4468 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
4470 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
4473 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
4474 const char *buf
, size_t count
)
4476 return pci_set_resource_alignment_param(buf
, count
);
4479 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
4480 pci_resource_alignment_store
);
4482 static int __init
pci_resource_alignment_sysfs_init(void)
4484 return bus_create_file(&pci_bus_type
,
4485 &bus_attr_resource_alignment
);
4487 late_initcall(pci_resource_alignment_sysfs_init
);
4489 static void pci_no_domains(void)
4491 #ifdef CONFIG_PCI_DOMAINS
4492 pci_domains_supported
= 0;
4496 #ifdef CONFIG_PCI_DOMAINS
4497 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
4499 int pci_get_new_domain_nr(void)
4501 return atomic_inc_return(&__domain_nr
);
4504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
4505 void pci_bus_assign_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
4507 static int use_dt_domains
= -1;
4508 int domain
= of_get_pci_domain_nr(parent
->of_node
);
4511 * Check DT domain and use_dt_domains values.
4513 * If DT domain property is valid (domain >= 0) and
4514 * use_dt_domains != 0, the DT assignment is valid since this means
4515 * we have not previously allocated a domain number by using
4516 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4517 * 1, to indicate that we have just assigned a domain number from
4520 * If DT domain property value is not valid (ie domain < 0), and we
4521 * have not previously assigned a domain number from DT
4522 * (use_dt_domains != 1) we should assign a domain number by
4525 * pci_get_new_domain_nr()
4527 * API and update the use_dt_domains value to keep track of method we
4528 * are using to assign domain numbers (use_dt_domains = 0).
4530 * All other combinations imply we have a platform that is trying
4531 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4532 * which is a recipe for domain mishandling and it is prevented by
4533 * invalidating the domain value (domain = -1) and printing a
4534 * corresponding error.
4536 if (domain
>= 0 && use_dt_domains
) {
4538 } else if (domain
< 0 && use_dt_domains
!= 1) {
4540 domain
= pci_get_new_domain_nr();
4542 dev_err(parent
, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4543 parent
->of_node
->full_name
);
4547 bus
->domain_nr
= domain
;
4553 * pci_ext_cfg_avail - can we access extended PCI config space?
4555 * Returns 1 if we can access PCI extended config space (offsets
4556 * greater than 0xff). This is the default implementation. Architecture
4557 * implementations can override this.
4559 int __weak
pci_ext_cfg_avail(void)
4564 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
4567 EXPORT_SYMBOL(pci_fixup_cardbus
);
4569 static int __init
pci_setup(char *str
)
4572 char *k
= strchr(str
, ',');
4575 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
4576 if (!strcmp(str
, "nomsi")) {
4578 } else if (!strcmp(str
, "noaer")) {
4580 } else if (!strncmp(str
, "realloc=", 8)) {
4581 pci_realloc_get_opt(str
+ 8);
4582 } else if (!strncmp(str
, "realloc", 7)) {
4583 pci_realloc_get_opt("on");
4584 } else if (!strcmp(str
, "nodomains")) {
4586 } else if (!strncmp(str
, "noari", 5)) {
4587 pcie_ari_disabled
= true;
4588 } else if (!strncmp(str
, "cbiosize=", 9)) {
4589 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
4590 } else if (!strncmp(str
, "cbmemsize=", 10)) {
4591 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
4592 } else if (!strncmp(str
, "resource_alignment=", 19)) {
4593 pci_set_resource_alignment_param(str
+ 19,
4595 } else if (!strncmp(str
, "ecrc=", 5)) {
4596 pcie_ecrc_get_policy(str
+ 5);
4597 } else if (!strncmp(str
, "hpiosize=", 9)) {
4598 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
4599 } else if (!strncmp(str
, "hpmemsize=", 10)) {
4600 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
4601 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
4602 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
4603 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
4604 pcie_bus_config
= PCIE_BUS_SAFE
;
4605 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
4606 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
4607 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
4608 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
4609 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
4610 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
4612 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
4620 early_param("pci", pci_setup
);