2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm-generic/pci-bridge.h>
26 #include <asm/setup.h>
29 const char *pci_power_names
[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32 EXPORT_SYMBOL_GPL(pci_power_names
);
34 int isa_dma_bridge_buggy
;
35 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
38 EXPORT_SYMBOL(pci_pci_problems
);
40 unsigned int pci_pm_d3_delay
;
42 static void pci_pme_list_scan(struct work_struct
*work
);
44 static LIST_HEAD(pci_pme_list
);
45 static DEFINE_MUTEX(pci_pme_list_mutex
);
46 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
48 struct pci_pme_device
{
49 struct list_head list
;
53 #define PME_TIMEOUT 1000 /* How long between PME checks */
55 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
57 unsigned int delay
= dev
->d3_delay
;
59 if (delay
< pci_pm_d3_delay
)
60 delay
= pci_pm_d3_delay
;
65 #ifdef CONFIG_PCI_DOMAINS
66 int pci_domains_supported
= 1;
69 #define DEFAULT_CARDBUS_IO_SIZE (256)
70 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
72 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
73 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
75 #define DEFAULT_HOTPLUG_IO_SIZE (256)
76 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
78 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
79 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
81 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
89 u8 pci_dfl_cache_line_size __devinitdata
= L1_CACHE_BYTES
>> 2;
90 u8 pci_cache_line_size
;
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
96 unsigned int pcibios_max_latency
= 255;
98 /* If set, the PCIe ARI capability will not be used. */
99 static bool pcie_ari_disabled
;
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
108 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
110 struct list_head
*tmp
;
111 unsigned char max
, n
;
113 max
= bus
->busn_res
.end
;
114 list_for_each(tmp
, &bus
->children
) {
115 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
121 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
123 #ifdef CONFIG_HAS_IOMEM
124 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
127 * Make sure the BAR is actually a memory resource, not an IO resource
129 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
133 return ioremap_nocache(pci_resource_start(pdev
, bar
),
134 pci_resource_len(pdev
, bar
));
136 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
139 #define PCI_FIND_CAP_TTL 48
141 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
142 u8 pos
, int cap
, int *ttl
)
147 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
151 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
157 pos
+= PCI_CAP_LIST_NEXT
;
162 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
165 int ttl
= PCI_FIND_CAP_TTL
;
167 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
170 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
172 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
173 pos
+ PCI_CAP_LIST_NEXT
, cap
);
175 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
177 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
178 unsigned int devfn
, u8 hdr_type
)
182 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
183 if (!(status
& PCI_STATUS_CAP_LIST
))
187 case PCI_HEADER_TYPE_NORMAL
:
188 case PCI_HEADER_TYPE_BRIDGE
:
189 return PCI_CAPABILITY_LIST
;
190 case PCI_HEADER_TYPE_CARDBUS
:
191 return PCI_CB_CAPABILITY_LIST
;
200 * pci_find_capability - query for devices' capabilities
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Tell if a device supports a given PCI capability.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
207 * support it. Possible values for @cap:
209 * %PCI_CAP_ID_PM Power Management
210 * %PCI_CAP_ID_AGP Accelerated Graphics Port
211 * %PCI_CAP_ID_VPD Vital Product Data
212 * %PCI_CAP_ID_SLOTID Slot Identification
213 * %PCI_CAP_ID_MSI Message Signalled Interrupts
214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
215 * %PCI_CAP_ID_PCIX PCI-X
216 * %PCI_CAP_ID_EXP PCI Express
218 int pci_find_capability(struct pci_dev
*dev
, int cap
)
222 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
224 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
230 * pci_bus_find_capability - query for devices' capabilities
231 * @bus: the PCI bus to query
232 * @devfn: PCI device to query
233 * @cap: capability code
235 * Like pci_find_capability() but works for pci devices that do not have a
236 * pci_dev structure set up yet.
238 * Returns the address of the requested capability structure within the
239 * device's PCI configuration space or 0 in case the device does not
242 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
247 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
249 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
251 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
257 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
258 * @dev: PCI device to check
260 * Like pci_pcie_cap() but also checks that the PCIe capability version is
261 * >= 2. Note that v1 capability structures could be sparse in that not
262 * all register fields were required. v2 requires the entire structure to
263 * be present size wise, while still allowing for non-implemented registers
264 * to exist but they must be hardwired to 0.
266 * Due to the differences in the versions of capability structures, one
267 * must be careful not to try and access non-existant registers that may
268 * exist in early versions - v1 - of Express devices.
270 * Returns the offset of the PCIe capability structure as long as the
271 * capability version is >= 2; otherwise 0 is returned.
273 static int pci_pcie_cap2(struct pci_dev
*dev
)
278 pos
= pci_pcie_cap(dev
);
280 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
281 if ((flags
& PCI_EXP_FLAGS_VERS
) < 2)
289 * pci_find_next_ext_capability - Find an extended capability
290 * @dev: PCI device to query
291 * @start: address at which to start looking (0 to start at beginning of list)
292 * @cap: capability code
294 * Returns the address of the next matching extended capability structure
295 * within the device's PCI configuration space or 0 if the device does
296 * not support it. Some capabilities can occur several times, e.g., the
297 * vendor-specific capability, and this provides a way to find them all.
299 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
303 int pos
= PCI_CFG_SPACE_SIZE
;
305 /* minimum 8 bytes per capability */
306 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
308 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
314 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
318 * If we have no capabilities, this is indicated by cap ID,
319 * cap version and next pointer all being 0.
325 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
328 pos
= PCI_EXT_CAP_NEXT(header
);
329 if (pos
< PCI_CFG_SPACE_SIZE
)
332 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
338 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
341 * pci_find_ext_capability - Find an extended capability
342 * @dev: PCI device to query
343 * @cap: capability code
345 * Returns the address of the requested extended capability structure
346 * within the device's PCI configuration space or 0 if the device does
347 * not support it. Possible values for @cap:
349 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
350 * %PCI_EXT_CAP_ID_VC Virtual Channel
351 * %PCI_EXT_CAP_ID_DSN Device Serial Number
352 * %PCI_EXT_CAP_ID_PWR Power Budgeting
354 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
356 return pci_find_next_ext_capability(dev
, 0, cap
);
358 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
360 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
362 int rc
, ttl
= PCI_FIND_CAP_TTL
;
365 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
366 mask
= HT_3BIT_CAP_MASK
;
368 mask
= HT_5BIT_CAP_MASK
;
370 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
371 PCI_CAP_ID_HT
, &ttl
);
373 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
374 if (rc
!= PCIBIOS_SUCCESSFUL
)
377 if ((cap
& mask
) == ht_cap
)
380 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
381 pos
+ PCI_CAP_LIST_NEXT
,
382 PCI_CAP_ID_HT
, &ttl
);
388 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
389 * @dev: PCI device to query
390 * @pos: Position from which to continue searching
391 * @ht_cap: Hypertransport capability code
393 * To be used in conjunction with pci_find_ht_capability() to search for
394 * all capabilities matching @ht_cap. @pos should always be a value returned
395 * from pci_find_ht_capability().
397 * NB. To be 100% safe against broken PCI devices, the caller should take
398 * steps to avoid an infinite loop.
400 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
402 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
404 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
407 * pci_find_ht_capability - query a device's Hypertransport capabilities
408 * @dev: PCI device to query
409 * @ht_cap: Hypertransport capability code
411 * Tell if a device supports a given Hypertransport capability.
412 * Returns an address within the device's PCI configuration space
413 * or 0 in case the device does not support the request capability.
414 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
415 * which has a Hypertransport capability matching @ht_cap.
417 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
421 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
423 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
427 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
430 * pci_find_parent_resource - return resource region of parent bus of given region
431 * @dev: PCI device structure contains resources to be searched
432 * @res: child resource record for which parent is sought
434 * For given resource region of given device, return the resource
435 * region of parent bus the given region is contained in or where
436 * it should be allocated from.
439 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
441 const struct pci_bus
*bus
= dev
->bus
;
443 struct resource
*best
= NULL
, *r
;
445 pci_bus_for_each_resource(bus
, r
, i
) {
448 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
449 continue; /* Not contained */
450 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
451 continue; /* Wrong type */
452 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
453 return r
; /* Exact match */
454 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
455 if (r
->flags
& IORESOURCE_PREFETCH
)
457 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
465 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
466 * @dev: PCI device to have its BARs restored
468 * Restore the BAR values for a given device, so as to make it
469 * accessible by its driver.
472 pci_restore_bars(struct pci_dev
*dev
)
476 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
477 pci_update_resource(dev
, i
);
480 static struct pci_platform_pm_ops
*pci_platform_pm
;
482 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
484 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
485 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
487 pci_platform_pm
= ops
;
491 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
493 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
496 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
499 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
502 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
504 return pci_platform_pm
?
505 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
508 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
510 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
513 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
515 return pci_platform_pm
?
516 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
519 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
521 return pci_platform_pm
?
522 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
526 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
528 * @dev: PCI device to handle.
529 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
532 * -EINVAL if the requested state is invalid.
533 * -EIO if device does not support PCI PM or its PM capabilities register has a
534 * wrong version, or device doesn't support the requested state.
535 * 0 if device already is in the requested state.
536 * 0 if device's power state has been successfully changed.
538 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
541 bool need_restore
= false;
543 /* Check if we're already there */
544 if (dev
->current_state
== state
)
550 if (state
< PCI_D0
|| state
> PCI_D3hot
)
553 /* Validate current state:
554 * Can enter D0 from any state, but if we can only go deeper
555 * to sleep if we're already in a low power state
557 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
558 && dev
->current_state
> state
) {
559 dev_err(&dev
->dev
, "invalid power transition "
560 "(from state %d to %d)\n", dev
->current_state
, state
);
564 /* check if this device supports the desired state */
565 if ((state
== PCI_D1
&& !dev
->d1_support
)
566 || (state
== PCI_D2
&& !dev
->d2_support
))
569 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
571 /* If we're (effectively) in D3, force entire word to 0.
572 * This doesn't affect PME_Status, disables PME_En, and
573 * sets PowerState to 0.
575 switch (dev
->current_state
) {
579 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
584 case PCI_UNKNOWN
: /* Boot-up */
585 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
586 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
588 /* Fall-through: force to D0 */
594 /* enter specified state */
595 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
597 /* Mandatory power management transition delays */
598 /* see PCI PM 1.1 5.6.1 table 18 */
599 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
600 pci_dev_d3_sleep(dev
);
601 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
602 udelay(PCI_PM_D2_DELAY
);
604 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
605 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
606 if (dev
->current_state
!= state
&& printk_ratelimit())
607 dev_info(&dev
->dev
, "Refused to change power state, "
608 "currently in D%d\n", dev
->current_state
);
611 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
612 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
613 * from D3hot to D0 _may_ perform an internal reset, thereby
614 * going to "D0 Uninitialized" rather than "D0 Initialized".
615 * For example, at least some versions of the 3c905B and the
616 * 3c556B exhibit this behaviour.
618 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
619 * devices in a D3hot state at boot. Consequently, we need to
620 * restore at least the BARs so that the device will be
621 * accessible to its driver.
624 pci_restore_bars(dev
);
627 pcie_aspm_pm_state_change(dev
->bus
->self
);
633 * pci_update_current_state - Read PCI power state of given device from its
634 * PCI PM registers and cache it
635 * @dev: PCI device to handle.
636 * @state: State to cache in case the device doesn't have the PM capability
638 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
644 * Configuration space is not accessible for device in
645 * D3cold, so just keep or set D3cold for safety
647 if (dev
->current_state
== PCI_D3cold
)
649 if (state
== PCI_D3cold
) {
650 dev
->current_state
= PCI_D3cold
;
653 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
654 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
656 dev
->current_state
= state
;
661 * pci_power_up - Put the given device into D0 forcibly
662 * @dev: PCI device to power up
664 void pci_power_up(struct pci_dev
*dev
)
666 if (platform_pci_power_manageable(dev
))
667 platform_pci_set_power_state(dev
, PCI_D0
);
669 pci_raw_set_power_state(dev
, PCI_D0
);
670 pci_update_current_state(dev
, PCI_D0
);
674 * pci_platform_power_transition - Use platform to change device power state
675 * @dev: PCI device to handle.
676 * @state: State to put the device into.
678 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
682 if (platform_pci_power_manageable(dev
)) {
683 error
= platform_pci_set_power_state(dev
, state
);
685 pci_update_current_state(dev
, state
);
686 /* Fall back to PCI_D0 if native PM is not supported */
688 dev
->current_state
= PCI_D0
;
691 /* Fall back to PCI_D0 if native PM is not supported */
693 dev
->current_state
= PCI_D0
;
700 * __pci_start_power_transition - Start power transition of a PCI device
701 * @dev: PCI device to handle.
702 * @state: State to put the device into.
704 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
706 if (state
== PCI_D0
) {
707 pci_platform_power_transition(dev
, PCI_D0
);
709 * Mandatory power management transition delays, see
710 * PCI Express Base Specification Revision 2.0 Section
711 * 6.6.1: Conventional Reset. Do not delay for
712 * devices powered on/off by corresponding bridge,
713 * because have already delayed for the bridge.
715 if (dev
->runtime_d3cold
) {
716 msleep(dev
->d3cold_delay
);
718 * When powering on a bridge from D3cold, the
719 * whole hierarchy may be powered on into
720 * D0uninitialized state, resume them to give
721 * them a chance to suspend again
723 pci_wakeup_bus(dev
->subordinate
);
729 * __pci_dev_set_current_state - Set current state of a PCI device
730 * @dev: Device to handle
731 * @data: pointer to state to be set
733 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
735 pci_power_t state
= *(pci_power_t
*)data
;
737 dev
->current_state
= state
;
742 * __pci_bus_set_current_state - Walk given bus and set current state of devices
743 * @bus: Top bus of the subtree to walk.
744 * @state: state to be set
746 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
749 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
753 * __pci_complete_power_transition - Complete power transition of a PCI device
754 * @dev: PCI device to handle.
755 * @state: State to put the device into.
757 * This function should not be called directly by device drivers.
759 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
765 ret
= pci_platform_power_transition(dev
, state
);
766 /* Power off the bridge may power off the whole hierarchy */
767 if (!ret
&& state
== PCI_D3cold
)
768 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
771 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
774 * pci_set_power_state - Set the power state of a PCI device
775 * @dev: PCI device to handle.
776 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
778 * Transition a device to a new power state, using the platform firmware and/or
779 * the device's PCI PM registers.
782 * -EINVAL if the requested state is invalid.
783 * -EIO if device does not support PCI PM or its PM capabilities register has a
784 * wrong version, or device doesn't support the requested state.
785 * 0 if device already is in the requested state.
786 * 0 if device's power state has been successfully changed.
788 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
792 /* bound the state we're entering */
793 if (state
> PCI_D3cold
)
795 else if (state
< PCI_D0
)
797 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
799 * If the device or the parent bridge do not support PCI PM,
800 * ignore the request if we're doing anything other than putting
801 * it into D0 (which would only happen on boot).
805 /* Check if we're already there */
806 if (dev
->current_state
== state
)
809 __pci_start_power_transition(dev
, state
);
811 /* This device is quirked not to be put into D3, so
812 don't put it in D3 */
813 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
817 * To put device in D3cold, we put device into D3hot in native
818 * way, then put device into D3cold with platform ops
820 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
823 if (!__pci_complete_power_transition(dev
, state
))
826 * When aspm_policy is "powersave" this call ensures
827 * that ASPM is configured.
829 if (!error
&& dev
->bus
->self
)
830 pcie_aspm_powersave_config_link(dev
->bus
->self
);
836 * pci_choose_state - Choose the power state of a PCI device
837 * @dev: PCI device to be suspended
838 * @state: target sleep state for the whole system. This is the value
839 * that is passed to suspend() function.
841 * Returns PCI power state suitable for given device and given system
845 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
849 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
852 ret
= platform_pci_choose_state(dev
);
853 if (ret
!= PCI_POWER_ERROR
)
856 switch (state
.event
) {
859 case PM_EVENT_FREEZE
:
860 case PM_EVENT_PRETHAW
:
861 /* REVISIT both freeze and pre-thaw "should" use D0 */
862 case PM_EVENT_SUSPEND
:
863 case PM_EVENT_HIBERNATE
:
866 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
873 EXPORT_SYMBOL(pci_choose_state
);
875 #define PCI_EXP_SAVE_REGS 7
877 #define pcie_cap_has_devctl(type, flags) 1
878 #define pcie_cap_has_lnkctl(type, flags) \
879 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
880 (type == PCI_EXP_TYPE_ROOT_PORT || \
881 type == PCI_EXP_TYPE_ENDPOINT || \
882 type == PCI_EXP_TYPE_LEG_END))
883 #define pcie_cap_has_sltctl(type, flags) \
884 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
885 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
886 (type == PCI_EXP_TYPE_DOWNSTREAM && \
887 (flags & PCI_EXP_FLAGS_SLOT))))
888 #define pcie_cap_has_rtctl(type, flags) \
889 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
890 (type == PCI_EXP_TYPE_ROOT_PORT || \
891 type == PCI_EXP_TYPE_RC_EC))
893 static struct pci_cap_saved_state
*pci_find_saved_cap(
894 struct pci_dev
*pci_dev
, char cap
)
896 struct pci_cap_saved_state
*tmp
;
897 struct hlist_node
*pos
;
899 hlist_for_each_entry(tmp
, pos
, &pci_dev
->saved_cap_space
, next
) {
900 if (tmp
->cap
.cap_nr
== cap
)
906 static int pci_save_pcie_state(struct pci_dev
*dev
)
909 struct pci_cap_saved_state
*save_state
;
913 pos
= pci_pcie_cap(dev
);
917 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
919 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
922 cap
= (u16
*)&save_state
->cap
.data
[0];
924 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
926 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
927 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
928 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
929 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
930 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
931 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
932 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
933 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
935 pos
= pci_pcie_cap2(dev
);
939 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
940 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
941 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
945 static void pci_restore_pcie_state(struct pci_dev
*dev
)
948 struct pci_cap_saved_state
*save_state
;
952 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
953 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
954 if (!save_state
|| pos
<= 0)
956 cap
= (u16
*)&save_state
->cap
.data
[0];
958 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
960 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
961 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
962 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
963 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
964 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
965 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
966 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
967 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
969 pos
= pci_pcie_cap2(dev
);
973 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
974 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
975 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
979 static int pci_save_pcix_state(struct pci_dev
*dev
)
982 struct pci_cap_saved_state
*save_state
;
984 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
988 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
990 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
994 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
995 (u16
*)save_state
->cap
.data
);
1000 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1003 struct pci_cap_saved_state
*save_state
;
1006 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1007 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1008 if (!save_state
|| pos
<= 0)
1010 cap
= (u16
*)&save_state
->cap
.data
[0];
1012 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1017 * pci_save_state - save the PCI configuration space of a device before suspending
1018 * @dev: - PCI device that we're dealing with
1021 pci_save_state(struct pci_dev
*dev
)
1024 /* XXX: 100% dword access ok here? */
1025 for (i
= 0; i
< 16; i
++)
1026 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1027 dev
->state_saved
= true;
1028 if ((i
= pci_save_pcie_state(dev
)) != 0)
1030 if ((i
= pci_save_pcix_state(dev
)) != 0)
1035 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1036 u32 saved_val
, int retry
)
1040 pci_read_config_dword(pdev
, offset
, &val
);
1041 if (val
== saved_val
)
1045 dev_dbg(&pdev
->dev
, "restoring config space at offset "
1046 "%#x (was %#x, writing %#x)\n", offset
, val
, saved_val
);
1047 pci_write_config_dword(pdev
, offset
, saved_val
);
1051 pci_read_config_dword(pdev
, offset
, &val
);
1052 if (val
== saved_val
)
1059 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1060 int start
, int end
, int retry
)
1064 for (index
= end
; index
>= start
; index
--)
1065 pci_restore_config_dword(pdev
, 4 * index
,
1066 pdev
->saved_config_space
[index
],
1070 static void pci_restore_config_space(struct pci_dev
*pdev
)
1072 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1073 pci_restore_config_space_range(pdev
, 10, 15, 0);
1074 /* Restore BARs before the command register. */
1075 pci_restore_config_space_range(pdev
, 4, 9, 10);
1076 pci_restore_config_space_range(pdev
, 0, 3, 0);
1078 pci_restore_config_space_range(pdev
, 0, 15, 0);
1083 * pci_restore_state - Restore the saved state of a PCI device
1084 * @dev: - PCI device that we're dealing with
1086 void pci_restore_state(struct pci_dev
*dev
)
1088 if (!dev
->state_saved
)
1091 /* PCI Express register must be restored first */
1092 pci_restore_pcie_state(dev
);
1093 pci_restore_ats_state(dev
);
1095 pci_restore_config_space(dev
);
1097 pci_restore_pcix_state(dev
);
1098 pci_restore_msi_state(dev
);
1099 pci_restore_iov_state(dev
);
1101 dev
->state_saved
= false;
1104 struct pci_saved_state
{
1105 u32 config_space
[16];
1106 struct pci_cap_saved_data cap
[0];
1110 * pci_store_saved_state - Allocate and return an opaque struct containing
1111 * the device saved state.
1112 * @dev: PCI device that we're dealing with
1114 * Rerturn NULL if no state or error.
1116 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1118 struct pci_saved_state
*state
;
1119 struct pci_cap_saved_state
*tmp
;
1120 struct pci_cap_saved_data
*cap
;
1121 struct hlist_node
*pos
;
1124 if (!dev
->state_saved
)
1127 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1129 hlist_for_each_entry(tmp
, pos
, &dev
->saved_cap_space
, next
)
1130 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1132 state
= kzalloc(size
, GFP_KERNEL
);
1136 memcpy(state
->config_space
, dev
->saved_config_space
,
1137 sizeof(state
->config_space
));
1140 hlist_for_each_entry(tmp
, pos
, &dev
->saved_cap_space
, next
) {
1141 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1142 memcpy(cap
, &tmp
->cap
, len
);
1143 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1145 /* Empty cap_save terminates list */
1149 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1152 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1153 * @dev: PCI device that we're dealing with
1154 * @state: Saved state returned from pci_store_saved_state()
1156 int pci_load_saved_state(struct pci_dev
*dev
, struct pci_saved_state
*state
)
1158 struct pci_cap_saved_data
*cap
;
1160 dev
->state_saved
= false;
1165 memcpy(dev
->saved_config_space
, state
->config_space
,
1166 sizeof(state
->config_space
));
1170 struct pci_cap_saved_state
*tmp
;
1172 tmp
= pci_find_saved_cap(dev
, cap
->cap_nr
);
1173 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1176 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1177 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1178 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1181 dev
->state_saved
= true;
1184 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1187 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1188 * and free the memory allocated for it.
1189 * @dev: PCI device that we're dealing with
1190 * @state: Pointer to saved state returned from pci_store_saved_state()
1192 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1193 struct pci_saved_state
**state
)
1195 int ret
= pci_load_saved_state(dev
, *state
);
1200 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1202 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1206 err
= pci_set_power_state(dev
, PCI_D0
);
1207 if (err
< 0 && err
!= -EIO
)
1209 err
= pcibios_enable_device(dev
, bars
);
1212 pci_fixup_device(pci_fixup_enable
, dev
);
1218 * pci_reenable_device - Resume abandoned device
1219 * @dev: PCI device to be resumed
1221 * Note this function is a backend of pci_default_resume and is not supposed
1222 * to be called by normal code, write proper resume handler and use it instead.
1224 int pci_reenable_device(struct pci_dev
*dev
)
1226 if (pci_is_enabled(dev
))
1227 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1231 static int __pci_enable_device_flags(struct pci_dev
*dev
,
1232 resource_size_t flags
)
1238 * Power state could be unknown at this point, either due to a fresh
1239 * boot or a device removal call. So get the current power state
1240 * so that things like MSI message writing will behave as expected
1241 * (e.g. if the device really is in D0 at enable time).
1245 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1246 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1249 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
1250 return 0; /* already enabled */
1252 /* only skip sriov related */
1253 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1254 if (dev
->resource
[i
].flags
& flags
)
1256 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1257 if (dev
->resource
[i
].flags
& flags
)
1260 err
= do_pci_enable_device(dev
, bars
);
1262 atomic_dec(&dev
->enable_cnt
);
1267 * pci_enable_device_io - Initialize a device for use with IO space
1268 * @dev: PCI device to be initialized
1270 * Initialize device before it's used by a driver. Ask low-level code
1271 * to enable I/O resources. Wake up the device if it was suspended.
1272 * Beware, this function can fail.
1274 int pci_enable_device_io(struct pci_dev
*dev
)
1276 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
1280 * pci_enable_device_mem - Initialize a device for use with Memory space
1281 * @dev: PCI device to be initialized
1283 * Initialize device before it's used by a driver. Ask low-level code
1284 * to enable Memory resources. Wake up the device if it was suspended.
1285 * Beware, this function can fail.
1287 int pci_enable_device_mem(struct pci_dev
*dev
)
1289 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1293 * pci_enable_device - Initialize device before it's used by a driver.
1294 * @dev: PCI device to be initialized
1296 * Initialize device before it's used by a driver. Ask low-level code
1297 * to enable I/O and memory. Wake up the device if it was suspended.
1298 * Beware, this function can fail.
1300 * Note we don't actually enable the device many times if we call
1301 * this function repeatedly (we just increment the count).
1303 int pci_enable_device(struct pci_dev
*dev
)
1305 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1309 * Managed PCI resources. This manages device on/off, intx/msi/msix
1310 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1311 * there's no need to track it separately. pci_devres is initialized
1312 * when a device is enabled using managed PCI device enable interface.
1315 unsigned int enabled
:1;
1316 unsigned int pinned
:1;
1317 unsigned int orig_intx
:1;
1318 unsigned int restore_intx
:1;
1322 static void pcim_release(struct device
*gendev
, void *res
)
1324 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1325 struct pci_devres
*this = res
;
1328 if (dev
->msi_enabled
)
1329 pci_disable_msi(dev
);
1330 if (dev
->msix_enabled
)
1331 pci_disable_msix(dev
);
1333 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1334 if (this->region_mask
& (1 << i
))
1335 pci_release_region(dev
, i
);
1337 if (this->restore_intx
)
1338 pci_intx(dev
, this->orig_intx
);
1340 if (this->enabled
&& !this->pinned
)
1341 pci_disable_device(dev
);
1344 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1346 struct pci_devres
*dr
, *new_dr
;
1348 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1352 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1355 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1358 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1360 if (pci_is_managed(pdev
))
1361 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1366 * pcim_enable_device - Managed pci_enable_device()
1367 * @pdev: PCI device to be initialized
1369 * Managed pci_enable_device().
1371 int pcim_enable_device(struct pci_dev
*pdev
)
1373 struct pci_devres
*dr
;
1376 dr
= get_pci_dr(pdev
);
1382 rc
= pci_enable_device(pdev
);
1384 pdev
->is_managed
= 1;
1391 * pcim_pin_device - Pin managed PCI device
1392 * @pdev: PCI device to pin
1394 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1395 * driver detach. @pdev must have been enabled with
1396 * pcim_enable_device().
1398 void pcim_pin_device(struct pci_dev
*pdev
)
1400 struct pci_devres
*dr
;
1402 dr
= find_pci_dr(pdev
);
1403 WARN_ON(!dr
|| !dr
->enabled
);
1409 * pcibios_disable_device - disable arch specific PCI resources for device dev
1410 * @dev: the PCI device to disable
1412 * Disables architecture specific PCI resources for the device. This
1413 * is the default implementation. Architecture implementations can
1416 void __weak
pcibios_disable_device (struct pci_dev
*dev
) {}
1418 static void do_pci_disable_device(struct pci_dev
*dev
)
1422 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1423 if (pci_command
& PCI_COMMAND_MASTER
) {
1424 pci_command
&= ~PCI_COMMAND_MASTER
;
1425 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1428 pcibios_disable_device(dev
);
1432 * pci_disable_enabled_device - Disable device without updating enable_cnt
1433 * @dev: PCI device to disable
1435 * NOTE: This function is a backend of PCI power management routines and is
1436 * not supposed to be called drivers.
1438 void pci_disable_enabled_device(struct pci_dev
*dev
)
1440 if (pci_is_enabled(dev
))
1441 do_pci_disable_device(dev
);
1445 * pci_disable_device - Disable PCI device after use
1446 * @dev: PCI device to be disabled
1448 * Signal to the system that the PCI device is not in use by the system
1449 * anymore. This only involves disabling PCI bus-mastering, if active.
1451 * Note we don't actually disable the device until all callers of
1452 * pci_enable_device() have called pci_disable_device().
1455 pci_disable_device(struct pci_dev
*dev
)
1457 struct pci_devres
*dr
;
1459 dr
= find_pci_dr(dev
);
1463 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1466 do_pci_disable_device(dev
);
1468 dev
->is_busmaster
= 0;
1472 * pcibios_set_pcie_reset_state - set reset state for device dev
1473 * @dev: the PCIe device reset
1474 * @state: Reset state to enter into
1477 * Sets the PCIe reset state for the device. This is the default
1478 * implementation. Architecture implementations can override this.
1480 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1481 enum pcie_reset_state state
)
1487 * pci_set_pcie_reset_state - set reset state for device dev
1488 * @dev: the PCIe device reset
1489 * @state: Reset state to enter into
1492 * Sets the PCI reset state for the device.
1494 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1496 return pcibios_set_pcie_reset_state(dev
, state
);
1500 * pci_check_pme_status - Check if given device has generated PME.
1501 * @dev: Device to check.
1503 * Check the PME status of the device and if set, clear it and clear PME enable
1504 * (if set). Return 'true' if PME status and PME enable were both set or
1505 * 'false' otherwise.
1507 bool pci_check_pme_status(struct pci_dev
*dev
)
1516 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1517 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1518 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1521 /* Clear PME status. */
1522 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1523 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1524 /* Disable PME to avoid interrupt flood. */
1525 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1529 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1535 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1536 * @dev: Device to handle.
1537 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1539 * Check if @dev has generated PME and queue a resume request for it in that
1542 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1544 if (pme_poll_reset
&& dev
->pme_poll
)
1545 dev
->pme_poll
= false;
1547 if (pci_check_pme_status(dev
)) {
1548 pci_wakeup_event(dev
);
1549 pm_request_resume(&dev
->dev
);
1555 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1556 * @bus: Top bus of the subtree to walk.
1558 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1561 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1565 * pci_wakeup - Wake up a PCI device
1566 * @dev: Device to handle.
1567 * @ign: ignored parameter
1569 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
1571 pci_wakeup_event(pci_dev
);
1572 pm_request_resume(&pci_dev
->dev
);
1577 * pci_wakeup_bus - Walk given bus and wake up devices on it
1578 * @bus: Top bus of the subtree to walk.
1580 void pci_wakeup_bus(struct pci_bus
*bus
)
1583 pci_walk_bus(bus
, pci_wakeup
, NULL
);
1587 * pci_pme_capable - check the capability of PCI device to generate PME#
1588 * @dev: PCI device to handle.
1589 * @state: PCI state from which device will issue PME#.
1591 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1596 return !!(dev
->pme_support
& (1 << state
));
1599 static void pci_pme_list_scan(struct work_struct
*work
)
1601 struct pci_pme_device
*pme_dev
, *n
;
1603 mutex_lock(&pci_pme_list_mutex
);
1604 if (!list_empty(&pci_pme_list
)) {
1605 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1606 if (pme_dev
->dev
->pme_poll
) {
1607 struct pci_dev
*bridge
;
1609 bridge
= pme_dev
->dev
->bus
->self
;
1611 * If bridge is in low power state, the
1612 * configuration space of subordinate devices
1613 * may be not accessible
1615 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1617 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1619 list_del(&pme_dev
->list
);
1623 if (!list_empty(&pci_pme_list
))
1624 schedule_delayed_work(&pci_pme_work
,
1625 msecs_to_jiffies(PME_TIMEOUT
));
1627 mutex_unlock(&pci_pme_list_mutex
);
1631 * pci_pme_active - enable or disable PCI device's PME# function
1632 * @dev: PCI device to handle.
1633 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1635 * The caller must verify that the device is capable of generating PME# before
1636 * calling this function with @enable equal to 'true'.
1638 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1645 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1646 /* Clear PME_Status by writing 1 to it and enable PME# */
1647 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1649 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1651 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1653 /* PCI (as opposed to PCIe) PME requires that the device have
1654 its PME# line hooked up correctly. Not all hardware vendors
1655 do this, so the PME never gets delivered and the device
1656 remains asleep. The easiest way around this is to
1657 periodically walk the list of suspended devices and check
1658 whether any have their PME flag set. The assumption is that
1659 we'll wake up often enough anyway that this won't be a huge
1660 hit, and the power savings from the devices will still be a
1663 if (dev
->pme_poll
) {
1664 struct pci_pme_device
*pme_dev
;
1666 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1671 mutex_lock(&pci_pme_list_mutex
);
1672 list_add(&pme_dev
->list
, &pci_pme_list
);
1673 if (list_is_singular(&pci_pme_list
))
1674 schedule_delayed_work(&pci_pme_work
,
1675 msecs_to_jiffies(PME_TIMEOUT
));
1676 mutex_unlock(&pci_pme_list_mutex
);
1678 mutex_lock(&pci_pme_list_mutex
);
1679 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1680 if (pme_dev
->dev
== dev
) {
1681 list_del(&pme_dev
->list
);
1686 mutex_unlock(&pci_pme_list_mutex
);
1691 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1695 * __pci_enable_wake - enable PCI device as wakeup event source
1696 * @dev: PCI device affected
1697 * @state: PCI state from which device will issue wakeup events
1698 * @runtime: True if the events are to be generated at run time
1699 * @enable: True to enable event generation; false to disable
1701 * This enables the device as a wakeup event source, or disables it.
1702 * When such events involves platform-specific hooks, those hooks are
1703 * called automatically by this routine.
1705 * Devices with legacy power management (no standard PCI PM capabilities)
1706 * always require such platform hooks.
1709 * 0 is returned on success
1710 * -EINVAL is returned if device is not supposed to wake up the system
1711 * Error code depending on the platform is returned if both the platform and
1712 * the native mechanism fail to enable the generation of wake-up events
1714 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1715 bool runtime
, bool enable
)
1719 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1722 /* Don't do the same thing twice in a row for one device. */
1723 if (!!enable
== !!dev
->wakeup_prepared
)
1727 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1728 * Anderson we should be doing PME# wake enable followed by ACPI wake
1729 * enable. To disable wake-up we call the platform first, for symmetry.
1735 if (pci_pme_capable(dev
, state
))
1736 pci_pme_active(dev
, true);
1739 error
= runtime
? platform_pci_run_wake(dev
, true) :
1740 platform_pci_sleep_wake(dev
, true);
1744 dev
->wakeup_prepared
= true;
1747 platform_pci_run_wake(dev
, false);
1749 platform_pci_sleep_wake(dev
, false);
1750 pci_pme_active(dev
, false);
1751 dev
->wakeup_prepared
= false;
1756 EXPORT_SYMBOL(__pci_enable_wake
);
1759 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1760 * @dev: PCI device to prepare
1761 * @enable: True to enable wake-up event generation; false to disable
1763 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1764 * and this function allows them to set that up cleanly - pci_enable_wake()
1765 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1766 * ordering constraints.
1768 * This function only returns error code if the device is not capable of
1769 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1770 * enable wake-up power for it.
1772 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1774 return pci_pme_capable(dev
, PCI_D3cold
) ?
1775 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1776 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1780 * pci_target_state - find an appropriate low power state for a given PCI dev
1783 * Use underlying platform code to find a supported low power state for @dev.
1784 * If the platform can't manage @dev, return the deepest state from which it
1785 * can generate wake events, based on any available PME info.
1787 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1789 pci_power_t target_state
= PCI_D3hot
;
1791 if (platform_pci_power_manageable(dev
)) {
1793 * Call the platform to choose the target state of the device
1794 * and enable wake-up from this state if supported.
1796 pci_power_t state
= platform_pci_choose_state(dev
);
1799 case PCI_POWER_ERROR
:
1804 if (pci_no_d1d2(dev
))
1807 target_state
= state
;
1809 } else if (!dev
->pm_cap
) {
1810 target_state
= PCI_D0
;
1811 } else if (device_may_wakeup(&dev
->dev
)) {
1813 * Find the deepest state from which the device can generate
1814 * wake-up events, make it the target state and enable device
1817 if (dev
->pme_support
) {
1819 && !(dev
->pme_support
& (1 << target_state
)))
1824 return target_state
;
1828 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1829 * @dev: Device to handle.
1831 * Choose the power state appropriate for the device depending on whether
1832 * it can wake up the system and/or is power manageable by the platform
1833 * (PCI_D3hot is the default) and put the device into that state.
1835 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1837 pci_power_t target_state
= pci_target_state(dev
);
1840 if (target_state
== PCI_POWER_ERROR
)
1843 /* D3cold during system suspend/hibernate is not supported */
1844 if (target_state
> PCI_D3hot
)
1845 target_state
= PCI_D3hot
;
1847 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1849 error
= pci_set_power_state(dev
, target_state
);
1852 pci_enable_wake(dev
, target_state
, false);
1858 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1859 * @dev: Device to handle.
1861 * Disable device's system wake-up capability and put it into D0.
1863 int pci_back_from_sleep(struct pci_dev
*dev
)
1865 pci_enable_wake(dev
, PCI_D0
, false);
1866 return pci_set_power_state(dev
, PCI_D0
);
1870 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1871 * @dev: PCI device being suspended.
1873 * Prepare @dev to generate wake-up events at run time and put it into a low
1876 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1878 pci_power_t target_state
= pci_target_state(dev
);
1881 if (target_state
== PCI_POWER_ERROR
)
1884 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
1886 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1888 error
= pci_set_power_state(dev
, target_state
);
1891 __pci_enable_wake(dev
, target_state
, true, false);
1892 dev
->runtime_d3cold
= false;
1899 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1900 * @dev: Device to check.
1902 * Return true if the device itself is cabable of generating wake-up events
1903 * (through the platform or using the native PCIe PME) or if the device supports
1904 * PME and one of its upstream bridges can generate wake-up events.
1906 bool pci_dev_run_wake(struct pci_dev
*dev
)
1908 struct pci_bus
*bus
= dev
->bus
;
1910 if (device_run_wake(&dev
->dev
))
1913 if (!dev
->pme_support
)
1916 while (bus
->parent
) {
1917 struct pci_dev
*bridge
= bus
->self
;
1919 if (device_run_wake(&bridge
->dev
))
1925 /* We have reached the root bus. */
1927 return device_run_wake(bus
->bridge
);
1931 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1934 * pci_pm_init - Initialize PM functions of given PCI device
1935 * @dev: PCI device to handle.
1937 void pci_pm_init(struct pci_dev
*dev
)
1942 pm_runtime_forbid(&dev
->dev
);
1943 device_enable_async_suspend(&dev
->dev
);
1944 dev
->wakeup_prepared
= false;
1948 /* find PCI PM capability in list */
1949 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1952 /* Check device's ability to generate PME# */
1953 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1955 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1956 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1957 pmc
& PCI_PM_CAP_VER_MASK
);
1962 dev
->d3_delay
= PCI_PM_D3_WAIT
;
1963 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
1965 dev
->d1_support
= false;
1966 dev
->d2_support
= false;
1967 if (!pci_no_d1d2(dev
)) {
1968 if (pmc
& PCI_PM_CAP_D1
)
1969 dev
->d1_support
= true;
1970 if (pmc
& PCI_PM_CAP_D2
)
1971 dev
->d2_support
= true;
1973 if (dev
->d1_support
|| dev
->d2_support
)
1974 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1975 dev
->d1_support
? " D1" : "",
1976 dev
->d2_support
? " D2" : "");
1979 pmc
&= PCI_PM_CAP_PME_MASK
;
1981 dev_printk(KERN_DEBUG
, &dev
->dev
,
1982 "PME# supported from%s%s%s%s%s\n",
1983 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1984 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1985 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1986 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1987 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1988 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1989 dev
->pme_poll
= true;
1991 * Make device's PM flags reflect the wake-up capability, but
1992 * let the user space enable it to wake up the system as needed.
1994 device_set_wakeup_capable(&dev
->dev
, true);
1995 /* Disable the PME# generation functionality */
1996 pci_pme_active(dev
, false);
1998 dev
->pme_support
= 0;
2003 * platform_pci_wakeup_init - init platform wakeup if present
2006 * Some devices don't have PCI PM caps but can still generate wakeup
2007 * events through platform methods (like ACPI events). If @dev supports
2008 * platform wakeup events, set the device flag to indicate as much. This
2009 * may be redundant if the device also supports PCI PM caps, but double
2010 * initialization should be safe in that case.
2012 void platform_pci_wakeup_init(struct pci_dev
*dev
)
2014 if (!platform_pci_can_wakeup(dev
))
2017 device_set_wakeup_capable(&dev
->dev
, true);
2018 platform_pci_sleep_wake(dev
, false);
2021 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2022 struct pci_cap_saved_state
*new_cap
)
2024 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2028 * pci_add_save_buffer - allocate buffer for saving given capability registers
2029 * @dev: the PCI device
2030 * @cap: the capability to allocate the buffer for
2031 * @size: requested size of the buffer
2033 static int pci_add_cap_save_buffer(
2034 struct pci_dev
*dev
, char cap
, unsigned int size
)
2037 struct pci_cap_saved_state
*save_state
;
2039 pos
= pci_find_capability(dev
, cap
);
2043 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2047 save_state
->cap
.cap_nr
= cap
;
2048 save_state
->cap
.size
= size
;
2049 pci_add_saved_cap(dev
, save_state
);
2055 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2056 * @dev: the PCI device
2058 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2062 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2063 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2066 "unable to preallocate PCI Express save buffer\n");
2068 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2071 "unable to preallocate PCI-X save buffer\n");
2074 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2076 struct pci_cap_saved_state
*tmp
;
2077 struct hlist_node
*pos
, *n
;
2079 hlist_for_each_entry_safe(tmp
, pos
, n
, &dev
->saved_cap_space
, next
)
2084 * pci_enable_ari - enable ARI forwarding if hardware support it
2085 * @dev: the PCI device
2087 void pci_enable_ari(struct pci_dev
*dev
)
2092 struct pci_dev
*bridge
;
2094 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2097 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
2101 bridge
= dev
->bus
->self
;
2105 /* ARI is a PCIe cap v2 feature */
2106 pos
= pci_pcie_cap2(bridge
);
2110 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2111 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2114 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2115 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
2116 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2118 bridge
->ari_enabled
= 1;
2122 * pci_enable_ido - enable ID-based Ordering on a device
2123 * @dev: the PCI device
2124 * @type: which types of IDO to enable
2126 * Enable ID-based ordering on @dev. @type can contain the bits
2127 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2128 * which types of transactions are allowed to be re-ordered.
2130 void pci_enable_ido(struct pci_dev
*dev
, unsigned long type
)
2135 /* ID-based Ordering is a PCIe cap v2 feature */
2136 pos
= pci_pcie_cap2(dev
);
2140 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2141 if (type
& PCI_EXP_IDO_REQUEST
)
2142 ctrl
|= PCI_EXP_IDO_REQ_EN
;
2143 if (type
& PCI_EXP_IDO_COMPLETION
)
2144 ctrl
|= PCI_EXP_IDO_CMP_EN
;
2145 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2147 EXPORT_SYMBOL(pci_enable_ido
);
2150 * pci_disable_ido - disable ID-based ordering on a device
2151 * @dev: the PCI device
2152 * @type: which types of IDO to disable
2154 void pci_disable_ido(struct pci_dev
*dev
, unsigned long type
)
2159 /* ID-based Ordering is a PCIe cap v2 feature */
2160 pos
= pci_pcie_cap2(dev
);
2164 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2165 if (type
& PCI_EXP_IDO_REQUEST
)
2166 ctrl
&= ~PCI_EXP_IDO_REQ_EN
;
2167 if (type
& PCI_EXP_IDO_COMPLETION
)
2168 ctrl
&= ~PCI_EXP_IDO_CMP_EN
;
2169 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2171 EXPORT_SYMBOL(pci_disable_ido
);
2174 * pci_enable_obff - enable optimized buffer flush/fill
2176 * @type: type of signaling to use
2178 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2179 * signaling if possible, falling back to message signaling only if
2180 * WAKE# isn't supported. @type should indicate whether the PCIe link
2181 * be brought out of L0s or L1 to send the message. It should be either
2182 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2184 * If your device can benefit from receiving all messages, even at the
2185 * power cost of bringing the link back up from a low power state, use
2186 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2190 * Zero on success, appropriate error number on failure.
2192 int pci_enable_obff(struct pci_dev
*dev
, enum pci_obff_signal_type type
)
2199 /* OBFF is a PCIe cap v2 feature */
2200 pos
= pci_pcie_cap2(dev
);
2204 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2205 if (!(cap
& PCI_EXP_OBFF_MASK
))
2206 return -ENOTSUPP
; /* no OBFF support at all */
2208 /* Make sure the topology supports OBFF as well */
2209 if (dev
->bus
->self
) {
2210 ret
= pci_enable_obff(dev
->bus
->self
, type
);
2215 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2216 if (cap
& PCI_EXP_OBFF_WAKE
)
2217 ctrl
|= PCI_EXP_OBFF_WAKE_EN
;
2220 case PCI_EXP_OBFF_SIGNAL_L0
:
2221 if (!(ctrl
& PCI_EXP_OBFF_WAKE_EN
))
2222 ctrl
|= PCI_EXP_OBFF_MSGA_EN
;
2224 case PCI_EXP_OBFF_SIGNAL_ALWAYS
:
2225 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
2226 ctrl
|= PCI_EXP_OBFF_MSGB_EN
;
2229 WARN(1, "bad OBFF signal type\n");
2233 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2237 EXPORT_SYMBOL(pci_enable_obff
);
2240 * pci_disable_obff - disable optimized buffer flush/fill
2243 * Disable OBFF on @dev.
2245 void pci_disable_obff(struct pci_dev
*dev
)
2250 /* OBFF is a PCIe cap v2 feature */
2251 pos
= pci_pcie_cap2(dev
);
2255 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2256 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
2257 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2259 EXPORT_SYMBOL(pci_disable_obff
);
2262 * pci_ltr_supported - check whether a device supports LTR
2266 * True if @dev supports latency tolerance reporting, false otherwise.
2268 static bool pci_ltr_supported(struct pci_dev
*dev
)
2273 /* LTR is a PCIe cap v2 feature */
2274 pos
= pci_pcie_cap2(dev
);
2278 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2280 return cap
& PCI_EXP_DEVCAP2_LTR
;
2284 * pci_enable_ltr - enable latency tolerance reporting
2287 * Enable LTR on @dev if possible, which means enabling it first on
2291 * Zero on success, errno on failure.
2293 int pci_enable_ltr(struct pci_dev
*dev
)
2299 if (!pci_ltr_supported(dev
))
2302 /* LTR is a PCIe cap v2 feature */
2303 pos
= pci_pcie_cap2(dev
);
2307 /* Only primary function can enable/disable LTR */
2308 if (PCI_FUNC(dev
->devfn
) != 0)
2311 /* Enable upstream ports first */
2312 if (dev
->bus
->self
) {
2313 ret
= pci_enable_ltr(dev
->bus
->self
);
2318 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2319 ctrl
|= PCI_EXP_LTR_EN
;
2320 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2324 EXPORT_SYMBOL(pci_enable_ltr
);
2327 * pci_disable_ltr - disable latency tolerance reporting
2330 void pci_disable_ltr(struct pci_dev
*dev
)
2335 if (!pci_ltr_supported(dev
))
2338 /* LTR is a PCIe cap v2 feature */
2339 pos
= pci_pcie_cap2(dev
);
2343 /* Only primary function can enable/disable LTR */
2344 if (PCI_FUNC(dev
->devfn
) != 0)
2347 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2348 ctrl
&= ~PCI_EXP_LTR_EN
;
2349 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2351 EXPORT_SYMBOL(pci_disable_ltr
);
2353 static int __pci_ltr_scale(int *val
)
2357 while (*val
> 1023) {
2358 *val
= (*val
+ 31) / 32;
2365 * pci_set_ltr - set LTR latency values
2367 * @snoop_lat_ns: snoop latency in nanoseconds
2368 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2370 * Figure out the scale and set the LTR values accordingly.
2372 int pci_set_ltr(struct pci_dev
*dev
, int snoop_lat_ns
, int nosnoop_lat_ns
)
2374 int pos
, ret
, snoop_scale
, nosnoop_scale
;
2377 if (!pci_ltr_supported(dev
))
2380 snoop_scale
= __pci_ltr_scale(&snoop_lat_ns
);
2381 nosnoop_scale
= __pci_ltr_scale(&nosnoop_lat_ns
);
2383 if (snoop_lat_ns
> PCI_LTR_VALUE_MASK
||
2384 nosnoop_lat_ns
> PCI_LTR_VALUE_MASK
)
2387 if ((snoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)) ||
2388 (nosnoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)))
2391 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
2395 val
= (snoop_scale
<< PCI_LTR_SCALE_SHIFT
) | snoop_lat_ns
;
2396 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_SNOOP_LAT
, val
);
2400 val
= (nosnoop_scale
<< PCI_LTR_SCALE_SHIFT
) | nosnoop_lat_ns
;
2401 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_NOSNOOP_LAT
, val
);
2407 EXPORT_SYMBOL(pci_set_ltr
);
2409 static int pci_acs_enable
;
2412 * pci_request_acs - ask for ACS to be enabled if supported
2414 void pci_request_acs(void)
2420 * pci_enable_acs - enable ACS if hardware support it
2421 * @dev: the PCI device
2423 void pci_enable_acs(struct pci_dev
*dev
)
2429 if (!pci_acs_enable
)
2432 if (!pci_is_pcie(dev
))
2435 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2439 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2440 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2442 /* Source Validation */
2443 ctrl
|= (cap
& PCI_ACS_SV
);
2445 /* P2P Request Redirect */
2446 ctrl
|= (cap
& PCI_ACS_RR
);
2448 /* P2P Completion Redirect */
2449 ctrl
|= (cap
& PCI_ACS_CR
);
2451 /* Upstream Forwarding */
2452 ctrl
|= (cap
& PCI_ACS_UF
);
2454 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2458 * pci_acs_enabled - test ACS against required flags for a given device
2459 * @pdev: device to test
2460 * @acs_flags: required PCI ACS flags
2462 * Return true if the device supports the provided flags. Automatically
2463 * filters out flags that are not implemented on multifunction devices.
2465 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2470 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2474 if (!pci_is_pcie(pdev
))
2477 /* Filter out flags not applicable to multifunction */
2478 if (pdev
->multifunction
)
2479 acs_flags
&= (PCI_ACS_RR
| PCI_ACS_CR
|
2480 PCI_ACS_EC
| PCI_ACS_DT
);
2482 if (pdev
->pcie_type
== PCI_EXP_TYPE_DOWNSTREAM
||
2483 pdev
->pcie_type
== PCI_EXP_TYPE_ROOT_PORT
||
2484 pdev
->multifunction
) {
2485 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2489 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2490 if ((ctrl
& acs_flags
) != acs_flags
)
2498 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2499 * @start: starting downstream device
2500 * @end: ending upstream device or NULL to search to the root bus
2501 * @acs_flags: required flags
2503 * Walk up a device tree from start to end testing PCI ACS support. If
2504 * any step along the way does not support the required flags, return false.
2506 bool pci_acs_path_enabled(struct pci_dev
*start
,
2507 struct pci_dev
*end
, u16 acs_flags
)
2509 struct pci_dev
*pdev
, *parent
= start
;
2514 if (!pci_acs_enabled(pdev
, acs_flags
))
2517 if (pci_is_root_bus(pdev
->bus
))
2518 return (end
== NULL
);
2520 parent
= pdev
->bus
->self
;
2521 } while (pdev
!= end
);
2527 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2528 * @dev: the PCI device
2529 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2531 * Perform INTx swizzling for a device behind one level of bridge. This is
2532 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2533 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2534 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2535 * the PCI Express Base Specification, Revision 2.1)
2537 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
2541 if (pci_ari_enabled(dev
->bus
))
2544 slot
= PCI_SLOT(dev
->devfn
);
2546 return (((pin
- 1) + slot
) % 4) + 1;
2550 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2558 while (!pci_is_root_bus(dev
->bus
)) {
2559 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2560 dev
= dev
->bus
->self
;
2567 * pci_common_swizzle - swizzle INTx all the way to root bridge
2568 * @dev: the PCI device
2569 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2571 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2572 * bridges all the way up to a PCI root bus.
2574 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2578 while (!pci_is_root_bus(dev
->bus
)) {
2579 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2580 dev
= dev
->bus
->self
;
2583 return PCI_SLOT(dev
->devfn
);
2587 * pci_release_region - Release a PCI bar
2588 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2589 * @bar: BAR to release
2591 * Releases the PCI I/O and memory resources previously reserved by a
2592 * successful call to pci_request_region. Call this function only
2593 * after all use of the PCI regions has ceased.
2595 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2597 struct pci_devres
*dr
;
2599 if (pci_resource_len(pdev
, bar
) == 0)
2601 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2602 release_region(pci_resource_start(pdev
, bar
),
2603 pci_resource_len(pdev
, bar
));
2604 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2605 release_mem_region(pci_resource_start(pdev
, bar
),
2606 pci_resource_len(pdev
, bar
));
2608 dr
= find_pci_dr(pdev
);
2610 dr
->region_mask
&= ~(1 << bar
);
2614 * __pci_request_region - Reserved PCI I/O and memory resource
2615 * @pdev: PCI device whose resources are to be reserved
2616 * @bar: BAR to be reserved
2617 * @res_name: Name to be associated with resource.
2618 * @exclusive: whether the region access is exclusive or not
2620 * Mark the PCI region associated with PCI device @pdev BR @bar as
2621 * being reserved by owner @res_name. Do not access any
2622 * address inside the PCI regions unless this call returns
2625 * If @exclusive is set, then the region is marked so that userspace
2626 * is explicitly not allowed to map the resource via /dev/mem or
2627 * sysfs MMIO access.
2629 * Returns 0 on success, or %EBUSY on error. A warning
2630 * message is also printed on failure.
2632 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
2635 struct pci_devres
*dr
;
2637 if (pci_resource_len(pdev
, bar
) == 0)
2640 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2641 if (!request_region(pci_resource_start(pdev
, bar
),
2642 pci_resource_len(pdev
, bar
), res_name
))
2645 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2646 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2647 pci_resource_len(pdev
, bar
), res_name
,
2652 dr
= find_pci_dr(pdev
);
2654 dr
->region_mask
|= 1 << bar
;
2659 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2660 &pdev
->resource
[bar
]);
2665 * pci_request_region - Reserve PCI I/O and memory resource
2666 * @pdev: PCI device whose resources are to be reserved
2667 * @bar: BAR to be reserved
2668 * @res_name: Name to be associated with resource
2670 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2671 * being reserved by owner @res_name. Do not access any
2672 * address inside the PCI regions unless this call returns
2675 * Returns 0 on success, or %EBUSY on error. A warning
2676 * message is also printed on failure.
2678 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2680 return __pci_request_region(pdev
, bar
, res_name
, 0);
2684 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2685 * @pdev: PCI device whose resources are to be reserved
2686 * @bar: BAR to be reserved
2687 * @res_name: Name to be associated with resource.
2689 * Mark the PCI region associated with PCI device @pdev BR @bar as
2690 * being reserved by owner @res_name. Do not access any
2691 * address inside the PCI regions unless this call returns
2694 * Returns 0 on success, or %EBUSY on error. A warning
2695 * message is also printed on failure.
2697 * The key difference that _exclusive makes it that userspace is
2698 * explicitly not allowed to map the resource via /dev/mem or
2701 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2703 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2706 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2707 * @pdev: PCI device whose resources were previously reserved
2708 * @bars: Bitmask of BARs to be released
2710 * Release selected PCI I/O and memory resources previously reserved.
2711 * Call this function only after all use of the PCI regions has ceased.
2713 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2717 for (i
= 0; i
< 6; i
++)
2718 if (bars
& (1 << i
))
2719 pci_release_region(pdev
, i
);
2722 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2723 const char *res_name
, int excl
)
2727 for (i
= 0; i
< 6; i
++)
2728 if (bars
& (1 << i
))
2729 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2735 if (bars
& (1 << i
))
2736 pci_release_region(pdev
, i
);
2743 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2744 * @pdev: PCI device whose resources are to be reserved
2745 * @bars: Bitmask of BARs to be requested
2746 * @res_name: Name to be associated with resource
2748 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2749 const char *res_name
)
2751 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2754 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2755 int bars
, const char *res_name
)
2757 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2758 IORESOURCE_EXCLUSIVE
);
2762 * pci_release_regions - Release reserved PCI I/O and memory resources
2763 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2765 * Releases all PCI I/O and memory resources previously reserved by a
2766 * successful call to pci_request_regions. Call this function only
2767 * after all use of the PCI regions has ceased.
2770 void pci_release_regions(struct pci_dev
*pdev
)
2772 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2776 * pci_request_regions - Reserved PCI I/O and memory resources
2777 * @pdev: PCI device whose resources are to be reserved
2778 * @res_name: Name to be associated with resource.
2780 * Mark all PCI regions associated with PCI device @pdev as
2781 * being reserved by owner @res_name. Do not access any
2782 * address inside the PCI regions unless this call returns
2785 * Returns 0 on success, or %EBUSY on error. A warning
2786 * message is also printed on failure.
2788 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2790 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2794 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2795 * @pdev: PCI device whose resources are to be reserved
2796 * @res_name: Name to be associated with resource.
2798 * Mark all PCI regions associated with PCI device @pdev as
2799 * being reserved by owner @res_name. Do not access any
2800 * address inside the PCI regions unless this call returns
2803 * pci_request_regions_exclusive() will mark the region so that
2804 * /dev/mem and the sysfs MMIO access will not be allowed.
2806 * Returns 0 on success, or %EBUSY on error. A warning
2807 * message is also printed on failure.
2809 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2811 return pci_request_selected_regions_exclusive(pdev
,
2812 ((1 << 6) - 1), res_name
);
2815 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2819 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2821 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2823 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2824 if (cmd
!= old_cmd
) {
2825 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2826 enable
? "enabling" : "disabling");
2827 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2829 dev
->is_busmaster
= enable
;
2833 * pcibios_setup - process "pci=" kernel boot arguments
2834 * @str: string used to pass in "pci=" kernel boot arguments
2836 * Process kernel boot arguments. This is the default implementation.
2837 * Architecture specific implementations can override this as necessary.
2839 char * __weak __init
pcibios_setup(char *str
)
2845 * pcibios_set_master - enable PCI bus-mastering for device dev
2846 * @dev: the PCI device to enable
2848 * Enables PCI bus-mastering for the device. This is the default
2849 * implementation. Architecture specific implementations can override
2850 * this if necessary.
2852 void __weak
pcibios_set_master(struct pci_dev
*dev
)
2856 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2857 if (pci_is_pcie(dev
))
2860 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
2862 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
2863 else if (lat
> pcibios_max_latency
)
2864 lat
= pcibios_max_latency
;
2867 dev_printk(KERN_DEBUG
, &dev
->dev
, "setting latency timer to %d\n", lat
);
2868 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
2872 * pci_set_master - enables bus-mastering for device dev
2873 * @dev: the PCI device to enable
2875 * Enables bus-mastering on the device and calls pcibios_set_master()
2876 * to do the needed arch specific settings.
2878 void pci_set_master(struct pci_dev
*dev
)
2880 __pci_set_master(dev
, true);
2881 pcibios_set_master(dev
);
2885 * pci_clear_master - disables bus-mastering for device dev
2886 * @dev: the PCI device to disable
2888 void pci_clear_master(struct pci_dev
*dev
)
2890 __pci_set_master(dev
, false);
2894 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2895 * @dev: the PCI device for which MWI is to be enabled
2897 * Helper function for pci_set_mwi.
2898 * Originally copied from drivers/net/acenic.c.
2899 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2901 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2903 int pci_set_cacheline_size(struct pci_dev
*dev
)
2907 if (!pci_cache_line_size
)
2910 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2911 equal to or multiple of the right value. */
2912 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2913 if (cacheline_size
>= pci_cache_line_size
&&
2914 (cacheline_size
% pci_cache_line_size
) == 0)
2917 /* Write the correct value. */
2918 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2920 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2921 if (cacheline_size
== pci_cache_line_size
)
2924 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2925 "supported\n", pci_cache_line_size
<< 2);
2929 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2931 #ifdef PCI_DISABLE_MWI
2932 int pci_set_mwi(struct pci_dev
*dev
)
2937 int pci_try_set_mwi(struct pci_dev
*dev
)
2942 void pci_clear_mwi(struct pci_dev
*dev
)
2949 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2950 * @dev: the PCI device for which MWI is enabled
2952 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2954 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2957 pci_set_mwi(struct pci_dev
*dev
)
2962 rc
= pci_set_cacheline_size(dev
);
2966 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2967 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2968 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2969 cmd
|= PCI_COMMAND_INVALIDATE
;
2970 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2977 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2978 * @dev: the PCI device for which MWI is enabled
2980 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2981 * Callers are not required to check the return value.
2983 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2985 int pci_try_set_mwi(struct pci_dev
*dev
)
2987 int rc
= pci_set_mwi(dev
);
2992 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2993 * @dev: the PCI device to disable
2995 * Disables PCI Memory-Write-Invalidate transaction on the device
2998 pci_clear_mwi(struct pci_dev
*dev
)
3002 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3003 if (cmd
& PCI_COMMAND_INVALIDATE
) {
3004 cmd
&= ~PCI_COMMAND_INVALIDATE
;
3005 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3008 #endif /* ! PCI_DISABLE_MWI */
3011 * pci_intx - enables/disables PCI INTx for device dev
3012 * @pdev: the PCI device to operate on
3013 * @enable: boolean: whether to enable or disable PCI INTx
3015 * Enables/disables PCI INTx for device dev
3018 pci_intx(struct pci_dev
*pdev
, int enable
)
3020 u16 pci_command
, new;
3022 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
3025 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
3027 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
3030 if (new != pci_command
) {
3031 struct pci_devres
*dr
;
3033 pci_write_config_word(pdev
, PCI_COMMAND
, new);
3035 dr
= find_pci_dr(pdev
);
3036 if (dr
&& !dr
->restore_intx
) {
3037 dr
->restore_intx
= 1;
3038 dr
->orig_intx
= !enable
;
3044 * pci_intx_mask_supported - probe for INTx masking support
3045 * @dev: the PCI device to operate on
3047 * Check if the device dev support INTx masking via the config space
3050 bool pci_intx_mask_supported(struct pci_dev
*dev
)
3052 bool mask_supported
= false;
3055 if (dev
->broken_intx_masking
)
3058 pci_cfg_access_lock(dev
);
3060 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
3061 pci_write_config_word(dev
, PCI_COMMAND
,
3062 orig
^ PCI_COMMAND_INTX_DISABLE
);
3063 pci_read_config_word(dev
, PCI_COMMAND
, &new);
3066 * There's no way to protect against hardware bugs or detect them
3067 * reliably, but as long as we know what the value should be, let's
3068 * go ahead and check it.
3070 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
3071 dev_err(&dev
->dev
, "Command register changed from "
3072 "0x%x to 0x%x: driver or hardware bug?\n", orig
, new);
3073 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
3074 mask_supported
= true;
3075 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
3078 pci_cfg_access_unlock(dev
);
3079 return mask_supported
;
3081 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
3083 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3085 struct pci_bus
*bus
= dev
->bus
;
3086 bool mask_updated
= true;
3087 u32 cmd_status_dword
;
3088 u16 origcmd
, newcmd
;
3089 unsigned long flags
;
3093 * We do a single dword read to retrieve both command and status.
3094 * Document assumptions that make this possible.
3096 BUILD_BUG_ON(PCI_COMMAND
% 4);
3097 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3099 raw_spin_lock_irqsave(&pci_lock
, flags
);
3101 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3103 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3106 * Check interrupt status register to see whether our device
3107 * triggered the interrupt (when masking) or the next IRQ is
3108 * already pending (when unmasking).
3110 if (mask
!= irq_pending
) {
3111 mask_updated
= false;
3115 origcmd
= cmd_status_dword
;
3116 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3118 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3119 if (newcmd
!= origcmd
)
3120 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3123 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3125 return mask_updated
;
3129 * pci_check_and_mask_intx - mask INTx on pending interrupt
3130 * @dev: the PCI device to operate on
3132 * Check if the device dev has its INTx line asserted, mask it and
3133 * return true in that case. False is returned if not interrupt was
3136 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3138 return pci_check_and_set_intx_mask(dev
, true);
3140 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3143 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
3144 * @dev: the PCI device to operate on
3146 * Check if the device dev has its INTx line asserted, unmask it if not
3147 * and return true. False is returned and the mask remains active if
3148 * there was still an interrupt pending.
3150 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3152 return pci_check_and_set_intx_mask(dev
, false);
3154 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3157 * pci_msi_off - disables any msi or msix capabilities
3158 * @dev: the PCI device to operate on
3160 * If you want to use msi see pci_enable_msi and friends.
3161 * This is a lower level primitive that allows us to disable
3162 * msi operation at the device level.
3164 void pci_msi_off(struct pci_dev
*dev
)
3169 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
3171 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
3172 control
&= ~PCI_MSI_FLAGS_ENABLE
;
3173 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
3175 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
3177 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
3178 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
3179 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
3182 EXPORT_SYMBOL_GPL(pci_msi_off
);
3184 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
3186 return dma_set_max_seg_size(&dev
->dev
, size
);
3188 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
3190 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
3192 return dma_set_seg_boundary(&dev
->dev
, mask
);
3194 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
3196 static int pcie_flr(struct pci_dev
*dev
, int probe
)
3201 u16 status
, control
;
3203 pos
= pci_pcie_cap(dev
);
3207 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
3208 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3214 /* Wait for Transaction Pending bit clean */
3215 for (i
= 0; i
< 4; i
++) {
3217 msleep((1 << (i
- 1)) * 100);
3219 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
3220 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
3224 dev_err(&dev
->dev
, "transaction is not cleared; "
3225 "proceeding with reset anyway\n");
3228 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &control
);
3229 control
|= PCI_EXP_DEVCTL_BCR_FLR
;
3230 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, control
);
3237 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3244 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3248 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3249 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3255 /* Wait for Transaction Pending bit clean */
3256 for (i
= 0; i
< 4; i
++) {
3258 msleep((1 << (i
- 1)) * 100);
3260 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
3261 if (!(status
& PCI_AF_STATUS_TP
))
3265 dev_err(&dev
->dev
, "transaction is not cleared; "
3266 "proceeding with reset anyway\n");
3269 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3276 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3277 * @dev: Device to reset.
3278 * @probe: If set, only check if the device can be reset this way.
3280 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3281 * unset, it will be reinitialized internally when going from PCI_D3hot to
3282 * PCI_D0. If that's the case and the device is not in a low-power state
3283 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3285 * NOTE: This causes the caller to sleep for twice the device power transition
3286 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3287 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3288 * Moreover, only devices in D0 can be reset by this function.
3290 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3297 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3298 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3304 if (dev
->current_state
!= PCI_D0
)
3307 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3309 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3310 pci_dev_d3_sleep(dev
);
3312 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3314 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3315 pci_dev_d3_sleep(dev
);
3320 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3323 struct pci_dev
*pdev
;
3325 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
3328 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3335 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
3336 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3337 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
3340 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3341 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
3347 static int __pci_dev_reset(struct pci_dev
*dev
, int probe
)
3353 rc
= pci_dev_specific_reset(dev
, probe
);
3357 rc
= pcie_flr(dev
, probe
);
3361 rc
= pci_af_flr(dev
, probe
);
3365 rc
= pci_pm_reset(dev
, probe
);
3369 rc
= pci_parent_bus_reset(dev
, probe
);
3374 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3379 pci_cfg_access_lock(dev
);
3380 /* block PM suspend, driver probe, etc. */
3381 device_lock(&dev
->dev
);
3384 rc
= __pci_dev_reset(dev
, probe
);
3387 device_unlock(&dev
->dev
);
3388 pci_cfg_access_unlock(dev
);
3393 * __pci_reset_function - reset a PCI device function
3394 * @dev: PCI device to reset
3396 * Some devices allow an individual function to be reset without affecting
3397 * other functions in the same device. The PCI device must be responsive
3398 * to PCI config space in order to use this function.
3400 * The device function is presumed to be unused when this function is called.
3401 * Resetting the device will make the contents of PCI configuration space
3402 * random, so any caller of this must be prepared to reinitialise the
3403 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3406 * Returns 0 if the device function was successfully reset or negative if the
3407 * device doesn't support resetting a single function.
3409 int __pci_reset_function(struct pci_dev
*dev
)
3411 return pci_dev_reset(dev
, 0);
3413 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3416 * __pci_reset_function_locked - reset a PCI device function while holding
3417 * the @dev mutex lock.
3418 * @dev: PCI device to reset
3420 * Some devices allow an individual function to be reset without affecting
3421 * other functions in the same device. The PCI device must be responsive
3422 * to PCI config space in order to use this function.
3424 * The device function is presumed to be unused and the caller is holding
3425 * the device mutex lock when this function is called.
3426 * Resetting the device will make the contents of PCI configuration space
3427 * random, so any caller of this must be prepared to reinitialise the
3428 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3431 * Returns 0 if the device function was successfully reset or negative if the
3432 * device doesn't support resetting a single function.
3434 int __pci_reset_function_locked(struct pci_dev
*dev
)
3436 return __pci_dev_reset(dev
, 0);
3438 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3441 * pci_probe_reset_function - check whether the device can be safely reset
3442 * @dev: PCI device to reset
3444 * Some devices allow an individual function to be reset without affecting
3445 * other functions in the same device. The PCI device must be responsive
3446 * to PCI config space in order to use this function.
3448 * Returns 0 if the device function can be reset or negative if the
3449 * device doesn't support resetting a single function.
3451 int pci_probe_reset_function(struct pci_dev
*dev
)
3453 return pci_dev_reset(dev
, 1);
3457 * pci_reset_function - quiesce and reset a PCI device function
3458 * @dev: PCI device to reset
3460 * Some devices allow an individual function to be reset without affecting
3461 * other functions in the same device. The PCI device must be responsive
3462 * to PCI config space in order to use this function.
3464 * This function does not just reset the PCI portion of a device, but
3465 * clears all the state associated with the device. This function differs
3466 * from __pci_reset_function in that it saves and restores device state
3469 * Returns 0 if the device function was successfully reset or negative if the
3470 * device doesn't support resetting a single function.
3472 int pci_reset_function(struct pci_dev
*dev
)
3476 rc
= pci_dev_reset(dev
, 1);
3480 pci_save_state(dev
);
3483 * both INTx and MSI are disabled after the Interrupt Disable bit
3484 * is set and the Bus Master bit is cleared.
3486 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3488 rc
= pci_dev_reset(dev
, 0);
3490 pci_restore_state(dev
);
3494 EXPORT_SYMBOL_GPL(pci_reset_function
);
3497 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3498 * @dev: PCI device to query
3500 * Returns mmrbc: maximum designed memory read count in bytes
3501 * or appropriate error value.
3503 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
3508 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3512 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3515 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
3517 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
3520 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3521 * @dev: PCI device to query
3523 * Returns mmrbc: maximum memory read count in bytes
3524 * or appropriate error value.
3526 int pcix_get_mmrbc(struct pci_dev
*dev
)
3531 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3535 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3538 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
3540 EXPORT_SYMBOL(pcix_get_mmrbc
);
3543 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3544 * @dev: PCI device to query
3545 * @mmrbc: maximum memory read count in bytes
3546 * valid values are 512, 1024, 2048, 4096
3548 * If possible sets maximum memory read byte count, some bridges have erratas
3549 * that prevent this.
3551 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
3557 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
3560 v
= ffs(mmrbc
) - 10;
3562 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3566 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3569 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
3572 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3575 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
3577 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
3580 cmd
&= ~PCI_X_CMD_MAX_READ
;
3582 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
3587 EXPORT_SYMBOL(pcix_set_mmrbc
);
3590 * pcie_get_readrq - get PCI Express read request size
3591 * @dev: PCI device to query
3593 * Returns maximum memory read request in bytes
3594 * or appropriate error value.
3596 int pcie_get_readrq(struct pci_dev
*dev
)
3601 cap
= pci_pcie_cap(dev
);
3605 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3607 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
3611 EXPORT_SYMBOL(pcie_get_readrq
);
3614 * pcie_set_readrq - set PCI Express maximum memory read request
3615 * @dev: PCI device to query
3616 * @rq: maximum memory read count in bytes
3617 * valid values are 128, 256, 512, 1024, 2048, 4096
3619 * If possible sets maximum memory read request in bytes
3621 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
3623 int cap
, err
= -EINVAL
;
3626 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
3629 cap
= pci_pcie_cap(dev
);
3633 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3637 * If using the "performance" PCIe config, we clamp the
3638 * read rq size to the max packet size to prevent the
3639 * host bridge generating requests larger than we can
3642 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
3643 int mps
= pcie_get_mps(dev
);
3651 v
= (ffs(rq
) - 8) << 12;
3653 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
3654 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
3656 err
= pci_write_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3662 EXPORT_SYMBOL(pcie_set_readrq
);
3665 * pcie_get_mps - get PCI Express maximum payload size
3666 * @dev: PCI device to query
3668 * Returns maximum payload size in bytes
3669 * or appropriate error value.
3671 int pcie_get_mps(struct pci_dev
*dev
)
3676 cap
= pci_pcie_cap(dev
);
3680 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3682 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
3688 * pcie_set_mps - set PCI Express maximum payload size
3689 * @dev: PCI device to query
3690 * @mps: maximum payload size in bytes
3691 * valid values are 128, 256, 512, 1024, 2048, 4096
3693 * If possible sets maximum payload size
3695 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
3697 int cap
, err
= -EINVAL
;
3700 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
3704 if (v
> dev
->pcie_mpss
)
3708 cap
= pci_pcie_cap(dev
);
3712 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3716 if ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) != v
) {
3717 ctl
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
3719 err
= pci_write_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3726 * pci_select_bars - Make BAR mask from the type of resource
3727 * @dev: the PCI device for which BAR mask is made
3728 * @flags: resource type mask to be selected
3730 * This helper routine makes bar mask from the type of resource.
3732 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
3735 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
3736 if (pci_resource_flags(dev
, i
) & flags
)
3742 * pci_resource_bar - get position of the BAR associated with a resource
3743 * @dev: the PCI device
3744 * @resno: the resource number
3745 * @type: the BAR type to be filled in
3747 * Returns BAR position in config space, or 0 if the BAR is invalid.
3749 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
3753 if (resno
< PCI_ROM_RESOURCE
) {
3754 *type
= pci_bar_unknown
;
3755 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
3756 } else if (resno
== PCI_ROM_RESOURCE
) {
3757 *type
= pci_bar_mem32
;
3758 return dev
->rom_base_reg
;
3759 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
3760 /* device specific resource */
3761 reg
= pci_iov_resource_bar(dev
, resno
, type
);
3766 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
3770 /* Some architectures require additional programming to enable VGA */
3771 static arch_set_vga_state_t arch_set_vga_state
;
3773 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
3775 arch_set_vga_state
= func
; /* NULL disables */
3778 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
3779 unsigned int command_bits
, u32 flags
)
3781 if (arch_set_vga_state
)
3782 return arch_set_vga_state(dev
, decode
, command_bits
,
3788 * pci_set_vga_state - set VGA decode state on device and parents if requested
3789 * @dev: the PCI device
3790 * @decode: true = enable decoding, false = disable decoding
3791 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3792 * @flags: traverse ancestors and change bridges
3793 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3795 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
3796 unsigned int command_bits
, u32 flags
)
3798 struct pci_bus
*bus
;
3799 struct pci_dev
*bridge
;
3803 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) & (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
3805 /* ARCH specific VGA enables */
3806 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
3810 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
3811 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3813 cmd
|= command_bits
;
3815 cmd
&= ~command_bits
;
3816 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3819 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
3826 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3829 cmd
|= PCI_BRIDGE_CTL_VGA
;
3831 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
3832 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3840 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3841 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
3842 static DEFINE_SPINLOCK(resource_alignment_lock
);
3845 * pci_specified_resource_alignment - get resource alignment specified by user.
3846 * @dev: the PCI device to get
3848 * RETURNS: Resource alignment if it is specified.
3849 * Zero if it is not specified.
3851 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
3853 int seg
, bus
, slot
, func
, align_order
, count
;
3854 resource_size_t align
= 0;
3857 spin_lock(&resource_alignment_lock
);
3858 p
= resource_alignment_param
;
3861 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
3867 if (sscanf(p
, "%x:%x:%x.%x%n",
3868 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
3870 if (sscanf(p
, "%x:%x.%x%n",
3871 &bus
, &slot
, &func
, &count
) != 3) {
3872 /* Invalid format */
3873 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
3879 if (seg
== pci_domain_nr(dev
->bus
) &&
3880 bus
== dev
->bus
->number
&&
3881 slot
== PCI_SLOT(dev
->devfn
) &&
3882 func
== PCI_FUNC(dev
->devfn
)) {
3883 if (align_order
== -1) {
3886 align
= 1 << align_order
;
3891 if (*p
!= ';' && *p
!= ',') {
3892 /* End of param or invalid format */
3897 spin_unlock(&resource_alignment_lock
);
3902 * pci_is_reassigndev - check if specified PCI is target device to reassign
3903 * @dev: the PCI device to check
3905 * RETURNS: non-zero for PCI device is a target device to reassign,
3908 int pci_is_reassigndev(struct pci_dev
*dev
)
3910 return (pci_specified_resource_alignment(dev
) != 0);
3914 * This function disables memory decoding and releases memory resources
3915 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3916 * It also rounds up size to specified alignment.
3917 * Later on, the kernel will assign page-aligned memory resource back
3920 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
3924 resource_size_t align
, size
;
3927 if (!pci_is_reassigndev(dev
))
3930 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
3931 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
3933 "Can't reassign resources to host bridge.\n");
3938 "Disabling memory decoding and releasing memory resources.\n");
3939 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
3940 command
&= ~PCI_COMMAND_MEMORY
;
3941 pci_write_config_word(dev
, PCI_COMMAND
, command
);
3943 align
= pci_specified_resource_alignment(dev
);
3944 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
3945 r
= &dev
->resource
[i
];
3946 if (!(r
->flags
& IORESOURCE_MEM
))
3948 size
= resource_size(r
);
3952 "Rounding up size of resource #%d to %#llx.\n",
3953 i
, (unsigned long long)size
);
3958 /* Need to disable bridge's resource window,
3959 * to enable the kernel to reassign new resource
3962 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
3963 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
3964 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
3965 r
= &dev
->resource
[i
];
3966 if (!(r
->flags
& IORESOURCE_MEM
))
3968 r
->end
= resource_size(r
) - 1;
3971 pci_disable_bridge_window(dev
);
3975 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
3977 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
3978 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
3979 spin_lock(&resource_alignment_lock
);
3980 strncpy(resource_alignment_param
, buf
, count
);
3981 resource_alignment_param
[count
] = '\0';
3982 spin_unlock(&resource_alignment_lock
);
3986 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
3989 spin_lock(&resource_alignment_lock
);
3990 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
3991 spin_unlock(&resource_alignment_lock
);
3995 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
3997 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
4000 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
4001 const char *buf
, size_t count
)
4003 return pci_set_resource_alignment_param(buf
, count
);
4006 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
4007 pci_resource_alignment_store
);
4009 static int __init
pci_resource_alignment_sysfs_init(void)
4011 return bus_create_file(&pci_bus_type
,
4012 &bus_attr_resource_alignment
);
4015 late_initcall(pci_resource_alignment_sysfs_init
);
4017 static void __devinit
pci_no_domains(void)
4019 #ifdef CONFIG_PCI_DOMAINS
4020 pci_domains_supported
= 0;
4025 * pci_ext_cfg_enabled - can we access extended PCI config space?
4026 * @dev: The PCI device of the root bridge.
4028 * Returns 1 if we can access PCI extended config space (offsets
4029 * greater than 0xff). This is the default implementation. Architecture
4030 * implementations can override this.
4032 int __weak
pci_ext_cfg_avail(struct pci_dev
*dev
)
4037 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
4040 EXPORT_SYMBOL(pci_fixup_cardbus
);
4042 static int __init
pci_setup(char *str
)
4045 char *k
= strchr(str
, ',');
4048 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
4049 if (!strcmp(str
, "nomsi")) {
4051 } else if (!strcmp(str
, "noaer")) {
4053 } else if (!strncmp(str
, "realloc=", 8)) {
4054 pci_realloc_get_opt(str
+ 8);
4055 } else if (!strncmp(str
, "realloc", 7)) {
4056 pci_realloc_get_opt("on");
4057 } else if (!strcmp(str
, "nodomains")) {
4059 } else if (!strncmp(str
, "noari", 5)) {
4060 pcie_ari_disabled
= true;
4061 } else if (!strncmp(str
, "cbiosize=", 9)) {
4062 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
4063 } else if (!strncmp(str
, "cbmemsize=", 10)) {
4064 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
4065 } else if (!strncmp(str
, "resource_alignment=", 19)) {
4066 pci_set_resource_alignment_param(str
+ 19,
4068 } else if (!strncmp(str
, "ecrc=", 5)) {
4069 pcie_ecrc_get_policy(str
+ 5);
4070 } else if (!strncmp(str
, "hpiosize=", 9)) {
4071 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
4072 } else if (!strncmp(str
, "hpmemsize=", 10)) {
4073 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
4074 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
4075 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
4076 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
4077 pcie_bus_config
= PCIE_BUS_SAFE
;
4078 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
4079 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
4080 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
4081 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
4082 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
4083 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
4085 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
4093 early_param("pci", pci_setup
);
4095 EXPORT_SYMBOL(pci_reenable_device
);
4096 EXPORT_SYMBOL(pci_enable_device_io
);
4097 EXPORT_SYMBOL(pci_enable_device_mem
);
4098 EXPORT_SYMBOL(pci_enable_device
);
4099 EXPORT_SYMBOL(pcim_enable_device
);
4100 EXPORT_SYMBOL(pcim_pin_device
);
4101 EXPORT_SYMBOL(pci_disable_device
);
4102 EXPORT_SYMBOL(pci_find_capability
);
4103 EXPORT_SYMBOL(pci_bus_find_capability
);
4104 EXPORT_SYMBOL(pci_release_regions
);
4105 EXPORT_SYMBOL(pci_request_regions
);
4106 EXPORT_SYMBOL(pci_request_regions_exclusive
);
4107 EXPORT_SYMBOL(pci_release_region
);
4108 EXPORT_SYMBOL(pci_request_region
);
4109 EXPORT_SYMBOL(pci_request_region_exclusive
);
4110 EXPORT_SYMBOL(pci_release_selected_regions
);
4111 EXPORT_SYMBOL(pci_request_selected_regions
);
4112 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
4113 EXPORT_SYMBOL(pci_set_master
);
4114 EXPORT_SYMBOL(pci_clear_master
);
4115 EXPORT_SYMBOL(pci_set_mwi
);
4116 EXPORT_SYMBOL(pci_try_set_mwi
);
4117 EXPORT_SYMBOL(pci_clear_mwi
);
4118 EXPORT_SYMBOL_GPL(pci_intx
);
4119 EXPORT_SYMBOL(pci_assign_resource
);
4120 EXPORT_SYMBOL(pci_find_parent_resource
);
4121 EXPORT_SYMBOL(pci_select_bars
);
4123 EXPORT_SYMBOL(pci_set_power_state
);
4124 EXPORT_SYMBOL(pci_save_state
);
4125 EXPORT_SYMBOL(pci_restore_state
);
4126 EXPORT_SYMBOL(pci_pme_capable
);
4127 EXPORT_SYMBOL(pci_pme_active
);
4128 EXPORT_SYMBOL(pci_wake_from_d3
);
4129 EXPORT_SYMBOL(pci_target_state
);
4130 EXPORT_SYMBOL(pci_prepare_to_sleep
);
4131 EXPORT_SYMBOL(pci_back_from_sleep
);
4132 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);