2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names
[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names
);
35 int isa_dma_bridge_buggy
;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
39 EXPORT_SYMBOL(pci_pci_problems
);
41 unsigned int pci_pm_d3_delay
;
43 static void pci_pme_list_scan(struct work_struct
*work
);
45 static LIST_HEAD(pci_pme_list
);
46 static DEFINE_MUTEX(pci_pme_list_mutex
);
47 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
49 struct pci_pme_device
{
50 struct list_head list
;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
58 unsigned int delay
= dev
->d3_delay
;
60 if (delay
< pci_pm_d3_delay
)
61 delay
= pci_pm_d3_delay
;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported
= 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
74 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
80 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
82 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
91 u8 pci_cache_line_size
;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency
= 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled
;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
111 struct list_head
*tmp
;
112 unsigned char max
, n
;
114 max
= bus
->busn_res
.end
;
115 list_for_each(tmp
, &bus
->children
) {
116 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
134 return ioremap_nocache(pci_resource_start(pdev
, bar
),
135 pci_resource_len(pdev
, bar
));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
143 u8 pos
, int cap
, int *ttl
)
148 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
152 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
158 pos
+= PCI_CAP_LIST_NEXT
;
163 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
166 int ttl
= PCI_FIND_CAP_TTL
;
168 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
171 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
173 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
174 pos
+ PCI_CAP_LIST_NEXT
, cap
);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
178 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
179 unsigned int devfn
, u8 hdr_type
)
183 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
184 if (!(status
& PCI_STATUS_CAP_LIST
))
188 case PCI_HEADER_TYPE_NORMAL
:
189 case PCI_HEADER_TYPE_BRIDGE
:
190 return PCI_CAPABILITY_LIST
;
191 case PCI_HEADER_TYPE_CARDBUS
:
192 return PCI_CB_CAPABILITY_LIST
;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev
*dev
, int cap
)
223 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
225 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
243 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
248 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
250 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
252 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
268 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
272 int pos
= PCI_CFG_SPACE_SIZE
;
274 /* minimum 8 bytes per capability */
275 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
277 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
283 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
294 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
297 pos
= PCI_EXT_CAP_NEXT(header
);
298 if (pos
< PCI_CFG_SPACE_SIZE
)
301 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
323 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
325 return pci_find_next_ext_capability(dev
, 0, cap
);
327 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
329 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
331 int rc
, ttl
= PCI_FIND_CAP_TTL
;
334 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
335 mask
= HT_3BIT_CAP_MASK
;
337 mask
= HT_5BIT_CAP_MASK
;
339 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
340 PCI_CAP_ID_HT
, &ttl
);
342 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
343 if (rc
!= PCIBIOS_SUCCESSFUL
)
346 if ((cap
& mask
) == ht_cap
)
349 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
350 pos
+ PCI_CAP_LIST_NEXT
,
351 PCI_CAP_ID_HT
, &ttl
);
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
369 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
371 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
386 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
390 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
392 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
396 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in.
407 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
409 const struct pci_bus
*bus
= dev
->bus
;
413 pci_bus_for_each_resource(bus
, r
, i
) {
416 if (res
->start
&& resource_contains(r
, res
)) {
419 * If the window is prefetchable but the BAR is
420 * not, the allocator made a mistake.
422 if (r
->flags
& IORESOURCE_PREFETCH
&&
423 !(res
->flags
& IORESOURCE_PREFETCH
))
427 * If we're below a transparent bridge, there may
428 * be both a positively-decoded aperture and a
429 * subtractively-decoded region that contain the BAR.
430 * We want the positively-decoded one, so this depends
431 * on pci_bus_for_each_resource() giving us those
441 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
442 * @dev: the PCI device to operate on
443 * @pos: config space offset of status word
444 * @mask: mask of bit(s) to care about in status word
446 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
448 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
452 /* Wait for Transaction Pending bit clean */
453 for (i
= 0; i
< 4; i
++) {
456 msleep((1 << (i
- 1)) * 100);
458 pci_read_config_word(dev
, pos
, &status
);
459 if (!(status
& mask
))
467 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
468 * @dev: PCI device to have its BARs restored
470 * Restore the BAR values for a given device, so as to make it
471 * accessible by its driver.
474 pci_restore_bars(struct pci_dev
*dev
)
478 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
479 pci_update_resource(dev
, i
);
482 static struct pci_platform_pm_ops
*pci_platform_pm
;
484 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
486 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
489 pci_platform_pm
= ops
;
493 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
495 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
498 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
501 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
504 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
506 return pci_platform_pm
?
507 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
510 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
512 return pci_platform_pm
?
513 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
516 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
518 return pci_platform_pm
?
519 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
523 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
525 * @dev: PCI device to handle.
526 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
529 * -EINVAL if the requested state is invalid.
530 * -EIO if device does not support PCI PM or its PM capabilities register has a
531 * wrong version, or device doesn't support the requested state.
532 * 0 if device already is in the requested state.
533 * 0 if device's power state has been successfully changed.
535 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
538 bool need_restore
= false;
540 /* Check if we're already there */
541 if (dev
->current_state
== state
)
547 if (state
< PCI_D0
|| state
> PCI_D3hot
)
550 /* Validate current state:
551 * Can enter D0 from any state, but if we can only go deeper
552 * to sleep if we're already in a low power state
554 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
555 && dev
->current_state
> state
) {
556 dev_err(&dev
->dev
, "invalid power transition "
557 "(from state %d to %d)\n", dev
->current_state
, state
);
561 /* check if this device supports the desired state */
562 if ((state
== PCI_D1
&& !dev
->d1_support
)
563 || (state
== PCI_D2
&& !dev
->d2_support
))
566 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
568 /* If we're (effectively) in D3, force entire word to 0.
569 * This doesn't affect PME_Status, disables PME_En, and
570 * sets PowerState to 0.
572 switch (dev
->current_state
) {
576 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
581 case PCI_UNKNOWN
: /* Boot-up */
582 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
583 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
585 /* Fall-through: force to D0 */
591 /* enter specified state */
592 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
594 /* Mandatory power management transition delays */
595 /* see PCI PM 1.1 5.6.1 table 18 */
596 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
597 pci_dev_d3_sleep(dev
);
598 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
599 udelay(PCI_PM_D2_DELAY
);
601 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
602 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
603 if (dev
->current_state
!= state
&& printk_ratelimit())
604 dev_info(&dev
->dev
, "Refused to change power state, "
605 "currently in D%d\n", dev
->current_state
);
608 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
609 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
610 * from D3hot to D0 _may_ perform an internal reset, thereby
611 * going to "D0 Uninitialized" rather than "D0 Initialized".
612 * For example, at least some versions of the 3c905B and the
613 * 3c556B exhibit this behaviour.
615 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
616 * devices in a D3hot state at boot. Consequently, we need to
617 * restore at least the BARs so that the device will be
618 * accessible to its driver.
621 pci_restore_bars(dev
);
624 pcie_aspm_pm_state_change(dev
->bus
->self
);
630 * pci_update_current_state - Read PCI power state of given device from its
631 * PCI PM registers and cache it
632 * @dev: PCI device to handle.
633 * @state: State to cache in case the device doesn't have the PM capability
635 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
641 * Configuration space is not accessible for device in
642 * D3cold, so just keep or set D3cold for safety
644 if (dev
->current_state
== PCI_D3cold
)
646 if (state
== PCI_D3cold
) {
647 dev
->current_state
= PCI_D3cold
;
650 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
651 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
653 dev
->current_state
= state
;
658 * pci_power_up - Put the given device into D0 forcibly
659 * @dev: PCI device to power up
661 void pci_power_up(struct pci_dev
*dev
)
663 if (platform_pci_power_manageable(dev
))
664 platform_pci_set_power_state(dev
, PCI_D0
);
666 pci_raw_set_power_state(dev
, PCI_D0
);
667 pci_update_current_state(dev
, PCI_D0
);
671 * pci_platform_power_transition - Use platform to change device power state
672 * @dev: PCI device to handle.
673 * @state: State to put the device into.
675 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
679 if (platform_pci_power_manageable(dev
)) {
680 error
= platform_pci_set_power_state(dev
, state
);
682 pci_update_current_state(dev
, state
);
686 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
687 dev
->current_state
= PCI_D0
;
693 * pci_wakeup - Wake up a PCI device
694 * @pci_dev: Device to handle.
695 * @ign: ignored parameter
697 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
699 pci_wakeup_event(pci_dev
);
700 pm_request_resume(&pci_dev
->dev
);
705 * pci_wakeup_bus - Walk given bus and wake up devices on it
706 * @bus: Top bus of the subtree to walk.
708 static void pci_wakeup_bus(struct pci_bus
*bus
)
711 pci_walk_bus(bus
, pci_wakeup
, NULL
);
715 * __pci_start_power_transition - Start power transition of a PCI device
716 * @dev: PCI device to handle.
717 * @state: State to put the device into.
719 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
721 if (state
== PCI_D0
) {
722 pci_platform_power_transition(dev
, PCI_D0
);
724 * Mandatory power management transition delays, see
725 * PCI Express Base Specification Revision 2.0 Section
726 * 6.6.1: Conventional Reset. Do not delay for
727 * devices powered on/off by corresponding bridge,
728 * because have already delayed for the bridge.
730 if (dev
->runtime_d3cold
) {
731 msleep(dev
->d3cold_delay
);
733 * When powering on a bridge from D3cold, the
734 * whole hierarchy may be powered on into
735 * D0uninitialized state, resume them to give
736 * them a chance to suspend again
738 pci_wakeup_bus(dev
->subordinate
);
744 * __pci_dev_set_current_state - Set current state of a PCI device
745 * @dev: Device to handle
746 * @data: pointer to state to be set
748 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
750 pci_power_t state
= *(pci_power_t
*)data
;
752 dev
->current_state
= state
;
757 * __pci_bus_set_current_state - Walk given bus and set current state of devices
758 * @bus: Top bus of the subtree to walk.
759 * @state: state to be set
761 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
764 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
768 * __pci_complete_power_transition - Complete power transition of a PCI device
769 * @dev: PCI device to handle.
770 * @state: State to put the device into.
772 * This function should not be called directly by device drivers.
774 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
780 ret
= pci_platform_power_transition(dev
, state
);
781 /* Power off the bridge may power off the whole hierarchy */
782 if (!ret
&& state
== PCI_D3cold
)
783 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
786 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
789 * pci_set_power_state - Set the power state of a PCI device
790 * @dev: PCI device to handle.
791 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
793 * Transition a device to a new power state, using the platform firmware and/or
794 * the device's PCI PM registers.
797 * -EINVAL if the requested state is invalid.
798 * -EIO if device does not support PCI PM or its PM capabilities register has a
799 * wrong version, or device doesn't support the requested state.
800 * 0 if device already is in the requested state.
801 * 0 if device's power state has been successfully changed.
803 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
807 /* bound the state we're entering */
808 if (state
> PCI_D3cold
)
810 else if (state
< PCI_D0
)
812 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
814 * If the device or the parent bridge do not support PCI PM,
815 * ignore the request if we're doing anything other than putting
816 * it into D0 (which would only happen on boot).
820 /* Check if we're already there */
821 if (dev
->current_state
== state
)
824 __pci_start_power_transition(dev
, state
);
826 /* This device is quirked not to be put into D3, so
827 don't put it in D3 */
828 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
832 * To put device in D3cold, we put device into D3hot in native
833 * way, then put device into D3cold with platform ops
835 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
838 if (!__pci_complete_power_transition(dev
, state
))
841 * When aspm_policy is "powersave" this call ensures
842 * that ASPM is configured.
844 if (!error
&& dev
->bus
->self
)
845 pcie_aspm_powersave_config_link(dev
->bus
->self
);
851 * pci_choose_state - Choose the power state of a PCI device
852 * @dev: PCI device to be suspended
853 * @state: target sleep state for the whole system. This is the value
854 * that is passed to suspend() function.
856 * Returns PCI power state suitable for given device and given system
860 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
867 ret
= platform_pci_choose_state(dev
);
868 if (ret
!= PCI_POWER_ERROR
)
871 switch (state
.event
) {
874 case PM_EVENT_FREEZE
:
875 case PM_EVENT_PRETHAW
:
876 /* REVISIT both freeze and pre-thaw "should" use D0 */
877 case PM_EVENT_SUSPEND
:
878 case PM_EVENT_HIBERNATE
:
881 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
888 EXPORT_SYMBOL(pci_choose_state
);
890 #define PCI_EXP_SAVE_REGS 7
893 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
894 u16 cap
, bool extended
)
896 struct pci_cap_saved_state
*tmp
;
898 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
899 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
905 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
907 return _pci_find_saved_cap(dev
, cap
, false);
910 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
912 return _pci_find_saved_cap(dev
, cap
, true);
915 static int pci_save_pcie_state(struct pci_dev
*dev
)
918 struct pci_cap_saved_state
*save_state
;
921 if (!pci_is_pcie(dev
))
924 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
926 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
930 cap
= (u16
*)&save_state
->cap
.data
[0];
931 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
932 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
933 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
934 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
935 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
936 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
937 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
942 static void pci_restore_pcie_state(struct pci_dev
*dev
)
945 struct pci_cap_saved_state
*save_state
;
948 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
952 cap
= (u16
*)&save_state
->cap
.data
[0];
953 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
954 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
955 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
956 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
957 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
958 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
959 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
963 static int pci_save_pcix_state(struct pci_dev
*dev
)
966 struct pci_cap_saved_state
*save_state
;
968 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
972 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
974 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
978 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
979 (u16
*)save_state
->cap
.data
);
984 static void pci_restore_pcix_state(struct pci_dev
*dev
)
987 struct pci_cap_saved_state
*save_state
;
990 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
991 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
992 if (!save_state
|| pos
<= 0)
994 cap
= (u16
*)&save_state
->cap
.data
[0];
996 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1001 * pci_save_state - save the PCI configuration space of a device before suspending
1002 * @dev: - PCI device that we're dealing with
1005 pci_save_state(struct pci_dev
*dev
)
1008 /* XXX: 100% dword access ok here? */
1009 for (i
= 0; i
< 16; i
++)
1010 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1011 dev
->state_saved
= true;
1012 if ((i
= pci_save_pcie_state(dev
)) != 0)
1014 if ((i
= pci_save_pcix_state(dev
)) != 0)
1016 if ((i
= pci_save_vc_state(dev
)) != 0)
1021 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1022 u32 saved_val
, int retry
)
1026 pci_read_config_dword(pdev
, offset
, &val
);
1027 if (val
== saved_val
)
1031 dev_dbg(&pdev
->dev
, "restoring config space at offset "
1032 "%#x (was %#x, writing %#x)\n", offset
, val
, saved_val
);
1033 pci_write_config_dword(pdev
, offset
, saved_val
);
1037 pci_read_config_dword(pdev
, offset
, &val
);
1038 if (val
== saved_val
)
1045 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1046 int start
, int end
, int retry
)
1050 for (index
= end
; index
>= start
; index
--)
1051 pci_restore_config_dword(pdev
, 4 * index
,
1052 pdev
->saved_config_space
[index
],
1056 static void pci_restore_config_space(struct pci_dev
*pdev
)
1058 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1059 pci_restore_config_space_range(pdev
, 10, 15, 0);
1060 /* Restore BARs before the command register. */
1061 pci_restore_config_space_range(pdev
, 4, 9, 10);
1062 pci_restore_config_space_range(pdev
, 0, 3, 0);
1064 pci_restore_config_space_range(pdev
, 0, 15, 0);
1069 * pci_restore_state - Restore the saved state of a PCI device
1070 * @dev: - PCI device that we're dealing with
1072 void pci_restore_state(struct pci_dev
*dev
)
1074 if (!dev
->state_saved
)
1077 /* PCI Express register must be restored first */
1078 pci_restore_pcie_state(dev
);
1079 pci_restore_ats_state(dev
);
1080 pci_restore_vc_state(dev
);
1082 pci_restore_config_space(dev
);
1084 pci_restore_pcix_state(dev
);
1085 pci_restore_msi_state(dev
);
1086 pci_restore_iov_state(dev
);
1088 dev
->state_saved
= false;
1091 struct pci_saved_state
{
1092 u32 config_space
[16];
1093 struct pci_cap_saved_data cap
[0];
1097 * pci_store_saved_state - Allocate and return an opaque struct containing
1098 * the device saved state.
1099 * @dev: PCI device that we're dealing with
1101 * Return NULL if no state or error.
1103 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1105 struct pci_saved_state
*state
;
1106 struct pci_cap_saved_state
*tmp
;
1107 struct pci_cap_saved_data
*cap
;
1110 if (!dev
->state_saved
)
1113 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1115 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1116 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1118 state
= kzalloc(size
, GFP_KERNEL
);
1122 memcpy(state
->config_space
, dev
->saved_config_space
,
1123 sizeof(state
->config_space
));
1126 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1127 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1128 memcpy(cap
, &tmp
->cap
, len
);
1129 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1131 /* Empty cap_save terminates list */
1135 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1138 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1139 * @dev: PCI device that we're dealing with
1140 * @state: Saved state returned from pci_store_saved_state()
1142 static int pci_load_saved_state(struct pci_dev
*dev
,
1143 struct pci_saved_state
*state
)
1145 struct pci_cap_saved_data
*cap
;
1147 dev
->state_saved
= false;
1152 memcpy(dev
->saved_config_space
, state
->config_space
,
1153 sizeof(state
->config_space
));
1157 struct pci_cap_saved_state
*tmp
;
1159 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1160 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1163 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1164 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1165 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1168 dev
->state_saved
= true;
1173 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1174 * and free the memory allocated for it.
1175 * @dev: PCI device that we're dealing with
1176 * @state: Pointer to saved state returned from pci_store_saved_state()
1178 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1179 struct pci_saved_state
**state
)
1181 int ret
= pci_load_saved_state(dev
, *state
);
1186 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1188 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1192 err
= pci_set_power_state(dev
, PCI_D0
);
1193 if (err
< 0 && err
!= -EIO
)
1195 err
= pcibios_enable_device(dev
, bars
);
1198 pci_fixup_device(pci_fixup_enable
, dev
);
1204 * pci_reenable_device - Resume abandoned device
1205 * @dev: PCI device to be resumed
1207 * Note this function is a backend of pci_default_resume and is not supposed
1208 * to be called by normal code, write proper resume handler and use it instead.
1210 int pci_reenable_device(struct pci_dev
*dev
)
1212 if (pci_is_enabled(dev
))
1213 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1217 static void pci_enable_bridge(struct pci_dev
*dev
)
1219 struct pci_dev
*bridge
;
1222 bridge
= pci_upstream_bridge(dev
);
1224 pci_enable_bridge(bridge
);
1226 if (pci_is_enabled(dev
)) {
1227 if (!dev
->is_busmaster
)
1228 pci_set_master(dev
);
1232 retval
= pci_enable_device(dev
);
1234 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1236 pci_set_master(dev
);
1239 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1241 struct pci_dev
*bridge
;
1246 * Power state could be unknown at this point, either due to a fresh
1247 * boot or a device removal call. So get the current power state
1248 * so that things like MSI message writing will behave as expected
1249 * (e.g. if the device really is in D0 at enable time).
1253 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1254 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1257 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1258 return 0; /* already enabled */
1260 bridge
= pci_upstream_bridge(dev
);
1262 pci_enable_bridge(bridge
);
1264 /* only skip sriov related */
1265 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1266 if (dev
->resource
[i
].flags
& flags
)
1268 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1269 if (dev
->resource
[i
].flags
& flags
)
1272 err
= do_pci_enable_device(dev
, bars
);
1274 atomic_dec(&dev
->enable_cnt
);
1279 * pci_enable_device_io - Initialize a device for use with IO space
1280 * @dev: PCI device to be initialized
1282 * Initialize device before it's used by a driver. Ask low-level code
1283 * to enable I/O resources. Wake up the device if it was suspended.
1284 * Beware, this function can fail.
1286 int pci_enable_device_io(struct pci_dev
*dev
)
1288 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1292 * pci_enable_device_mem - Initialize a device for use with Memory space
1293 * @dev: PCI device to be initialized
1295 * Initialize device before it's used by a driver. Ask low-level code
1296 * to enable Memory resources. Wake up the device if it was suspended.
1297 * Beware, this function can fail.
1299 int pci_enable_device_mem(struct pci_dev
*dev
)
1301 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1305 * pci_enable_device - Initialize device before it's used by a driver.
1306 * @dev: PCI device to be initialized
1308 * Initialize device before it's used by a driver. Ask low-level code
1309 * to enable I/O and memory. Wake up the device if it was suspended.
1310 * Beware, this function can fail.
1312 * Note we don't actually enable the device many times if we call
1313 * this function repeatedly (we just increment the count).
1315 int pci_enable_device(struct pci_dev
*dev
)
1317 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1321 * Managed PCI resources. This manages device on/off, intx/msi/msix
1322 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1323 * there's no need to track it separately. pci_devres is initialized
1324 * when a device is enabled using managed PCI device enable interface.
1327 unsigned int enabled
:1;
1328 unsigned int pinned
:1;
1329 unsigned int orig_intx
:1;
1330 unsigned int restore_intx
:1;
1334 static void pcim_release(struct device
*gendev
, void *res
)
1336 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1337 struct pci_devres
*this = res
;
1340 if (dev
->msi_enabled
)
1341 pci_disable_msi(dev
);
1342 if (dev
->msix_enabled
)
1343 pci_disable_msix(dev
);
1345 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1346 if (this->region_mask
& (1 << i
))
1347 pci_release_region(dev
, i
);
1349 if (this->restore_intx
)
1350 pci_intx(dev
, this->orig_intx
);
1352 if (this->enabled
&& !this->pinned
)
1353 pci_disable_device(dev
);
1356 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1358 struct pci_devres
*dr
, *new_dr
;
1360 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1364 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1367 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1370 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1372 if (pci_is_managed(pdev
))
1373 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1378 * pcim_enable_device - Managed pci_enable_device()
1379 * @pdev: PCI device to be initialized
1381 * Managed pci_enable_device().
1383 int pcim_enable_device(struct pci_dev
*pdev
)
1385 struct pci_devres
*dr
;
1388 dr
= get_pci_dr(pdev
);
1394 rc
= pci_enable_device(pdev
);
1396 pdev
->is_managed
= 1;
1403 * pcim_pin_device - Pin managed PCI device
1404 * @pdev: PCI device to pin
1406 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1407 * driver detach. @pdev must have been enabled with
1408 * pcim_enable_device().
1410 void pcim_pin_device(struct pci_dev
*pdev
)
1412 struct pci_devres
*dr
;
1414 dr
= find_pci_dr(pdev
);
1415 WARN_ON(!dr
|| !dr
->enabled
);
1421 * pcibios_add_device - provide arch specific hooks when adding device dev
1422 * @dev: the PCI device being added
1424 * Permits the platform to provide architecture specific functionality when
1425 * devices are added. This is the default implementation. Architecture
1426 * implementations can override this.
1428 int __weak
pcibios_add_device (struct pci_dev
*dev
)
1434 * pcibios_release_device - provide arch specific hooks when releasing device dev
1435 * @dev: the PCI device being released
1437 * Permits the platform to provide architecture specific functionality when
1438 * devices are released. This is the default implementation. Architecture
1439 * implementations can override this.
1441 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1444 * pcibios_disable_device - disable arch specific PCI resources for device dev
1445 * @dev: the PCI device to disable
1447 * Disables architecture specific PCI resources for the device. This
1448 * is the default implementation. Architecture implementations can
1451 void __weak
pcibios_disable_device (struct pci_dev
*dev
) {}
1453 static void do_pci_disable_device(struct pci_dev
*dev
)
1457 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1458 if (pci_command
& PCI_COMMAND_MASTER
) {
1459 pci_command
&= ~PCI_COMMAND_MASTER
;
1460 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1463 pcibios_disable_device(dev
);
1467 * pci_disable_enabled_device - Disable device without updating enable_cnt
1468 * @dev: PCI device to disable
1470 * NOTE: This function is a backend of PCI power management routines and is
1471 * not supposed to be called drivers.
1473 void pci_disable_enabled_device(struct pci_dev
*dev
)
1475 if (pci_is_enabled(dev
))
1476 do_pci_disable_device(dev
);
1480 * pci_disable_device - Disable PCI device after use
1481 * @dev: PCI device to be disabled
1483 * Signal to the system that the PCI device is not in use by the system
1484 * anymore. This only involves disabling PCI bus-mastering, if active.
1486 * Note we don't actually disable the device until all callers of
1487 * pci_enable_device() have called pci_disable_device().
1490 pci_disable_device(struct pci_dev
*dev
)
1492 struct pci_devres
*dr
;
1494 dr
= find_pci_dr(dev
);
1498 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1499 "disabling already-disabled device");
1501 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1504 do_pci_disable_device(dev
);
1506 dev
->is_busmaster
= 0;
1510 * pcibios_set_pcie_reset_state - set reset state for device dev
1511 * @dev: the PCIe device reset
1512 * @state: Reset state to enter into
1515 * Sets the PCIe reset state for the device. This is the default
1516 * implementation. Architecture implementations can override this.
1518 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1519 enum pcie_reset_state state
)
1525 * pci_set_pcie_reset_state - set reset state for device dev
1526 * @dev: the PCIe device reset
1527 * @state: Reset state to enter into
1530 * Sets the PCI reset state for the device.
1532 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1534 return pcibios_set_pcie_reset_state(dev
, state
);
1538 * pci_check_pme_status - Check if given device has generated PME.
1539 * @dev: Device to check.
1541 * Check the PME status of the device and if set, clear it and clear PME enable
1542 * (if set). Return 'true' if PME status and PME enable were both set or
1543 * 'false' otherwise.
1545 bool pci_check_pme_status(struct pci_dev
*dev
)
1554 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1555 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1556 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1559 /* Clear PME status. */
1560 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1561 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1562 /* Disable PME to avoid interrupt flood. */
1563 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1567 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1573 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1574 * @dev: Device to handle.
1575 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1577 * Check if @dev has generated PME and queue a resume request for it in that
1580 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1582 if (pme_poll_reset
&& dev
->pme_poll
)
1583 dev
->pme_poll
= false;
1585 if (pci_check_pme_status(dev
)) {
1586 pci_wakeup_event(dev
);
1587 pm_request_resume(&dev
->dev
);
1593 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1594 * @bus: Top bus of the subtree to walk.
1596 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1599 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1604 * pci_pme_capable - check the capability of PCI device to generate PME#
1605 * @dev: PCI device to handle.
1606 * @state: PCI state from which device will issue PME#.
1608 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1613 return !!(dev
->pme_support
& (1 << state
));
1616 static void pci_pme_list_scan(struct work_struct
*work
)
1618 struct pci_pme_device
*pme_dev
, *n
;
1620 mutex_lock(&pci_pme_list_mutex
);
1621 if (!list_empty(&pci_pme_list
)) {
1622 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1623 if (pme_dev
->dev
->pme_poll
) {
1624 struct pci_dev
*bridge
;
1626 bridge
= pme_dev
->dev
->bus
->self
;
1628 * If bridge is in low power state, the
1629 * configuration space of subordinate devices
1630 * may be not accessible
1632 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1634 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1636 list_del(&pme_dev
->list
);
1640 if (!list_empty(&pci_pme_list
))
1641 schedule_delayed_work(&pci_pme_work
,
1642 msecs_to_jiffies(PME_TIMEOUT
));
1644 mutex_unlock(&pci_pme_list_mutex
);
1648 * pci_pme_active - enable or disable PCI device's PME# function
1649 * @dev: PCI device to handle.
1650 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1652 * The caller must verify that the device is capable of generating PME# before
1653 * calling this function with @enable equal to 'true'.
1655 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1659 if (!dev
->pme_support
)
1662 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1663 /* Clear PME_Status by writing 1 to it and enable PME# */
1664 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1666 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1668 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1671 * PCI (as opposed to PCIe) PME requires that the device have
1672 * its PME# line hooked up correctly. Not all hardware vendors
1673 * do this, so the PME never gets delivered and the device
1674 * remains asleep. The easiest way around this is to
1675 * periodically walk the list of suspended devices and check
1676 * whether any have their PME flag set. The assumption is that
1677 * we'll wake up often enough anyway that this won't be a huge
1678 * hit, and the power savings from the devices will still be a
1681 * Although PCIe uses in-band PME message instead of PME# line
1682 * to report PME, PME does not work for some PCIe devices in
1683 * reality. For example, there are devices that set their PME
1684 * status bits, but don't really bother to send a PME message;
1685 * there are PCI Express Root Ports that don't bother to
1686 * trigger interrupts when they receive PME messages from the
1687 * devices below. So PME poll is used for PCIe devices too.
1690 if (dev
->pme_poll
) {
1691 struct pci_pme_device
*pme_dev
;
1693 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1696 dev_warn(&dev
->dev
, "can't enable PME#\n");
1700 mutex_lock(&pci_pme_list_mutex
);
1701 list_add(&pme_dev
->list
, &pci_pme_list
);
1702 if (list_is_singular(&pci_pme_list
))
1703 schedule_delayed_work(&pci_pme_work
,
1704 msecs_to_jiffies(PME_TIMEOUT
));
1705 mutex_unlock(&pci_pme_list_mutex
);
1707 mutex_lock(&pci_pme_list_mutex
);
1708 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1709 if (pme_dev
->dev
== dev
) {
1710 list_del(&pme_dev
->list
);
1715 mutex_unlock(&pci_pme_list_mutex
);
1719 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1723 * __pci_enable_wake - enable PCI device as wakeup event source
1724 * @dev: PCI device affected
1725 * @state: PCI state from which device will issue wakeup events
1726 * @runtime: True if the events are to be generated at run time
1727 * @enable: True to enable event generation; false to disable
1729 * This enables the device as a wakeup event source, or disables it.
1730 * When such events involves platform-specific hooks, those hooks are
1731 * called automatically by this routine.
1733 * Devices with legacy power management (no standard PCI PM capabilities)
1734 * always require such platform hooks.
1737 * 0 is returned on success
1738 * -EINVAL is returned if device is not supposed to wake up the system
1739 * Error code depending on the platform is returned if both the platform and
1740 * the native mechanism fail to enable the generation of wake-up events
1742 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1743 bool runtime
, bool enable
)
1747 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1750 /* Don't do the same thing twice in a row for one device. */
1751 if (!!enable
== !!dev
->wakeup_prepared
)
1755 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1756 * Anderson we should be doing PME# wake enable followed by ACPI wake
1757 * enable. To disable wake-up we call the platform first, for symmetry.
1763 if (pci_pme_capable(dev
, state
))
1764 pci_pme_active(dev
, true);
1767 error
= runtime
? platform_pci_run_wake(dev
, true) :
1768 platform_pci_sleep_wake(dev
, true);
1772 dev
->wakeup_prepared
= true;
1775 platform_pci_run_wake(dev
, false);
1777 platform_pci_sleep_wake(dev
, false);
1778 pci_pme_active(dev
, false);
1779 dev
->wakeup_prepared
= false;
1784 EXPORT_SYMBOL(__pci_enable_wake
);
1787 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1788 * @dev: PCI device to prepare
1789 * @enable: True to enable wake-up event generation; false to disable
1791 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1792 * and this function allows them to set that up cleanly - pci_enable_wake()
1793 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1794 * ordering constraints.
1796 * This function only returns error code if the device is not capable of
1797 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1798 * enable wake-up power for it.
1800 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1802 return pci_pme_capable(dev
, PCI_D3cold
) ?
1803 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1804 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1808 * pci_target_state - find an appropriate low power state for a given PCI dev
1811 * Use underlying platform code to find a supported low power state for @dev.
1812 * If the platform can't manage @dev, return the deepest state from which it
1813 * can generate wake events, based on any available PME info.
1815 static pci_power_t
pci_target_state(struct pci_dev
*dev
)
1817 pci_power_t target_state
= PCI_D3hot
;
1819 if (platform_pci_power_manageable(dev
)) {
1821 * Call the platform to choose the target state of the device
1822 * and enable wake-up from this state if supported.
1824 pci_power_t state
= platform_pci_choose_state(dev
);
1827 case PCI_POWER_ERROR
:
1832 if (pci_no_d1d2(dev
))
1835 target_state
= state
;
1837 } else if (!dev
->pm_cap
) {
1838 target_state
= PCI_D0
;
1839 } else if (device_may_wakeup(&dev
->dev
)) {
1841 * Find the deepest state from which the device can generate
1842 * wake-up events, make it the target state and enable device
1845 if (dev
->pme_support
) {
1847 && !(dev
->pme_support
& (1 << target_state
)))
1852 return target_state
;
1856 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1857 * @dev: Device to handle.
1859 * Choose the power state appropriate for the device depending on whether
1860 * it can wake up the system and/or is power manageable by the platform
1861 * (PCI_D3hot is the default) and put the device into that state.
1863 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1865 pci_power_t target_state
= pci_target_state(dev
);
1868 if (target_state
== PCI_POWER_ERROR
)
1871 /* D3cold during system suspend/hibernate is not supported */
1872 if (target_state
> PCI_D3hot
)
1873 target_state
= PCI_D3hot
;
1875 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1877 error
= pci_set_power_state(dev
, target_state
);
1880 pci_enable_wake(dev
, target_state
, false);
1886 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1887 * @dev: Device to handle.
1889 * Disable device's system wake-up capability and put it into D0.
1891 int pci_back_from_sleep(struct pci_dev
*dev
)
1893 pci_enable_wake(dev
, PCI_D0
, false);
1894 return pci_set_power_state(dev
, PCI_D0
);
1898 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1899 * @dev: PCI device being suspended.
1901 * Prepare @dev to generate wake-up events at run time and put it into a low
1904 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1906 pci_power_t target_state
= pci_target_state(dev
);
1909 if (target_state
== PCI_POWER_ERROR
)
1912 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
1914 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1916 error
= pci_set_power_state(dev
, target_state
);
1919 __pci_enable_wake(dev
, target_state
, true, false);
1920 dev
->runtime_d3cold
= false;
1927 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1928 * @dev: Device to check.
1930 * Return true if the device itself is capable of generating wake-up events
1931 * (through the platform or using the native PCIe PME) or if the device supports
1932 * PME and one of its upstream bridges can generate wake-up events.
1934 bool pci_dev_run_wake(struct pci_dev
*dev
)
1936 struct pci_bus
*bus
= dev
->bus
;
1938 if (device_run_wake(&dev
->dev
))
1941 if (!dev
->pme_support
)
1944 while (bus
->parent
) {
1945 struct pci_dev
*bridge
= bus
->self
;
1947 if (device_run_wake(&bridge
->dev
))
1953 /* We have reached the root bus. */
1955 return device_run_wake(bus
->bridge
);
1959 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1961 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
1963 struct device
*dev
= &pdev
->dev
;
1964 struct device
*parent
= dev
->parent
;
1967 pm_runtime_get_sync(parent
);
1968 pm_runtime_get_noresume(dev
);
1970 * pdev->current_state is set to PCI_D3cold during suspending,
1971 * so wait until suspending completes
1973 pm_runtime_barrier(dev
);
1975 * Only need to resume devices in D3cold, because config
1976 * registers are still accessible for devices suspended but
1979 if (pdev
->current_state
== PCI_D3cold
)
1980 pm_runtime_resume(dev
);
1983 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
1985 struct device
*dev
= &pdev
->dev
;
1986 struct device
*parent
= dev
->parent
;
1988 pm_runtime_put(dev
);
1990 pm_runtime_put_sync(parent
);
1994 * pci_pm_init - Initialize PM functions of given PCI device
1995 * @dev: PCI device to handle.
1997 void pci_pm_init(struct pci_dev
*dev
)
2002 pm_runtime_forbid(&dev
->dev
);
2003 pm_runtime_set_active(&dev
->dev
);
2004 pm_runtime_enable(&dev
->dev
);
2005 device_enable_async_suspend(&dev
->dev
);
2006 dev
->wakeup_prepared
= false;
2009 dev
->pme_support
= 0;
2011 /* find PCI PM capability in list */
2012 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2015 /* Check device's ability to generate PME# */
2016 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2018 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2019 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2020 pmc
& PCI_PM_CAP_VER_MASK
);
2025 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2026 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2027 dev
->d3cold_allowed
= true;
2029 dev
->d1_support
= false;
2030 dev
->d2_support
= false;
2031 if (!pci_no_d1d2(dev
)) {
2032 if (pmc
& PCI_PM_CAP_D1
)
2033 dev
->d1_support
= true;
2034 if (pmc
& PCI_PM_CAP_D2
)
2035 dev
->d2_support
= true;
2037 if (dev
->d1_support
|| dev
->d2_support
)
2038 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2039 dev
->d1_support
? " D1" : "",
2040 dev
->d2_support
? " D2" : "");
2043 pmc
&= PCI_PM_CAP_PME_MASK
;
2045 dev_printk(KERN_DEBUG
, &dev
->dev
,
2046 "PME# supported from%s%s%s%s%s\n",
2047 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2048 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2049 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2050 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2051 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2052 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2053 dev
->pme_poll
= true;
2055 * Make device's PM flags reflect the wake-up capability, but
2056 * let the user space enable it to wake up the system as needed.
2058 device_set_wakeup_capable(&dev
->dev
, true);
2059 /* Disable the PME# generation functionality */
2060 pci_pme_active(dev
, false);
2064 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2065 struct pci_cap_saved_state
*new_cap
)
2067 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2071 * _pci_add_cap_save_buffer - allocate buffer for saving given
2072 * capability registers
2073 * @dev: the PCI device
2074 * @cap: the capability to allocate the buffer for
2075 * @extended: Standard or Extended capability ID
2076 * @size: requested size of the buffer
2078 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2079 bool extended
, unsigned int size
)
2082 struct pci_cap_saved_state
*save_state
;
2085 pos
= pci_find_ext_capability(dev
, cap
);
2087 pos
= pci_find_capability(dev
, cap
);
2092 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2096 save_state
->cap
.cap_nr
= cap
;
2097 save_state
->cap
.cap_extended
= extended
;
2098 save_state
->cap
.size
= size
;
2099 pci_add_saved_cap(dev
, save_state
);
2104 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2106 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2109 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2111 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2115 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2116 * @dev: the PCI device
2118 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2122 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2123 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2126 "unable to preallocate PCI Express save buffer\n");
2128 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2131 "unable to preallocate PCI-X save buffer\n");
2133 pci_allocate_vc_save_buffers(dev
);
2136 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2138 struct pci_cap_saved_state
*tmp
;
2139 struct hlist_node
*n
;
2141 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2146 * pci_configure_ari - enable or disable ARI forwarding
2147 * @dev: the PCI device
2149 * If @dev and its upstream bridge both support ARI, enable ARI in the
2150 * bridge. Otherwise, disable ARI in the bridge.
2152 void pci_configure_ari(struct pci_dev
*dev
)
2155 struct pci_dev
*bridge
;
2157 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2160 bridge
= dev
->bus
->self
;
2164 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2165 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2168 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2169 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2170 PCI_EXP_DEVCTL2_ARI
);
2171 bridge
->ari_enabled
= 1;
2173 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2174 PCI_EXP_DEVCTL2_ARI
);
2175 bridge
->ari_enabled
= 0;
2179 static int pci_acs_enable
;
2182 * pci_request_acs - ask for ACS to be enabled if supported
2184 void pci_request_acs(void)
2190 * pci_enable_acs - enable ACS if hardware support it
2191 * @dev: the PCI device
2193 void pci_enable_acs(struct pci_dev
*dev
)
2199 if (!pci_acs_enable
)
2202 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2206 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2207 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2209 /* Source Validation */
2210 ctrl
|= (cap
& PCI_ACS_SV
);
2212 /* P2P Request Redirect */
2213 ctrl
|= (cap
& PCI_ACS_RR
);
2215 /* P2P Completion Redirect */
2216 ctrl
|= (cap
& PCI_ACS_CR
);
2218 /* Upstream Forwarding */
2219 ctrl
|= (cap
& PCI_ACS_UF
);
2221 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2224 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2229 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2234 * Except for egress control, capabilities are either required
2235 * or only required if controllable. Features missing from the
2236 * capability field can therefore be assumed as hard-wired enabled.
2238 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2239 acs_flags
&= (cap
| PCI_ACS_EC
);
2241 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2242 return (ctrl
& acs_flags
) == acs_flags
;
2246 * pci_acs_enabled - test ACS against required flags for a given device
2247 * @pdev: device to test
2248 * @acs_flags: required PCI ACS flags
2250 * Return true if the device supports the provided flags. Automatically
2251 * filters out flags that are not implemented on multifunction devices.
2253 * Note that this interface checks the effective ACS capabilities of the
2254 * device rather than the actual capabilities. For instance, most single
2255 * function endpoints are not required to support ACS because they have no
2256 * opportunity for peer-to-peer access. We therefore return 'true'
2257 * regardless of whether the device exposes an ACS capability. This makes
2258 * it much easier for callers of this function to ignore the actual type
2259 * or topology of the device when testing ACS support.
2261 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2265 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2270 * Conventional PCI and PCI-X devices never support ACS, either
2271 * effectively or actually. The shared bus topology implies that
2272 * any device on the bus can receive or snoop DMA.
2274 if (!pci_is_pcie(pdev
))
2277 switch (pci_pcie_type(pdev
)) {
2279 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2280 * but since their primary interface is PCI/X, we conservatively
2281 * handle them as we would a non-PCIe device.
2283 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2285 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2286 * applicable... must never implement an ACS Extended Capability...".
2287 * This seems arbitrary, but we take a conservative interpretation
2288 * of this statement.
2290 case PCI_EXP_TYPE_PCI_BRIDGE
:
2291 case PCI_EXP_TYPE_RC_EC
:
2294 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2295 * implement ACS in order to indicate their peer-to-peer capabilities,
2296 * regardless of whether they are single- or multi-function devices.
2298 case PCI_EXP_TYPE_DOWNSTREAM
:
2299 case PCI_EXP_TYPE_ROOT_PORT
:
2300 return pci_acs_flags_enabled(pdev
, acs_flags
);
2302 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2303 * implemented by the remaining PCIe types to indicate peer-to-peer
2304 * capabilities, but only when they are part of a multifunction
2305 * device. The footnote for section 6.12 indicates the specific
2306 * PCIe types included here.
2308 case PCI_EXP_TYPE_ENDPOINT
:
2309 case PCI_EXP_TYPE_UPSTREAM
:
2310 case PCI_EXP_TYPE_LEG_END
:
2311 case PCI_EXP_TYPE_RC_END
:
2312 if (!pdev
->multifunction
)
2315 return pci_acs_flags_enabled(pdev
, acs_flags
);
2319 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2320 * to single function devices with the exception of downstream ports.
2326 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2327 * @start: starting downstream device
2328 * @end: ending upstream device or NULL to search to the root bus
2329 * @acs_flags: required flags
2331 * Walk up a device tree from start to end testing PCI ACS support. If
2332 * any step along the way does not support the required flags, return false.
2334 bool pci_acs_path_enabled(struct pci_dev
*start
,
2335 struct pci_dev
*end
, u16 acs_flags
)
2337 struct pci_dev
*pdev
, *parent
= start
;
2342 if (!pci_acs_enabled(pdev
, acs_flags
))
2345 if (pci_is_root_bus(pdev
->bus
))
2346 return (end
== NULL
);
2348 parent
= pdev
->bus
->self
;
2349 } while (pdev
!= end
);
2355 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2356 * @dev: the PCI device
2357 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2359 * Perform INTx swizzling for a device behind one level of bridge. This is
2360 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2361 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2362 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2363 * the PCI Express Base Specification, Revision 2.1)
2365 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
2369 if (pci_ari_enabled(dev
->bus
))
2372 slot
= PCI_SLOT(dev
->devfn
);
2374 return (((pin
- 1) + slot
) % 4) + 1;
2378 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2386 while (!pci_is_root_bus(dev
->bus
)) {
2387 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2388 dev
= dev
->bus
->self
;
2395 * pci_common_swizzle - swizzle INTx all the way to root bridge
2396 * @dev: the PCI device
2397 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2399 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2400 * bridges all the way up to a PCI root bus.
2402 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2406 while (!pci_is_root_bus(dev
->bus
)) {
2407 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2408 dev
= dev
->bus
->self
;
2411 return PCI_SLOT(dev
->devfn
);
2415 * pci_release_region - Release a PCI bar
2416 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2417 * @bar: BAR to release
2419 * Releases the PCI I/O and memory resources previously reserved by a
2420 * successful call to pci_request_region. Call this function only
2421 * after all use of the PCI regions has ceased.
2423 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2425 struct pci_devres
*dr
;
2427 if (pci_resource_len(pdev
, bar
) == 0)
2429 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2430 release_region(pci_resource_start(pdev
, bar
),
2431 pci_resource_len(pdev
, bar
));
2432 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2433 release_mem_region(pci_resource_start(pdev
, bar
),
2434 pci_resource_len(pdev
, bar
));
2436 dr
= find_pci_dr(pdev
);
2438 dr
->region_mask
&= ~(1 << bar
);
2442 * __pci_request_region - Reserved PCI I/O and memory resource
2443 * @pdev: PCI device whose resources are to be reserved
2444 * @bar: BAR to be reserved
2445 * @res_name: Name to be associated with resource.
2446 * @exclusive: whether the region access is exclusive or not
2448 * Mark the PCI region associated with PCI device @pdev BR @bar as
2449 * being reserved by owner @res_name. Do not access any
2450 * address inside the PCI regions unless this call returns
2453 * If @exclusive is set, then the region is marked so that userspace
2454 * is explicitly not allowed to map the resource via /dev/mem or
2455 * sysfs MMIO access.
2457 * Returns 0 on success, or %EBUSY on error. A warning
2458 * message is also printed on failure.
2460 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
2463 struct pci_devres
*dr
;
2465 if (pci_resource_len(pdev
, bar
) == 0)
2468 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2469 if (!request_region(pci_resource_start(pdev
, bar
),
2470 pci_resource_len(pdev
, bar
), res_name
))
2473 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2474 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2475 pci_resource_len(pdev
, bar
), res_name
,
2480 dr
= find_pci_dr(pdev
);
2482 dr
->region_mask
|= 1 << bar
;
2487 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2488 &pdev
->resource
[bar
]);
2493 * pci_request_region - Reserve PCI I/O and memory resource
2494 * @pdev: PCI device whose resources are to be reserved
2495 * @bar: BAR to be reserved
2496 * @res_name: Name to be associated with resource
2498 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2499 * being reserved by owner @res_name. Do not access any
2500 * address inside the PCI regions unless this call returns
2503 * Returns 0 on success, or %EBUSY on error. A warning
2504 * message is also printed on failure.
2506 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2508 return __pci_request_region(pdev
, bar
, res_name
, 0);
2512 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2513 * @pdev: PCI device whose resources are to be reserved
2514 * @bar: BAR to be reserved
2515 * @res_name: Name to be associated with resource.
2517 * Mark the PCI region associated with PCI device @pdev BR @bar as
2518 * being reserved by owner @res_name. Do not access any
2519 * address inside the PCI regions unless this call returns
2522 * Returns 0 on success, or %EBUSY on error. A warning
2523 * message is also printed on failure.
2525 * The key difference that _exclusive makes it that userspace is
2526 * explicitly not allowed to map the resource via /dev/mem or
2529 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2531 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2534 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2535 * @pdev: PCI device whose resources were previously reserved
2536 * @bars: Bitmask of BARs to be released
2538 * Release selected PCI I/O and memory resources previously reserved.
2539 * Call this function only after all use of the PCI regions has ceased.
2541 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2545 for (i
= 0; i
< 6; i
++)
2546 if (bars
& (1 << i
))
2547 pci_release_region(pdev
, i
);
2550 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2551 const char *res_name
, int excl
)
2555 for (i
= 0; i
< 6; i
++)
2556 if (bars
& (1 << i
))
2557 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2563 if (bars
& (1 << i
))
2564 pci_release_region(pdev
, i
);
2571 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2572 * @pdev: PCI device whose resources are to be reserved
2573 * @bars: Bitmask of BARs to be requested
2574 * @res_name: Name to be associated with resource
2576 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2577 const char *res_name
)
2579 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2582 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2583 int bars
, const char *res_name
)
2585 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2586 IORESOURCE_EXCLUSIVE
);
2590 * pci_release_regions - Release reserved PCI I/O and memory resources
2591 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2593 * Releases all PCI I/O and memory resources previously reserved by a
2594 * successful call to pci_request_regions. Call this function only
2595 * after all use of the PCI regions has ceased.
2598 void pci_release_regions(struct pci_dev
*pdev
)
2600 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2604 * pci_request_regions - Reserved PCI I/O and memory resources
2605 * @pdev: PCI device whose resources are to be reserved
2606 * @res_name: Name to be associated with resource.
2608 * Mark all PCI regions associated with PCI device @pdev as
2609 * being reserved by owner @res_name. Do not access any
2610 * address inside the PCI regions unless this call returns
2613 * Returns 0 on success, or %EBUSY on error. A warning
2614 * message is also printed on failure.
2616 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2618 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2622 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2623 * @pdev: PCI device whose resources are to be reserved
2624 * @res_name: Name to be associated with resource.
2626 * Mark all PCI regions associated with PCI device @pdev as
2627 * being reserved by owner @res_name. Do not access any
2628 * address inside the PCI regions unless this call returns
2631 * pci_request_regions_exclusive() will mark the region so that
2632 * /dev/mem and the sysfs MMIO access will not be allowed.
2634 * Returns 0 on success, or %EBUSY on error. A warning
2635 * message is also printed on failure.
2637 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2639 return pci_request_selected_regions_exclusive(pdev
,
2640 ((1 << 6) - 1), res_name
);
2643 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2647 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2649 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2651 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2652 if (cmd
!= old_cmd
) {
2653 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2654 enable
? "enabling" : "disabling");
2655 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2657 dev
->is_busmaster
= enable
;
2661 * pcibios_setup - process "pci=" kernel boot arguments
2662 * @str: string used to pass in "pci=" kernel boot arguments
2664 * Process kernel boot arguments. This is the default implementation.
2665 * Architecture specific implementations can override this as necessary.
2667 char * __weak __init
pcibios_setup(char *str
)
2673 * pcibios_set_master - enable PCI bus-mastering for device dev
2674 * @dev: the PCI device to enable
2676 * Enables PCI bus-mastering for the device. This is the default
2677 * implementation. Architecture specific implementations can override
2678 * this if necessary.
2680 void __weak
pcibios_set_master(struct pci_dev
*dev
)
2684 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2685 if (pci_is_pcie(dev
))
2688 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
2690 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
2691 else if (lat
> pcibios_max_latency
)
2692 lat
= pcibios_max_latency
;
2696 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
2700 * pci_set_master - enables bus-mastering for device dev
2701 * @dev: the PCI device to enable
2703 * Enables bus-mastering on the device and calls pcibios_set_master()
2704 * to do the needed arch specific settings.
2706 void pci_set_master(struct pci_dev
*dev
)
2708 __pci_set_master(dev
, true);
2709 pcibios_set_master(dev
);
2713 * pci_clear_master - disables bus-mastering for device dev
2714 * @dev: the PCI device to disable
2716 void pci_clear_master(struct pci_dev
*dev
)
2718 __pci_set_master(dev
, false);
2722 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2723 * @dev: the PCI device for which MWI is to be enabled
2725 * Helper function for pci_set_mwi.
2726 * Originally copied from drivers/net/acenic.c.
2727 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2729 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2731 int pci_set_cacheline_size(struct pci_dev
*dev
)
2735 if (!pci_cache_line_size
)
2738 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2739 equal to or multiple of the right value. */
2740 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2741 if (cacheline_size
>= pci_cache_line_size
&&
2742 (cacheline_size
% pci_cache_line_size
) == 0)
2745 /* Write the correct value. */
2746 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2748 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2749 if (cacheline_size
== pci_cache_line_size
)
2752 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2753 "supported\n", pci_cache_line_size
<< 2);
2757 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2759 #ifdef PCI_DISABLE_MWI
2760 int pci_set_mwi(struct pci_dev
*dev
)
2765 int pci_try_set_mwi(struct pci_dev
*dev
)
2770 void pci_clear_mwi(struct pci_dev
*dev
)
2777 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2778 * @dev: the PCI device for which MWI is enabled
2780 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2782 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2785 pci_set_mwi(struct pci_dev
*dev
)
2790 rc
= pci_set_cacheline_size(dev
);
2794 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2795 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2796 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2797 cmd
|= PCI_COMMAND_INVALIDATE
;
2798 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2805 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2806 * @dev: the PCI device for which MWI is enabled
2808 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2809 * Callers are not required to check the return value.
2811 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2813 int pci_try_set_mwi(struct pci_dev
*dev
)
2815 int rc
= pci_set_mwi(dev
);
2820 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2821 * @dev: the PCI device to disable
2823 * Disables PCI Memory-Write-Invalidate transaction on the device
2826 pci_clear_mwi(struct pci_dev
*dev
)
2830 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2831 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2832 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2833 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2836 #endif /* ! PCI_DISABLE_MWI */
2839 * pci_intx - enables/disables PCI INTx for device dev
2840 * @pdev: the PCI device to operate on
2841 * @enable: boolean: whether to enable or disable PCI INTx
2843 * Enables/disables PCI INTx for device dev
2846 pci_intx(struct pci_dev
*pdev
, int enable
)
2848 u16 pci_command
, new;
2850 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2853 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2855 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2858 if (new != pci_command
) {
2859 struct pci_devres
*dr
;
2861 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2863 dr
= find_pci_dr(pdev
);
2864 if (dr
&& !dr
->restore_intx
) {
2865 dr
->restore_intx
= 1;
2866 dr
->orig_intx
= !enable
;
2872 * pci_intx_mask_supported - probe for INTx masking support
2873 * @dev: the PCI device to operate on
2875 * Check if the device dev support INTx masking via the config space
2878 bool pci_intx_mask_supported(struct pci_dev
*dev
)
2880 bool mask_supported
= false;
2883 if (dev
->broken_intx_masking
)
2886 pci_cfg_access_lock(dev
);
2888 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
2889 pci_write_config_word(dev
, PCI_COMMAND
,
2890 orig
^ PCI_COMMAND_INTX_DISABLE
);
2891 pci_read_config_word(dev
, PCI_COMMAND
, &new);
2894 * There's no way to protect against hardware bugs or detect them
2895 * reliably, but as long as we know what the value should be, let's
2896 * go ahead and check it.
2898 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
2899 dev_err(&dev
->dev
, "Command register changed from "
2900 "0x%x to 0x%x: driver or hardware bug?\n", orig
, new);
2901 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
2902 mask_supported
= true;
2903 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
2906 pci_cfg_access_unlock(dev
);
2907 return mask_supported
;
2909 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
2911 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
2913 struct pci_bus
*bus
= dev
->bus
;
2914 bool mask_updated
= true;
2915 u32 cmd_status_dword
;
2916 u16 origcmd
, newcmd
;
2917 unsigned long flags
;
2921 * We do a single dword read to retrieve both command and status.
2922 * Document assumptions that make this possible.
2924 BUILD_BUG_ON(PCI_COMMAND
% 4);
2925 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
2927 raw_spin_lock_irqsave(&pci_lock
, flags
);
2929 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
2931 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
2934 * Check interrupt status register to see whether our device
2935 * triggered the interrupt (when masking) or the next IRQ is
2936 * already pending (when unmasking).
2938 if (mask
!= irq_pending
) {
2939 mask_updated
= false;
2943 origcmd
= cmd_status_dword
;
2944 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
2946 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
2947 if (newcmd
!= origcmd
)
2948 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
2951 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
2953 return mask_updated
;
2957 * pci_check_and_mask_intx - mask INTx on pending interrupt
2958 * @dev: the PCI device to operate on
2960 * Check if the device dev has its INTx line asserted, mask it and
2961 * return true in that case. False is returned if not interrupt was
2964 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
2966 return pci_check_and_set_intx_mask(dev
, true);
2968 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
2971 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
2972 * @dev: the PCI device to operate on
2974 * Check if the device dev has its INTx line asserted, unmask it if not
2975 * and return true. False is returned and the mask remains active if
2976 * there was still an interrupt pending.
2978 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
2980 return pci_check_and_set_intx_mask(dev
, false);
2982 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
2985 * pci_msi_off - disables any MSI or MSI-X capabilities
2986 * @dev: the PCI device to operate on
2988 * If you want to use MSI, see pci_enable_msi() and friends.
2989 * This is a lower-level primitive that allows us to disable
2990 * MSI operation at the device level.
2992 void pci_msi_off(struct pci_dev
*dev
)
2998 * This looks like it could go in msi.c, but we need it even when
2999 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3000 * dev->msi_cap or dev->msix_cap here.
3002 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
3004 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
3005 control
&= ~PCI_MSI_FLAGS_ENABLE
;
3006 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
3008 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
3010 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
3011 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
3012 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
3015 EXPORT_SYMBOL_GPL(pci_msi_off
);
3017 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
3019 return dma_set_max_seg_size(&dev
->dev
, size
);
3021 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
3023 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
3025 return dma_set_seg_boundary(&dev
->dev
, mask
);
3027 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
3030 * pci_wait_for_pending_transaction - waits for pending transaction
3031 * @dev: the PCI device to operate on
3033 * Return 0 if transaction is pending 1 otherwise.
3035 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3037 if (!pci_is_pcie(dev
))
3040 return pci_wait_for_pending(dev
, PCI_EXP_DEVSTA
, PCI_EXP_DEVSTA_TRPND
);
3042 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3044 static int pcie_flr(struct pci_dev
*dev
, int probe
)
3048 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
3049 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3055 if (!pci_wait_for_pending_transaction(dev
))
3056 dev_err(&dev
->dev
, "transaction is not cleared; proceeding with reset anyway\n");
3058 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3065 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3070 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3074 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3075 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3081 /* Wait for Transaction Pending bit clean */
3082 if (pci_wait_for_pending(dev
, PCI_AF_STATUS
, PCI_AF_STATUS_TP
))
3085 dev_err(&dev
->dev
, "transaction is not cleared; "
3086 "proceeding with reset anyway\n");
3089 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3096 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3097 * @dev: Device to reset.
3098 * @probe: If set, only check if the device can be reset this way.
3100 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3101 * unset, it will be reinitialized internally when going from PCI_D3hot to
3102 * PCI_D0. If that's the case and the device is not in a low-power state
3103 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3105 * NOTE: This causes the caller to sleep for twice the device power transition
3106 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3107 * by default (i.e. unless the @dev's d3_delay field has a different value).
3108 * Moreover, only devices in D0 can be reset by this function.
3110 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3117 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3118 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3124 if (dev
->current_state
!= PCI_D0
)
3127 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3129 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3130 pci_dev_d3_sleep(dev
);
3132 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3134 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3135 pci_dev_d3_sleep(dev
);
3141 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3142 * @dev: Bridge device
3144 * Use the bridge control register to assert reset on the secondary bus.
3145 * Devices on the secondary bus are left in power-on state.
3147 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
3151 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
3152 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3153 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3155 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3156 * this to 2ms to ensure that we meet the minimum requirement.
3160 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3161 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3164 * Trhfa for conventional PCI is 2^25 clock cycles.
3165 * Assuming a minimum 33MHz clock this results in a 1s
3166 * delay before we can consider subordinate devices to
3167 * be re-initialized. PCIe has some ways to shorten this,
3168 * but we don't make use of them yet.
3172 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
3174 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3176 struct pci_dev
*pdev
;
3178 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
3181 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3188 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
3193 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
3197 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
3200 if (hotplug
->ops
->reset_slot
)
3201 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
3203 module_put(hotplug
->ops
->owner
);
3208 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
3210 struct pci_dev
*pdev
;
3212 if (dev
->subordinate
|| !dev
->slot
)
3215 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3216 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
3219 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
3222 static int __pci_dev_reset(struct pci_dev
*dev
, int probe
)
3228 rc
= pci_dev_specific_reset(dev
, probe
);
3232 rc
= pcie_flr(dev
, probe
);
3236 rc
= pci_af_flr(dev
, probe
);
3240 rc
= pci_pm_reset(dev
, probe
);
3244 rc
= pci_dev_reset_slot_function(dev
, probe
);
3248 rc
= pci_parent_bus_reset(dev
, probe
);
3253 static void pci_dev_lock(struct pci_dev
*dev
)
3255 pci_cfg_access_lock(dev
);
3256 /* block PM suspend, driver probe, etc. */
3257 device_lock(&dev
->dev
);
3260 /* Return 1 on successful lock, 0 on contention */
3261 static int pci_dev_trylock(struct pci_dev
*dev
)
3263 if (pci_cfg_access_trylock(dev
)) {
3264 if (device_trylock(&dev
->dev
))
3266 pci_cfg_access_unlock(dev
);
3272 static void pci_dev_unlock(struct pci_dev
*dev
)
3274 device_unlock(&dev
->dev
);
3275 pci_cfg_access_unlock(dev
);
3278 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
3281 * Wake-up device prior to save. PM registers default to D0 after
3282 * reset and a simple register restore doesn't reliably return
3283 * to a non-D0 state anyway.
3285 pci_set_power_state(dev
, PCI_D0
);
3287 pci_save_state(dev
);
3289 * Disable the device by clearing the Command register, except for
3290 * INTx-disable which is set. This not only disables MMIO and I/O port
3291 * BARs, but also prevents the device from being Bus Master, preventing
3292 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3293 * compliant devices, INTx-disable prevents legacy interrupts.
3295 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3298 static void pci_dev_restore(struct pci_dev
*dev
)
3300 pci_restore_state(dev
);
3303 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3310 rc
= __pci_dev_reset(dev
, probe
);
3313 pci_dev_unlock(dev
);
3318 * __pci_reset_function - reset a PCI device function
3319 * @dev: PCI device to reset
3321 * Some devices allow an individual function to be reset without affecting
3322 * other functions in the same device. The PCI device must be responsive
3323 * to PCI config space in order to use this function.
3325 * The device function is presumed to be unused when this function is called.
3326 * Resetting the device will make the contents of PCI configuration space
3327 * random, so any caller of this must be prepared to reinitialise the
3328 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3331 * Returns 0 if the device function was successfully reset or negative if the
3332 * device doesn't support resetting a single function.
3334 int __pci_reset_function(struct pci_dev
*dev
)
3336 return pci_dev_reset(dev
, 0);
3338 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3341 * __pci_reset_function_locked - reset a PCI device function while holding
3342 * the @dev mutex lock.
3343 * @dev: PCI device to reset
3345 * Some devices allow an individual function to be reset without affecting
3346 * other functions in the same device. The PCI device must be responsive
3347 * to PCI config space in order to use this function.
3349 * The device function is presumed to be unused and the caller is holding
3350 * the device mutex lock when this function is called.
3351 * Resetting the device will make the contents of PCI configuration space
3352 * random, so any caller of this must be prepared to reinitialise the
3353 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3356 * Returns 0 if the device function was successfully reset or negative if the
3357 * device doesn't support resetting a single function.
3359 int __pci_reset_function_locked(struct pci_dev
*dev
)
3361 return __pci_dev_reset(dev
, 0);
3363 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3366 * pci_probe_reset_function - check whether the device can be safely reset
3367 * @dev: PCI device to reset
3369 * Some devices allow an individual function to be reset without affecting
3370 * other functions in the same device. The PCI device must be responsive
3371 * to PCI config space in order to use this function.
3373 * Returns 0 if the device function can be reset or negative if the
3374 * device doesn't support resetting a single function.
3376 int pci_probe_reset_function(struct pci_dev
*dev
)
3378 return pci_dev_reset(dev
, 1);
3382 * pci_reset_function - quiesce and reset a PCI device function
3383 * @dev: PCI device to reset
3385 * Some devices allow an individual function to be reset without affecting
3386 * other functions in the same device. The PCI device must be responsive
3387 * to PCI config space in order to use this function.
3389 * This function does not just reset the PCI portion of a device, but
3390 * clears all the state associated with the device. This function differs
3391 * from __pci_reset_function in that it saves and restores device state
3394 * Returns 0 if the device function was successfully reset or negative if the
3395 * device doesn't support resetting a single function.
3397 int pci_reset_function(struct pci_dev
*dev
)
3401 rc
= pci_dev_reset(dev
, 1);
3405 pci_dev_save_and_disable(dev
);
3407 rc
= pci_dev_reset(dev
, 0);
3409 pci_dev_restore(dev
);
3413 EXPORT_SYMBOL_GPL(pci_reset_function
);
3416 * pci_try_reset_function - quiesce and reset a PCI device function
3417 * @dev: PCI device to reset
3419 * Same as above, except return -EAGAIN if unable to lock device.
3421 int pci_try_reset_function(struct pci_dev
*dev
)
3425 rc
= pci_dev_reset(dev
, 1);
3429 pci_dev_save_and_disable(dev
);
3431 if (pci_dev_trylock(dev
)) {
3432 rc
= __pci_dev_reset(dev
, 0);
3433 pci_dev_unlock(dev
);
3437 pci_dev_restore(dev
);
3441 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
3443 /* Lock devices from the top of the tree down */
3444 static void pci_bus_lock(struct pci_bus
*bus
)
3446 struct pci_dev
*dev
;
3448 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3450 if (dev
->subordinate
)
3451 pci_bus_lock(dev
->subordinate
);
3455 /* Unlock devices from the bottom of the tree up */
3456 static void pci_bus_unlock(struct pci_bus
*bus
)
3458 struct pci_dev
*dev
;
3460 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3461 if (dev
->subordinate
)
3462 pci_bus_unlock(dev
->subordinate
);
3463 pci_dev_unlock(dev
);
3467 /* Return 1 on successful lock, 0 on contention */
3468 static int pci_bus_trylock(struct pci_bus
*bus
)
3470 struct pci_dev
*dev
;
3472 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3473 if (!pci_dev_trylock(dev
))
3475 if (dev
->subordinate
) {
3476 if (!pci_bus_trylock(dev
->subordinate
)) {
3477 pci_dev_unlock(dev
);
3485 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
3486 if (dev
->subordinate
)
3487 pci_bus_unlock(dev
->subordinate
);
3488 pci_dev_unlock(dev
);
3493 /* Lock devices from the top of the tree down */
3494 static void pci_slot_lock(struct pci_slot
*slot
)
3496 struct pci_dev
*dev
;
3498 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3499 if (!dev
->slot
|| dev
->slot
!= slot
)
3502 if (dev
->subordinate
)
3503 pci_bus_lock(dev
->subordinate
);
3507 /* Unlock devices from the bottom of the tree up */
3508 static void pci_slot_unlock(struct pci_slot
*slot
)
3510 struct pci_dev
*dev
;
3512 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3513 if (!dev
->slot
|| dev
->slot
!= slot
)
3515 if (dev
->subordinate
)
3516 pci_bus_unlock(dev
->subordinate
);
3517 pci_dev_unlock(dev
);
3521 /* Return 1 on successful lock, 0 on contention */
3522 static int pci_slot_trylock(struct pci_slot
*slot
)
3524 struct pci_dev
*dev
;
3526 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3527 if (!dev
->slot
|| dev
->slot
!= slot
)
3529 if (!pci_dev_trylock(dev
))
3531 if (dev
->subordinate
) {
3532 if (!pci_bus_trylock(dev
->subordinate
)) {
3533 pci_dev_unlock(dev
);
3541 list_for_each_entry_continue_reverse(dev
,
3542 &slot
->bus
->devices
, bus_list
) {
3543 if (!dev
->slot
|| dev
->slot
!= slot
)
3545 if (dev
->subordinate
)
3546 pci_bus_unlock(dev
->subordinate
);
3547 pci_dev_unlock(dev
);
3552 /* Save and disable devices from the top of the tree down */
3553 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
3555 struct pci_dev
*dev
;
3557 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3558 pci_dev_save_and_disable(dev
);
3559 if (dev
->subordinate
)
3560 pci_bus_save_and_disable(dev
->subordinate
);
3565 * Restore devices from top of the tree down - parent bridges need to be
3566 * restored before we can get to subordinate devices.
3568 static void pci_bus_restore(struct pci_bus
*bus
)
3570 struct pci_dev
*dev
;
3572 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3573 pci_dev_restore(dev
);
3574 if (dev
->subordinate
)
3575 pci_bus_restore(dev
->subordinate
);
3579 /* Save and disable devices from the top of the tree down */
3580 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
3582 struct pci_dev
*dev
;
3584 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3585 if (!dev
->slot
|| dev
->slot
!= slot
)
3587 pci_dev_save_and_disable(dev
);
3588 if (dev
->subordinate
)
3589 pci_bus_save_and_disable(dev
->subordinate
);
3594 * Restore devices from top of the tree down - parent bridges need to be
3595 * restored before we can get to subordinate devices.
3597 static void pci_slot_restore(struct pci_slot
*slot
)
3599 struct pci_dev
*dev
;
3601 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3602 if (!dev
->slot
|| dev
->slot
!= slot
)
3604 pci_dev_restore(dev
);
3605 if (dev
->subordinate
)
3606 pci_bus_restore(dev
->subordinate
);
3610 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
3618 pci_slot_lock(slot
);
3622 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
3625 pci_slot_unlock(slot
);
3631 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3632 * @slot: PCI slot to probe
3634 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3636 int pci_probe_reset_slot(struct pci_slot
*slot
)
3638 return pci_slot_reset(slot
, 1);
3640 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
3643 * pci_reset_slot - reset a PCI slot
3644 * @slot: PCI slot to reset
3646 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3647 * independent of other slots. For instance, some slots may support slot power
3648 * control. In the case of a 1:1 bus to slot architecture, this function may
3649 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3650 * Generally a slot reset should be attempted before a bus reset. All of the
3651 * function of the slot and any subordinate buses behind the slot are reset
3652 * through this function. PCI config space of all devices in the slot and
3653 * behind the slot is saved before and restored after reset.
3655 * Return 0 on success, non-zero on error.
3657 int pci_reset_slot(struct pci_slot
*slot
)
3661 rc
= pci_slot_reset(slot
, 1);
3665 pci_slot_save_and_disable(slot
);
3667 rc
= pci_slot_reset(slot
, 0);
3669 pci_slot_restore(slot
);
3673 EXPORT_SYMBOL_GPL(pci_reset_slot
);
3676 * pci_try_reset_slot - Try to reset a PCI slot
3677 * @slot: PCI slot to reset
3679 * Same as above except return -EAGAIN if the slot cannot be locked
3681 int pci_try_reset_slot(struct pci_slot
*slot
)
3685 rc
= pci_slot_reset(slot
, 1);
3689 pci_slot_save_and_disable(slot
);
3691 if (pci_slot_trylock(slot
)) {
3693 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
3694 pci_slot_unlock(slot
);
3698 pci_slot_restore(slot
);
3702 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
3704 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
3716 pci_reset_bridge_secondary_bus(bus
->self
);
3718 pci_bus_unlock(bus
);
3724 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3725 * @bus: PCI bus to probe
3727 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3729 int pci_probe_reset_bus(struct pci_bus
*bus
)
3731 return pci_bus_reset(bus
, 1);
3733 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
3736 * pci_reset_bus - reset a PCI bus
3737 * @bus: top level PCI bus to reset
3739 * Do a bus reset on the given bus and any subordinate buses, saving
3740 * and restoring state of all devices.
3742 * Return 0 on success, non-zero on error.
3744 int pci_reset_bus(struct pci_bus
*bus
)
3748 rc
= pci_bus_reset(bus
, 1);
3752 pci_bus_save_and_disable(bus
);
3754 rc
= pci_bus_reset(bus
, 0);
3756 pci_bus_restore(bus
);
3760 EXPORT_SYMBOL_GPL(pci_reset_bus
);
3763 * pci_try_reset_bus - Try to reset a PCI bus
3764 * @bus: top level PCI bus to reset
3766 * Same as above except return -EAGAIN if the bus cannot be locked
3768 int pci_try_reset_bus(struct pci_bus
*bus
)
3772 rc
= pci_bus_reset(bus
, 1);
3776 pci_bus_save_and_disable(bus
);
3778 if (pci_bus_trylock(bus
)) {
3780 pci_reset_bridge_secondary_bus(bus
->self
);
3781 pci_bus_unlock(bus
);
3785 pci_bus_restore(bus
);
3789 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
3792 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3793 * @dev: PCI device to query
3795 * Returns mmrbc: maximum designed memory read count in bytes
3796 * or appropriate error value.
3798 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
3803 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3807 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3810 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
3812 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
3815 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3816 * @dev: PCI device to query
3818 * Returns mmrbc: maximum memory read count in bytes
3819 * or appropriate error value.
3821 int pcix_get_mmrbc(struct pci_dev
*dev
)
3826 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3830 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3833 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
3835 EXPORT_SYMBOL(pcix_get_mmrbc
);
3838 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3839 * @dev: PCI device to query
3840 * @mmrbc: maximum memory read count in bytes
3841 * valid values are 512, 1024, 2048, 4096
3843 * If possible sets maximum memory read byte count, some bridges have erratas
3844 * that prevent this.
3846 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
3852 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
3855 v
= ffs(mmrbc
) - 10;
3857 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3861 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3864 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
3867 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3870 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
3872 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
3875 cmd
&= ~PCI_X_CMD_MAX_READ
;
3877 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
3882 EXPORT_SYMBOL(pcix_set_mmrbc
);
3885 * pcie_get_readrq - get PCI Express read request size
3886 * @dev: PCI device to query
3888 * Returns maximum memory read request in bytes
3889 * or appropriate error value.
3891 int pcie_get_readrq(struct pci_dev
*dev
)
3895 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
3897 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
3899 EXPORT_SYMBOL(pcie_get_readrq
);
3902 * pcie_set_readrq - set PCI Express maximum memory read request
3903 * @dev: PCI device to query
3904 * @rq: maximum memory read count in bytes
3905 * valid values are 128, 256, 512, 1024, 2048, 4096
3907 * If possible sets maximum memory read request in bytes
3909 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
3913 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
3917 * If using the "performance" PCIe config, we clamp the
3918 * read rq size to the max packet size to prevent the
3919 * host bridge generating requests larger than we can
3922 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
3923 int mps
= pcie_get_mps(dev
);
3929 v
= (ffs(rq
) - 8) << 12;
3931 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
3932 PCI_EXP_DEVCTL_READRQ
, v
);
3934 EXPORT_SYMBOL(pcie_set_readrq
);
3937 * pcie_get_mps - get PCI Express maximum payload size
3938 * @dev: PCI device to query
3940 * Returns maximum payload size in bytes
3942 int pcie_get_mps(struct pci_dev
*dev
)
3946 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
3948 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
3950 EXPORT_SYMBOL(pcie_get_mps
);
3953 * pcie_set_mps - set PCI Express maximum payload size
3954 * @dev: PCI device to query
3955 * @mps: maximum payload size in bytes
3956 * valid values are 128, 256, 512, 1024, 2048, 4096
3958 * If possible sets maximum payload size
3960 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
3964 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
3968 if (v
> dev
->pcie_mpss
)
3972 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
3973 PCI_EXP_DEVCTL_PAYLOAD
, v
);
3975 EXPORT_SYMBOL(pcie_set_mps
);
3978 * pcie_get_minimum_link - determine minimum link settings of a PCI device
3979 * @dev: PCI device to query
3980 * @speed: storage for minimum speed
3981 * @width: storage for minimum width
3983 * This function will walk up the PCI device chain and determine the minimum
3984 * link width and speed of the device.
3986 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
3987 enum pcie_link_width
*width
)
3991 *speed
= PCI_SPEED_UNKNOWN
;
3992 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
3996 enum pci_bus_speed next_speed
;
3997 enum pcie_link_width next_width
;
3999 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
4003 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
4004 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
4005 PCI_EXP_LNKSTA_NLW_SHIFT
;
4007 if (next_speed
< *speed
)
4008 *speed
= next_speed
;
4010 if (next_width
< *width
)
4011 *width
= next_width
;
4013 dev
= dev
->bus
->self
;
4018 EXPORT_SYMBOL(pcie_get_minimum_link
);
4021 * pci_select_bars - Make BAR mask from the type of resource
4022 * @dev: the PCI device for which BAR mask is made
4023 * @flags: resource type mask to be selected
4025 * This helper routine makes bar mask from the type of resource.
4027 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
4030 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
4031 if (pci_resource_flags(dev
, i
) & flags
)
4037 * pci_resource_bar - get position of the BAR associated with a resource
4038 * @dev: the PCI device
4039 * @resno: the resource number
4040 * @type: the BAR type to be filled in
4042 * Returns BAR position in config space, or 0 if the BAR is invalid.
4044 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
4048 if (resno
< PCI_ROM_RESOURCE
) {
4049 *type
= pci_bar_unknown
;
4050 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
4051 } else if (resno
== PCI_ROM_RESOURCE
) {
4052 *type
= pci_bar_mem32
;
4053 return dev
->rom_base_reg
;
4054 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
4055 /* device specific resource */
4056 reg
= pci_iov_resource_bar(dev
, resno
, type
);
4061 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
4065 /* Some architectures require additional programming to enable VGA */
4066 static arch_set_vga_state_t arch_set_vga_state
;
4068 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
4070 arch_set_vga_state
= func
; /* NULL disables */
4073 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
4074 unsigned int command_bits
, u32 flags
)
4076 if (arch_set_vga_state
)
4077 return arch_set_vga_state(dev
, decode
, command_bits
,
4083 * pci_set_vga_state - set VGA decode state on device and parents if requested
4084 * @dev: the PCI device
4085 * @decode: true = enable decoding, false = disable decoding
4086 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4087 * @flags: traverse ancestors and change bridges
4088 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4090 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
4091 unsigned int command_bits
, u32 flags
)
4093 struct pci_bus
*bus
;
4094 struct pci_dev
*bridge
;
4098 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) & (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
4100 /* ARCH specific VGA enables */
4101 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
4105 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
4106 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4108 cmd
|= command_bits
;
4110 cmd
&= ~command_bits
;
4111 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4114 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
4121 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4124 cmd
|= PCI_BRIDGE_CTL_VGA
;
4126 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
4127 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4135 bool pci_device_is_present(struct pci_dev
*pdev
)
4139 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
4141 EXPORT_SYMBOL_GPL(pci_device_is_present
);
4143 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4144 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
4145 static DEFINE_SPINLOCK(resource_alignment_lock
);
4148 * pci_specified_resource_alignment - get resource alignment specified by user.
4149 * @dev: the PCI device to get
4151 * RETURNS: Resource alignment if it is specified.
4152 * Zero if it is not specified.
4154 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
4156 int seg
, bus
, slot
, func
, align_order
, count
;
4157 resource_size_t align
= 0;
4160 spin_lock(&resource_alignment_lock
);
4161 p
= resource_alignment_param
;
4164 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
4170 if (sscanf(p
, "%x:%x:%x.%x%n",
4171 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
4173 if (sscanf(p
, "%x:%x.%x%n",
4174 &bus
, &slot
, &func
, &count
) != 3) {
4175 /* Invalid format */
4176 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
4182 if (seg
== pci_domain_nr(dev
->bus
) &&
4183 bus
== dev
->bus
->number
&&
4184 slot
== PCI_SLOT(dev
->devfn
) &&
4185 func
== PCI_FUNC(dev
->devfn
)) {
4186 if (align_order
== -1) {
4189 align
= 1 << align_order
;
4194 if (*p
!= ';' && *p
!= ',') {
4195 /* End of param or invalid format */
4200 spin_unlock(&resource_alignment_lock
);
4205 * This function disables memory decoding and releases memory resources
4206 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4207 * It also rounds up size to specified alignment.
4208 * Later on, the kernel will assign page-aligned memory resource back
4211 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
4215 resource_size_t align
, size
;
4218 /* check if specified PCI is target device to reassign */
4219 align
= pci_specified_resource_alignment(dev
);
4223 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
4224 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
4226 "Can't reassign resources to host bridge.\n");
4231 "Disabling memory decoding and releasing memory resources.\n");
4232 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
4233 command
&= ~PCI_COMMAND_MEMORY
;
4234 pci_write_config_word(dev
, PCI_COMMAND
, command
);
4236 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
4237 r
= &dev
->resource
[i
];
4238 if (!(r
->flags
& IORESOURCE_MEM
))
4240 size
= resource_size(r
);
4244 "Rounding up size of resource #%d to %#llx.\n",
4245 i
, (unsigned long long)size
);
4247 r
->flags
|= IORESOURCE_UNSET
;
4251 /* Need to disable bridge's resource window,
4252 * to enable the kernel to reassign new resource
4255 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
4256 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
4257 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
4258 r
= &dev
->resource
[i
];
4259 if (!(r
->flags
& IORESOURCE_MEM
))
4261 r
->flags
|= IORESOURCE_UNSET
;
4262 r
->end
= resource_size(r
) - 1;
4265 pci_disable_bridge_window(dev
);
4269 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
4271 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
4272 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
4273 spin_lock(&resource_alignment_lock
);
4274 strncpy(resource_alignment_param
, buf
, count
);
4275 resource_alignment_param
[count
] = '\0';
4276 spin_unlock(&resource_alignment_lock
);
4280 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
4283 spin_lock(&resource_alignment_lock
);
4284 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
4285 spin_unlock(&resource_alignment_lock
);
4289 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
4291 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
4294 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
4295 const char *buf
, size_t count
)
4297 return pci_set_resource_alignment_param(buf
, count
);
4300 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
4301 pci_resource_alignment_store
);
4303 static int __init
pci_resource_alignment_sysfs_init(void)
4305 return bus_create_file(&pci_bus_type
,
4306 &bus_attr_resource_alignment
);
4309 late_initcall(pci_resource_alignment_sysfs_init
);
4311 static void pci_no_domains(void)
4313 #ifdef CONFIG_PCI_DOMAINS
4314 pci_domains_supported
= 0;
4319 * pci_ext_cfg_avail - can we access extended PCI config space?
4321 * Returns 1 if we can access PCI extended config space (offsets
4322 * greater than 0xff). This is the default implementation. Architecture
4323 * implementations can override this.
4325 int __weak
pci_ext_cfg_avail(void)
4330 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
4333 EXPORT_SYMBOL(pci_fixup_cardbus
);
4335 static int __init
pci_setup(char *str
)
4338 char *k
= strchr(str
, ',');
4341 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
4342 if (!strcmp(str
, "nomsi")) {
4344 } else if (!strcmp(str
, "noaer")) {
4346 } else if (!strncmp(str
, "realloc=", 8)) {
4347 pci_realloc_get_opt(str
+ 8);
4348 } else if (!strncmp(str
, "realloc", 7)) {
4349 pci_realloc_get_opt("on");
4350 } else if (!strcmp(str
, "nodomains")) {
4352 } else if (!strncmp(str
, "noari", 5)) {
4353 pcie_ari_disabled
= true;
4354 } else if (!strncmp(str
, "cbiosize=", 9)) {
4355 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
4356 } else if (!strncmp(str
, "cbmemsize=", 10)) {
4357 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
4358 } else if (!strncmp(str
, "resource_alignment=", 19)) {
4359 pci_set_resource_alignment_param(str
+ 19,
4361 } else if (!strncmp(str
, "ecrc=", 5)) {
4362 pcie_ecrc_get_policy(str
+ 5);
4363 } else if (!strncmp(str
, "hpiosize=", 9)) {
4364 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
4365 } else if (!strncmp(str
, "hpmemsize=", 10)) {
4366 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
4367 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
4368 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
4369 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
4370 pcie_bus_config
= PCIE_BUS_SAFE
;
4371 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
4372 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
4373 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
4374 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
4375 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
4376 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
4378 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
4386 early_param("pci", pci_setup
);
4388 EXPORT_SYMBOL(pci_reenable_device
);
4389 EXPORT_SYMBOL(pci_enable_device_io
);
4390 EXPORT_SYMBOL(pci_enable_device_mem
);
4391 EXPORT_SYMBOL(pci_enable_device
);
4392 EXPORT_SYMBOL(pcim_enable_device
);
4393 EXPORT_SYMBOL(pcim_pin_device
);
4394 EXPORT_SYMBOL(pci_disable_device
);
4395 EXPORT_SYMBOL(pci_find_capability
);
4396 EXPORT_SYMBOL(pci_bus_find_capability
);
4397 EXPORT_SYMBOL(pci_release_regions
);
4398 EXPORT_SYMBOL(pci_request_regions
);
4399 EXPORT_SYMBOL(pci_request_regions_exclusive
);
4400 EXPORT_SYMBOL(pci_release_region
);
4401 EXPORT_SYMBOL(pci_request_region
);
4402 EXPORT_SYMBOL(pci_request_region_exclusive
);
4403 EXPORT_SYMBOL(pci_release_selected_regions
);
4404 EXPORT_SYMBOL(pci_request_selected_regions
);
4405 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
4406 EXPORT_SYMBOL(pci_set_master
);
4407 EXPORT_SYMBOL(pci_clear_master
);
4408 EXPORT_SYMBOL(pci_set_mwi
);
4409 EXPORT_SYMBOL(pci_try_set_mwi
);
4410 EXPORT_SYMBOL(pci_clear_mwi
);
4411 EXPORT_SYMBOL_GPL(pci_intx
);
4412 EXPORT_SYMBOL(pci_assign_resource
);
4413 EXPORT_SYMBOL(pci_find_parent_resource
);
4414 EXPORT_SYMBOL(pci_select_bars
);
4416 EXPORT_SYMBOL(pci_set_power_state
);
4417 EXPORT_SYMBOL(pci_save_state
);
4418 EXPORT_SYMBOL(pci_restore_state
);
4419 EXPORT_SYMBOL(pci_pme_capable
);
4420 EXPORT_SYMBOL(pci_pme_active
);
4421 EXPORT_SYMBOL(pci_wake_from_d3
);
4422 EXPORT_SYMBOL(pci_prepare_to_sleep
);
4423 EXPORT_SYMBOL(pci_back_from_sleep
);
4424 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);