2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names
[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names
);
33 int isa_dma_bridge_buggy
;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
37 EXPORT_SYMBOL(pci_pci_problems
);
39 unsigned int pci_pm_d3_delay
;
41 static void pci_pme_list_scan(struct work_struct
*work
);
43 static LIST_HEAD(pci_pme_list
);
44 static DEFINE_MUTEX(pci_pme_list_mutex
);
45 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
47 struct pci_pme_device
{
48 struct list_head list
;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
56 unsigned int delay
= dev
->d3_delay
;
58 if (delay
< pci_pm_d3_delay
)
59 delay
= pci_pm_d3_delay
;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported
= 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
72 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
78 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
80 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
88 u8 pci_dfl_cache_line_size __devinitdata
= L1_CACHE_BYTES
>> 2;
89 u8 pci_cache_line_size
;
92 * If we set up a device for bus mastering, we need to check the latency
93 * timer as certain BIOSes forget to set it properly.
95 unsigned int pcibios_max_latency
= 255;
98 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
99 * @bus: pointer to PCI bus structure to search
101 * Given a PCI bus, returns the highest PCI bus number present in the set
102 * including the given PCI bus and its list of child PCI buses.
104 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
106 struct list_head
*tmp
;
107 unsigned char max
, n
;
109 max
= bus
->subordinate
;
110 list_for_each(tmp
, &bus
->children
) {
111 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
117 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
119 #ifdef CONFIG_HAS_IOMEM
120 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
123 * Make sure the BAR is actually a memory resource, not an IO resource
125 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
129 return ioremap_nocache(pci_resource_start(pdev
, bar
),
130 pci_resource_len(pdev
, bar
));
132 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
137 * pci_max_busnr - returns maximum PCI bus number
139 * Returns the highest PCI bus number present in the system global list of
142 unsigned char __devinit
145 struct pci_bus
*bus
= NULL
;
146 unsigned char max
, n
;
149 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
150 n
= pci_bus_max_busnr(bus
);
159 #define PCI_FIND_CAP_TTL 48
161 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
162 u8 pos
, int cap
, int *ttl
)
167 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
171 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
177 pos
+= PCI_CAP_LIST_NEXT
;
182 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
185 int ttl
= PCI_FIND_CAP_TTL
;
187 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
190 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
192 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
193 pos
+ PCI_CAP_LIST_NEXT
, cap
);
195 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
197 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
198 unsigned int devfn
, u8 hdr_type
)
202 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
203 if (!(status
& PCI_STATUS_CAP_LIST
))
207 case PCI_HEADER_TYPE_NORMAL
:
208 case PCI_HEADER_TYPE_BRIDGE
:
209 return PCI_CAPABILITY_LIST
;
210 case PCI_HEADER_TYPE_CARDBUS
:
211 return PCI_CB_CAPABILITY_LIST
;
220 * pci_find_capability - query for devices' capabilities
221 * @dev: PCI device to query
222 * @cap: capability code
224 * Tell if a device supports a given PCI capability.
225 * Returns the address of the requested capability structure within the
226 * device's PCI configuration space or 0 in case the device does not
227 * support it. Possible values for @cap:
229 * %PCI_CAP_ID_PM Power Management
230 * %PCI_CAP_ID_AGP Accelerated Graphics Port
231 * %PCI_CAP_ID_VPD Vital Product Data
232 * %PCI_CAP_ID_SLOTID Slot Identification
233 * %PCI_CAP_ID_MSI Message Signalled Interrupts
234 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
235 * %PCI_CAP_ID_PCIX PCI-X
236 * %PCI_CAP_ID_EXP PCI Express
238 int pci_find_capability(struct pci_dev
*dev
, int cap
)
242 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
244 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
250 * pci_bus_find_capability - query for devices' capabilities
251 * @bus: the PCI bus to query
252 * @devfn: PCI device to query
253 * @cap: capability code
255 * Like pci_find_capability() but works for pci devices that do not have a
256 * pci_dev structure set up yet.
258 * Returns the address of the requested capability structure within the
259 * device's PCI configuration space or 0 in case the device does not
262 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
267 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
269 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
271 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
277 * pci_find_ext_capability - Find an extended capability
278 * @dev: PCI device to query
279 * @cap: capability code
281 * Returns the address of the requested extended capability structure
282 * within the device's PCI configuration space or 0 if the device does
283 * not support it. Possible values for @cap:
285 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
286 * %PCI_EXT_CAP_ID_VC Virtual Channel
287 * %PCI_EXT_CAP_ID_DSN Device Serial Number
288 * %PCI_EXT_CAP_ID_PWR Power Budgeting
290 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
294 int pos
= PCI_CFG_SPACE_SIZE
;
296 /* minimum 8 bytes per capability */
297 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
299 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
302 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
306 * If we have no capabilities, this is indicated by cap ID,
307 * cap version and next pointer all being 0.
313 if (PCI_EXT_CAP_ID(header
) == cap
)
316 pos
= PCI_EXT_CAP_NEXT(header
);
317 if (pos
< PCI_CFG_SPACE_SIZE
)
320 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
326 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
329 * pci_bus_find_ext_capability - find an extended capability
330 * @bus: the PCI bus to query
331 * @devfn: PCI device to query
332 * @cap: capability code
334 * Like pci_find_ext_capability() but works for pci devices that do not have a
335 * pci_dev structure set up yet.
337 * Returns the address of the requested capability structure within the
338 * device's PCI configuration space or 0 in case the device does not
341 int pci_bus_find_ext_capability(struct pci_bus
*bus
, unsigned int devfn
,
346 int pos
= PCI_CFG_SPACE_SIZE
;
348 /* minimum 8 bytes per capability */
349 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
351 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
353 if (header
== 0xffffffff || header
== 0)
357 if (PCI_EXT_CAP_ID(header
) == cap
)
360 pos
= PCI_EXT_CAP_NEXT(header
);
361 if (pos
< PCI_CFG_SPACE_SIZE
)
364 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
371 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
373 int rc
, ttl
= PCI_FIND_CAP_TTL
;
376 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
377 mask
= HT_3BIT_CAP_MASK
;
379 mask
= HT_5BIT_CAP_MASK
;
381 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
382 PCI_CAP_ID_HT
, &ttl
);
384 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
385 if (rc
!= PCIBIOS_SUCCESSFUL
)
388 if ((cap
& mask
) == ht_cap
)
391 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
392 pos
+ PCI_CAP_LIST_NEXT
,
393 PCI_CAP_ID_HT
, &ttl
);
399 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
400 * @dev: PCI device to query
401 * @pos: Position from which to continue searching
402 * @ht_cap: Hypertransport capability code
404 * To be used in conjunction with pci_find_ht_capability() to search for
405 * all capabilities matching @ht_cap. @pos should always be a value returned
406 * from pci_find_ht_capability().
408 * NB. To be 100% safe against broken PCI devices, the caller should take
409 * steps to avoid an infinite loop.
411 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
413 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
415 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
418 * pci_find_ht_capability - query a device's Hypertransport capabilities
419 * @dev: PCI device to query
420 * @ht_cap: Hypertransport capability code
422 * Tell if a device supports a given Hypertransport capability.
423 * Returns an address within the device's PCI configuration space
424 * or 0 in case the device does not support the request capability.
425 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
426 * which has a Hypertransport capability matching @ht_cap.
428 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
432 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
434 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
438 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
441 * pci_find_parent_resource - return resource region of parent bus of given region
442 * @dev: PCI device structure contains resources to be searched
443 * @res: child resource record for which parent is sought
445 * For given resource region of given device, return the resource
446 * region of parent bus the given region is contained in or where
447 * it should be allocated from.
450 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
452 const struct pci_bus
*bus
= dev
->bus
;
454 struct resource
*best
= NULL
, *r
;
456 pci_bus_for_each_resource(bus
, r
, i
) {
459 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
460 continue; /* Not contained */
461 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
462 continue; /* Wrong type */
463 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
464 return r
; /* Exact match */
465 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
466 if (r
->flags
& IORESOURCE_PREFETCH
)
468 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
476 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
477 * @dev: PCI device to have its BARs restored
479 * Restore the BAR values for a given device, so as to make it
480 * accessible by its driver.
483 pci_restore_bars(struct pci_dev
*dev
)
487 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
488 pci_update_resource(dev
, i
);
491 static struct pci_platform_pm_ops
*pci_platform_pm
;
493 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
495 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
496 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
498 pci_platform_pm
= ops
;
502 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
504 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
507 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
510 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
513 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
515 return pci_platform_pm
?
516 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
519 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
521 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
524 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
526 return pci_platform_pm
?
527 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
530 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
532 return pci_platform_pm
?
533 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
537 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
539 * @dev: PCI device to handle.
540 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
543 * -EINVAL if the requested state is invalid.
544 * -EIO if device does not support PCI PM or its PM capabilities register has a
545 * wrong version, or device doesn't support the requested state.
546 * 0 if device already is in the requested state.
547 * 0 if device's power state has been successfully changed.
549 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
552 bool need_restore
= false;
554 /* Check if we're already there */
555 if (dev
->current_state
== state
)
561 if (state
< PCI_D0
|| state
> PCI_D3hot
)
564 /* Validate current state:
565 * Can enter D0 from any state, but if we can only go deeper
566 * to sleep if we're already in a low power state
568 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
569 && dev
->current_state
> state
) {
570 dev_err(&dev
->dev
, "invalid power transition "
571 "(from state %d to %d)\n", dev
->current_state
, state
);
575 /* check if this device supports the desired state */
576 if ((state
== PCI_D1
&& !dev
->d1_support
)
577 || (state
== PCI_D2
&& !dev
->d2_support
))
580 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
582 /* If we're (effectively) in D3, force entire word to 0.
583 * This doesn't affect PME_Status, disables PME_En, and
584 * sets PowerState to 0.
586 switch (dev
->current_state
) {
590 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
595 case PCI_UNKNOWN
: /* Boot-up */
596 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
597 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
599 /* Fall-through: force to D0 */
605 /* enter specified state */
606 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
608 /* Mandatory power management transition delays */
609 /* see PCI PM 1.1 5.6.1 table 18 */
610 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
611 pci_dev_d3_sleep(dev
);
612 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
613 udelay(PCI_PM_D2_DELAY
);
615 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
616 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
617 if (dev
->current_state
!= state
&& printk_ratelimit())
618 dev_info(&dev
->dev
, "Refused to change power state, "
619 "currently in D%d\n", dev
->current_state
);
621 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
622 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
623 * from D3hot to D0 _may_ perform an internal reset, thereby
624 * going to "D0 Uninitialized" rather than "D0 Initialized".
625 * For example, at least some versions of the 3c905B and the
626 * 3c556B exhibit this behaviour.
628 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
629 * devices in a D3hot state at boot. Consequently, we need to
630 * restore at least the BARs so that the device will be
631 * accessible to its driver.
634 pci_restore_bars(dev
);
637 pcie_aspm_pm_state_change(dev
->bus
->self
);
643 * pci_update_current_state - Read PCI power state of given device from its
644 * PCI PM registers and cache it
645 * @dev: PCI device to handle.
646 * @state: State to cache in case the device doesn't have the PM capability
648 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
653 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
654 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
656 dev
->current_state
= state
;
661 * pci_platform_power_transition - Use platform to change device power state
662 * @dev: PCI device to handle.
663 * @state: State to put the device into.
665 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
669 if (platform_pci_power_manageable(dev
)) {
670 error
= platform_pci_set_power_state(dev
, state
);
672 pci_update_current_state(dev
, state
);
673 /* Fall back to PCI_D0 if native PM is not supported */
675 dev
->current_state
= PCI_D0
;
678 /* Fall back to PCI_D0 if native PM is not supported */
680 dev
->current_state
= PCI_D0
;
687 * __pci_start_power_transition - Start power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
691 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
694 pci_platform_power_transition(dev
, PCI_D0
);
698 * __pci_complete_power_transition - Complete power transition of a PCI device
699 * @dev: PCI device to handle.
700 * @state: State to put the device into.
702 * This function should not be called directly by device drivers.
704 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
706 return state
>= PCI_D0
?
707 pci_platform_power_transition(dev
, state
) : -EINVAL
;
709 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
712 * pci_set_power_state - Set the power state of a PCI device
713 * @dev: PCI device to handle.
714 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
716 * Transition a device to a new power state, using the platform firmware and/or
717 * the device's PCI PM registers.
720 * -EINVAL if the requested state is invalid.
721 * -EIO if device does not support PCI PM or its PM capabilities register has a
722 * wrong version, or device doesn't support the requested state.
723 * 0 if device already is in the requested state.
724 * 0 if device's power state has been successfully changed.
726 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
730 /* bound the state we're entering */
731 if (state
> PCI_D3hot
)
733 else if (state
< PCI_D0
)
735 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
737 * If the device or the parent bridge do not support PCI PM,
738 * ignore the request if we're doing anything other than putting
739 * it into D0 (which would only happen on boot).
743 __pci_start_power_transition(dev
, state
);
745 /* This device is quirked not to be put into D3, so
746 don't put it in D3 */
747 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
750 error
= pci_raw_set_power_state(dev
, state
);
752 if (!__pci_complete_power_transition(dev
, state
))
755 * When aspm_policy is "powersave" this call ensures
756 * that ASPM is configured.
758 if (!error
&& dev
->bus
->self
)
759 pcie_aspm_powersave_config_link(dev
->bus
->self
);
765 * pci_choose_state - Choose the power state of a PCI device
766 * @dev: PCI device to be suspended
767 * @state: target sleep state for the whole system. This is the value
768 * that is passed to suspend() function.
770 * Returns PCI power state suitable for given device and given system
774 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
778 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
781 ret
= platform_pci_choose_state(dev
);
782 if (ret
!= PCI_POWER_ERROR
)
785 switch (state
.event
) {
788 case PM_EVENT_FREEZE
:
789 case PM_EVENT_PRETHAW
:
790 /* REVISIT both freeze and pre-thaw "should" use D0 */
791 case PM_EVENT_SUSPEND
:
792 case PM_EVENT_HIBERNATE
:
795 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
802 EXPORT_SYMBOL(pci_choose_state
);
804 #define PCI_EXP_SAVE_REGS 7
806 #define pcie_cap_has_devctl(type, flags) 1
807 #define pcie_cap_has_lnkctl(type, flags) \
808 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
809 (type == PCI_EXP_TYPE_ROOT_PORT || \
810 type == PCI_EXP_TYPE_ENDPOINT || \
811 type == PCI_EXP_TYPE_LEG_END))
812 #define pcie_cap_has_sltctl(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
814 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
815 (type == PCI_EXP_TYPE_DOWNSTREAM && \
816 (flags & PCI_EXP_FLAGS_SLOT))))
817 #define pcie_cap_has_rtctl(type, flags) \
818 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
819 (type == PCI_EXP_TYPE_ROOT_PORT || \
820 type == PCI_EXP_TYPE_RC_EC))
821 #define pcie_cap_has_devctl2(type, flags) \
822 ((flags & PCI_EXP_FLAGS_VERS) > 1)
823 #define pcie_cap_has_lnkctl2(type, flags) \
824 ((flags & PCI_EXP_FLAGS_VERS) > 1)
825 #define pcie_cap_has_sltctl2(type, flags) \
826 ((flags & PCI_EXP_FLAGS_VERS) > 1)
828 static struct pci_cap_saved_state
*pci_find_saved_cap(
829 struct pci_dev
*pci_dev
, char cap
)
831 struct pci_cap_saved_state
*tmp
;
832 struct hlist_node
*pos
;
834 hlist_for_each_entry(tmp
, pos
, &pci_dev
->saved_cap_space
, next
) {
835 if (tmp
->cap
.cap_nr
== cap
)
841 static int pci_save_pcie_state(struct pci_dev
*dev
)
844 struct pci_cap_saved_state
*save_state
;
848 pos
= pci_pcie_cap(dev
);
852 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
854 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
857 cap
= (u16
*)&save_state
->cap
.data
[0];
859 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
861 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
862 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
863 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
864 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
865 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
866 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
867 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
868 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
869 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
870 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
871 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
872 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
873 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
874 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
879 static void pci_restore_pcie_state(struct pci_dev
*dev
)
882 struct pci_cap_saved_state
*save_state
;
886 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
887 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
888 if (!save_state
|| pos
<= 0)
890 cap
= (u16
*)&save_state
->cap
.data
[0];
892 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
894 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
895 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
896 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
897 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
898 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
899 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
900 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
901 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
902 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
903 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
904 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
905 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
906 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
907 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
911 static int pci_save_pcix_state(struct pci_dev
*dev
)
914 struct pci_cap_saved_state
*save_state
;
916 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
920 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
922 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
926 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
927 (u16
*)save_state
->cap
.data
);
932 static void pci_restore_pcix_state(struct pci_dev
*dev
)
935 struct pci_cap_saved_state
*save_state
;
938 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
939 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
940 if (!save_state
|| pos
<= 0)
942 cap
= (u16
*)&save_state
->cap
.data
[0];
944 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
949 * pci_save_state - save the PCI configuration space of a device before suspending
950 * @dev: - PCI device that we're dealing with
953 pci_save_state(struct pci_dev
*dev
)
956 /* XXX: 100% dword access ok here? */
957 for (i
= 0; i
< 16; i
++)
958 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
959 dev
->state_saved
= true;
960 if ((i
= pci_save_pcie_state(dev
)) != 0)
962 if ((i
= pci_save_pcix_state(dev
)) != 0)
968 * pci_restore_state - Restore the saved state of a PCI device
969 * @dev: - PCI device that we're dealing with
971 void pci_restore_state(struct pci_dev
*dev
)
977 if (!dev
->state_saved
)
980 /* PCI Express register must be restored first */
981 pci_restore_pcie_state(dev
);
982 pci_restore_ats_state(dev
);
985 * The Base Address register should be programmed before the command
988 for (i
= 15; i
>= 0; i
--) {
989 pci_read_config_dword(dev
, i
* 4, &val
);
991 while (tries
&& val
!= dev
->saved_config_space
[i
]) {
992 dev_dbg(&dev
->dev
, "restoring config "
993 "space at offset %#x (was %#x, writing %#x)\n",
994 i
, val
, (int)dev
->saved_config_space
[i
]);
995 pci_write_config_dword(dev
,i
* 4,
996 dev
->saved_config_space
[i
]);
997 pci_read_config_dword(dev
, i
* 4, &val
);
1002 pci_restore_pcix_state(dev
);
1003 pci_restore_msi_state(dev
);
1004 pci_restore_iov_state(dev
);
1006 dev
->state_saved
= false;
1009 struct pci_saved_state
{
1010 u32 config_space
[16];
1011 struct pci_cap_saved_data cap
[0];
1015 * pci_store_saved_state - Allocate and return an opaque struct containing
1016 * the device saved state.
1017 * @dev: PCI device that we're dealing with
1019 * Rerturn NULL if no state or error.
1021 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1023 struct pci_saved_state
*state
;
1024 struct pci_cap_saved_state
*tmp
;
1025 struct pci_cap_saved_data
*cap
;
1026 struct hlist_node
*pos
;
1029 if (!dev
->state_saved
)
1032 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1034 hlist_for_each_entry(tmp
, pos
, &dev
->saved_cap_space
, next
)
1035 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1037 state
= kzalloc(size
, GFP_KERNEL
);
1041 memcpy(state
->config_space
, dev
->saved_config_space
,
1042 sizeof(state
->config_space
));
1045 hlist_for_each_entry(tmp
, pos
, &dev
->saved_cap_space
, next
) {
1046 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1047 memcpy(cap
, &tmp
->cap
, len
);
1048 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1050 /* Empty cap_save terminates list */
1054 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1057 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1058 * @dev: PCI device that we're dealing with
1059 * @state: Saved state returned from pci_store_saved_state()
1061 int pci_load_saved_state(struct pci_dev
*dev
, struct pci_saved_state
*state
)
1063 struct pci_cap_saved_data
*cap
;
1065 dev
->state_saved
= false;
1070 memcpy(dev
->saved_config_space
, state
->config_space
,
1071 sizeof(state
->config_space
));
1075 struct pci_cap_saved_state
*tmp
;
1077 tmp
= pci_find_saved_cap(dev
, cap
->cap_nr
);
1078 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1081 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1082 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1083 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1086 dev
->state_saved
= true;
1089 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1092 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1093 * and free the memory allocated for it.
1094 * @dev: PCI device that we're dealing with
1095 * @state: Pointer to saved state returned from pci_store_saved_state()
1097 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1098 struct pci_saved_state
**state
)
1100 int ret
= pci_load_saved_state(dev
, *state
);
1105 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1107 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1111 err
= pci_set_power_state(dev
, PCI_D0
);
1112 if (err
< 0 && err
!= -EIO
)
1114 err
= pcibios_enable_device(dev
, bars
);
1117 pci_fixup_device(pci_fixup_enable
, dev
);
1123 * pci_reenable_device - Resume abandoned device
1124 * @dev: PCI device to be resumed
1126 * Note this function is a backend of pci_default_resume and is not supposed
1127 * to be called by normal code, write proper resume handler and use it instead.
1129 int pci_reenable_device(struct pci_dev
*dev
)
1131 if (pci_is_enabled(dev
))
1132 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1136 static int __pci_enable_device_flags(struct pci_dev
*dev
,
1137 resource_size_t flags
)
1143 * Power state could be unknown at this point, either due to a fresh
1144 * boot or a device removal call. So get the current power state
1145 * so that things like MSI message writing will behave as expected
1146 * (e.g. if the device really is in D0 at enable time).
1150 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1151 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1154 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
1155 return 0; /* already enabled */
1157 /* only skip sriov related */
1158 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1159 if (dev
->resource
[i
].flags
& flags
)
1161 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1162 if (dev
->resource
[i
].flags
& flags
)
1165 err
= do_pci_enable_device(dev
, bars
);
1167 atomic_dec(&dev
->enable_cnt
);
1172 * pci_enable_device_io - Initialize a device for use with IO space
1173 * @dev: PCI device to be initialized
1175 * Initialize device before it's used by a driver. Ask low-level code
1176 * to enable I/O resources. Wake up the device if it was suspended.
1177 * Beware, this function can fail.
1179 int pci_enable_device_io(struct pci_dev
*dev
)
1181 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
1185 * pci_enable_device_mem - Initialize a device for use with Memory space
1186 * @dev: PCI device to be initialized
1188 * Initialize device before it's used by a driver. Ask low-level code
1189 * to enable Memory resources. Wake up the device if it was suspended.
1190 * Beware, this function can fail.
1192 int pci_enable_device_mem(struct pci_dev
*dev
)
1194 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1198 * pci_enable_device - Initialize device before it's used by a driver.
1199 * @dev: PCI device to be initialized
1201 * Initialize device before it's used by a driver. Ask low-level code
1202 * to enable I/O and memory. Wake up the device if it was suspended.
1203 * Beware, this function can fail.
1205 * Note we don't actually enable the device many times if we call
1206 * this function repeatedly (we just increment the count).
1208 int pci_enable_device(struct pci_dev
*dev
)
1210 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1214 * Managed PCI resources. This manages device on/off, intx/msi/msix
1215 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1216 * there's no need to track it separately. pci_devres is initialized
1217 * when a device is enabled using managed PCI device enable interface.
1220 unsigned int enabled
:1;
1221 unsigned int pinned
:1;
1222 unsigned int orig_intx
:1;
1223 unsigned int restore_intx
:1;
1227 static void pcim_release(struct device
*gendev
, void *res
)
1229 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1230 struct pci_devres
*this = res
;
1233 if (dev
->msi_enabled
)
1234 pci_disable_msi(dev
);
1235 if (dev
->msix_enabled
)
1236 pci_disable_msix(dev
);
1238 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1239 if (this->region_mask
& (1 << i
))
1240 pci_release_region(dev
, i
);
1242 if (this->restore_intx
)
1243 pci_intx(dev
, this->orig_intx
);
1245 if (this->enabled
&& !this->pinned
)
1246 pci_disable_device(dev
);
1249 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1251 struct pci_devres
*dr
, *new_dr
;
1253 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1257 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1260 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1263 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1265 if (pci_is_managed(pdev
))
1266 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1271 * pcim_enable_device - Managed pci_enable_device()
1272 * @pdev: PCI device to be initialized
1274 * Managed pci_enable_device().
1276 int pcim_enable_device(struct pci_dev
*pdev
)
1278 struct pci_devres
*dr
;
1281 dr
= get_pci_dr(pdev
);
1287 rc
= pci_enable_device(pdev
);
1289 pdev
->is_managed
= 1;
1296 * pcim_pin_device - Pin managed PCI device
1297 * @pdev: PCI device to pin
1299 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1300 * driver detach. @pdev must have been enabled with
1301 * pcim_enable_device().
1303 void pcim_pin_device(struct pci_dev
*pdev
)
1305 struct pci_devres
*dr
;
1307 dr
= find_pci_dr(pdev
);
1308 WARN_ON(!dr
|| !dr
->enabled
);
1314 * pcibios_disable_device - disable arch specific PCI resources for device dev
1315 * @dev: the PCI device to disable
1317 * Disables architecture specific PCI resources for the device. This
1318 * is the default implementation. Architecture implementations can
1321 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1323 static void do_pci_disable_device(struct pci_dev
*dev
)
1327 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1328 if (pci_command
& PCI_COMMAND_MASTER
) {
1329 pci_command
&= ~PCI_COMMAND_MASTER
;
1330 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1333 pcibios_disable_device(dev
);
1337 * pci_disable_enabled_device - Disable device without updating enable_cnt
1338 * @dev: PCI device to disable
1340 * NOTE: This function is a backend of PCI power management routines and is
1341 * not supposed to be called drivers.
1343 void pci_disable_enabled_device(struct pci_dev
*dev
)
1345 if (pci_is_enabled(dev
))
1346 do_pci_disable_device(dev
);
1350 * pci_disable_device - Disable PCI device after use
1351 * @dev: PCI device to be disabled
1353 * Signal to the system that the PCI device is not in use by the system
1354 * anymore. This only involves disabling PCI bus-mastering, if active.
1356 * Note we don't actually disable the device until all callers of
1357 * pci_enable_device() have called pci_disable_device().
1360 pci_disable_device(struct pci_dev
*dev
)
1362 struct pci_devres
*dr
;
1364 dr
= find_pci_dr(dev
);
1368 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1371 do_pci_disable_device(dev
);
1373 dev
->is_busmaster
= 0;
1377 * pcibios_set_pcie_reset_state - set reset state for device dev
1378 * @dev: the PCIe device reset
1379 * @state: Reset state to enter into
1382 * Sets the PCIe reset state for the device. This is the default
1383 * implementation. Architecture implementations can override this.
1385 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1386 enum pcie_reset_state state
)
1392 * pci_set_pcie_reset_state - set reset state for device dev
1393 * @dev: the PCIe device reset
1394 * @state: Reset state to enter into
1397 * Sets the PCI reset state for the device.
1399 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1401 return pcibios_set_pcie_reset_state(dev
, state
);
1405 * pci_check_pme_status - Check if given device has generated PME.
1406 * @dev: Device to check.
1408 * Check the PME status of the device and if set, clear it and clear PME enable
1409 * (if set). Return 'true' if PME status and PME enable were both set or
1410 * 'false' otherwise.
1412 bool pci_check_pme_status(struct pci_dev
*dev
)
1421 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1422 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1423 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1426 /* Clear PME status. */
1427 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1428 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1429 /* Disable PME to avoid interrupt flood. */
1430 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1434 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1440 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1441 * @dev: Device to handle.
1442 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1444 * Check if @dev has generated PME and queue a resume request for it in that
1447 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1449 if (pme_poll_reset
&& dev
->pme_poll
)
1450 dev
->pme_poll
= false;
1452 if (pci_check_pme_status(dev
)) {
1453 pci_wakeup_event(dev
);
1454 pm_request_resume(&dev
->dev
);
1460 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1461 * @bus: Top bus of the subtree to walk.
1463 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1466 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1470 * pci_pme_capable - check the capability of PCI device to generate PME#
1471 * @dev: PCI device to handle.
1472 * @state: PCI state from which device will issue PME#.
1474 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1479 return !!(dev
->pme_support
& (1 << state
));
1482 static void pci_pme_list_scan(struct work_struct
*work
)
1484 struct pci_pme_device
*pme_dev
, *n
;
1486 mutex_lock(&pci_pme_list_mutex
);
1487 if (!list_empty(&pci_pme_list
)) {
1488 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1489 if (pme_dev
->dev
->pme_poll
) {
1490 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1492 list_del(&pme_dev
->list
);
1496 if (!list_empty(&pci_pme_list
))
1497 schedule_delayed_work(&pci_pme_work
,
1498 msecs_to_jiffies(PME_TIMEOUT
));
1500 mutex_unlock(&pci_pme_list_mutex
);
1504 * pci_pme_active - enable or disable PCI device's PME# function
1505 * @dev: PCI device to handle.
1506 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1508 * The caller must verify that the device is capable of generating PME# before
1509 * calling this function with @enable equal to 'true'.
1511 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1518 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1519 /* Clear PME_Status by writing 1 to it and enable PME# */
1520 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1522 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1524 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1526 /* PCI (as opposed to PCIe) PME requires that the device have
1527 its PME# line hooked up correctly. Not all hardware vendors
1528 do this, so the PME never gets delivered and the device
1529 remains asleep. The easiest way around this is to
1530 periodically walk the list of suspended devices and check
1531 whether any have their PME flag set. The assumption is that
1532 we'll wake up often enough anyway that this won't be a huge
1533 hit, and the power savings from the devices will still be a
1536 if (dev
->pme_poll
) {
1537 struct pci_pme_device
*pme_dev
;
1539 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1544 mutex_lock(&pci_pme_list_mutex
);
1545 list_add(&pme_dev
->list
, &pci_pme_list
);
1546 if (list_is_singular(&pci_pme_list
))
1547 schedule_delayed_work(&pci_pme_work
,
1548 msecs_to_jiffies(PME_TIMEOUT
));
1549 mutex_unlock(&pci_pme_list_mutex
);
1551 mutex_lock(&pci_pme_list_mutex
);
1552 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1553 if (pme_dev
->dev
== dev
) {
1554 list_del(&pme_dev
->list
);
1559 mutex_unlock(&pci_pme_list_mutex
);
1564 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1568 * __pci_enable_wake - enable PCI device as wakeup event source
1569 * @dev: PCI device affected
1570 * @state: PCI state from which device will issue wakeup events
1571 * @runtime: True if the events are to be generated at run time
1572 * @enable: True to enable event generation; false to disable
1574 * This enables the device as a wakeup event source, or disables it.
1575 * When such events involves platform-specific hooks, those hooks are
1576 * called automatically by this routine.
1578 * Devices with legacy power management (no standard PCI PM capabilities)
1579 * always require such platform hooks.
1582 * 0 is returned on success
1583 * -EINVAL is returned if device is not supposed to wake up the system
1584 * Error code depending on the platform is returned if both the platform and
1585 * the native mechanism fail to enable the generation of wake-up events
1587 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1588 bool runtime
, bool enable
)
1592 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1595 /* Don't do the same thing twice in a row for one device. */
1596 if (!!enable
== !!dev
->wakeup_prepared
)
1600 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1601 * Anderson we should be doing PME# wake enable followed by ACPI wake
1602 * enable. To disable wake-up we call the platform first, for symmetry.
1608 if (pci_pme_capable(dev
, state
))
1609 pci_pme_active(dev
, true);
1612 error
= runtime
? platform_pci_run_wake(dev
, true) :
1613 platform_pci_sleep_wake(dev
, true);
1617 dev
->wakeup_prepared
= true;
1620 platform_pci_run_wake(dev
, false);
1622 platform_pci_sleep_wake(dev
, false);
1623 pci_pme_active(dev
, false);
1624 dev
->wakeup_prepared
= false;
1629 EXPORT_SYMBOL(__pci_enable_wake
);
1632 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1633 * @dev: PCI device to prepare
1634 * @enable: True to enable wake-up event generation; false to disable
1636 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1637 * and this function allows them to set that up cleanly - pci_enable_wake()
1638 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1639 * ordering constraints.
1641 * This function only returns error code if the device is not capable of
1642 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1643 * enable wake-up power for it.
1645 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1647 return pci_pme_capable(dev
, PCI_D3cold
) ?
1648 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1649 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1653 * pci_target_state - find an appropriate low power state for a given PCI dev
1656 * Use underlying platform code to find a supported low power state for @dev.
1657 * If the platform can't manage @dev, return the deepest state from which it
1658 * can generate wake events, based on any available PME info.
1660 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1662 pci_power_t target_state
= PCI_D3hot
;
1664 if (platform_pci_power_manageable(dev
)) {
1666 * Call the platform to choose the target state of the device
1667 * and enable wake-up from this state if supported.
1669 pci_power_t state
= platform_pci_choose_state(dev
);
1672 case PCI_POWER_ERROR
:
1677 if (pci_no_d1d2(dev
))
1680 target_state
= state
;
1682 } else if (!dev
->pm_cap
) {
1683 target_state
= PCI_D0
;
1684 } else if (device_may_wakeup(&dev
->dev
)) {
1686 * Find the deepest state from which the device can generate
1687 * wake-up events, make it the target state and enable device
1690 if (dev
->pme_support
) {
1692 && !(dev
->pme_support
& (1 << target_state
)))
1697 return target_state
;
1701 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1702 * @dev: Device to handle.
1704 * Choose the power state appropriate for the device depending on whether
1705 * it can wake up the system and/or is power manageable by the platform
1706 * (PCI_D3hot is the default) and put the device into that state.
1708 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1710 pci_power_t target_state
= pci_target_state(dev
);
1713 if (target_state
== PCI_POWER_ERROR
)
1716 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1718 error
= pci_set_power_state(dev
, target_state
);
1721 pci_enable_wake(dev
, target_state
, false);
1727 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1728 * @dev: Device to handle.
1730 * Disable device's system wake-up capability and put it into D0.
1732 int pci_back_from_sleep(struct pci_dev
*dev
)
1734 pci_enable_wake(dev
, PCI_D0
, false);
1735 return pci_set_power_state(dev
, PCI_D0
);
1739 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1740 * @dev: PCI device being suspended.
1742 * Prepare @dev to generate wake-up events at run time and put it into a low
1745 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1747 pci_power_t target_state
= pci_target_state(dev
);
1750 if (target_state
== PCI_POWER_ERROR
)
1753 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1755 error
= pci_set_power_state(dev
, target_state
);
1758 __pci_enable_wake(dev
, target_state
, true, false);
1764 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1765 * @dev: Device to check.
1767 * Return true if the device itself is cabable of generating wake-up events
1768 * (through the platform or using the native PCIe PME) or if the device supports
1769 * PME and one of its upstream bridges can generate wake-up events.
1771 bool pci_dev_run_wake(struct pci_dev
*dev
)
1773 struct pci_bus
*bus
= dev
->bus
;
1775 if (device_run_wake(&dev
->dev
))
1778 if (!dev
->pme_support
)
1781 while (bus
->parent
) {
1782 struct pci_dev
*bridge
= bus
->self
;
1784 if (device_run_wake(&bridge
->dev
))
1790 /* We have reached the root bus. */
1792 return device_run_wake(bus
->bridge
);
1796 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1799 * pci_pm_init - Initialize PM functions of given PCI device
1800 * @dev: PCI device to handle.
1802 void pci_pm_init(struct pci_dev
*dev
)
1807 pm_runtime_forbid(&dev
->dev
);
1808 device_enable_async_suspend(&dev
->dev
);
1809 dev
->wakeup_prepared
= false;
1813 /* find PCI PM capability in list */
1814 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1817 /* Check device's ability to generate PME# */
1818 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1820 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1821 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1822 pmc
& PCI_PM_CAP_VER_MASK
);
1827 dev
->d3_delay
= PCI_PM_D3_WAIT
;
1829 dev
->d1_support
= false;
1830 dev
->d2_support
= false;
1831 if (!pci_no_d1d2(dev
)) {
1832 if (pmc
& PCI_PM_CAP_D1
)
1833 dev
->d1_support
= true;
1834 if (pmc
& PCI_PM_CAP_D2
)
1835 dev
->d2_support
= true;
1837 if (dev
->d1_support
|| dev
->d2_support
)
1838 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1839 dev
->d1_support
? " D1" : "",
1840 dev
->d2_support
? " D2" : "");
1843 pmc
&= PCI_PM_CAP_PME_MASK
;
1845 dev_printk(KERN_DEBUG
, &dev
->dev
,
1846 "PME# supported from%s%s%s%s%s\n",
1847 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1848 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1849 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1850 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1851 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1852 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1853 dev
->pme_poll
= true;
1855 * Make device's PM flags reflect the wake-up capability, but
1856 * let the user space enable it to wake up the system as needed.
1858 device_set_wakeup_capable(&dev
->dev
, true);
1859 /* Disable the PME# generation functionality */
1860 pci_pme_active(dev
, false);
1862 dev
->pme_support
= 0;
1867 * platform_pci_wakeup_init - init platform wakeup if present
1870 * Some devices don't have PCI PM caps but can still generate wakeup
1871 * events through platform methods (like ACPI events). If @dev supports
1872 * platform wakeup events, set the device flag to indicate as much. This
1873 * may be redundant if the device also supports PCI PM caps, but double
1874 * initialization should be safe in that case.
1876 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1878 if (!platform_pci_can_wakeup(dev
))
1881 device_set_wakeup_capable(&dev
->dev
, true);
1882 platform_pci_sleep_wake(dev
, false);
1885 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
1886 struct pci_cap_saved_state
*new_cap
)
1888 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
1892 * pci_add_save_buffer - allocate buffer for saving given capability registers
1893 * @dev: the PCI device
1894 * @cap: the capability to allocate the buffer for
1895 * @size: requested size of the buffer
1897 static int pci_add_cap_save_buffer(
1898 struct pci_dev
*dev
, char cap
, unsigned int size
)
1901 struct pci_cap_saved_state
*save_state
;
1903 pos
= pci_find_capability(dev
, cap
);
1907 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1911 save_state
->cap
.cap_nr
= cap
;
1912 save_state
->cap
.size
= size
;
1913 pci_add_saved_cap(dev
, save_state
);
1919 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1920 * @dev: the PCI device
1922 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1926 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1927 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1930 "unable to preallocate PCI Express save buffer\n");
1932 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1935 "unable to preallocate PCI-X save buffer\n");
1938 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
1940 struct pci_cap_saved_state
*tmp
;
1941 struct hlist_node
*pos
, *n
;
1943 hlist_for_each_entry_safe(tmp
, pos
, n
, &dev
->saved_cap_space
, next
)
1948 * pci_enable_ari - enable ARI forwarding if hardware support it
1949 * @dev: the PCI device
1951 void pci_enable_ari(struct pci_dev
*dev
)
1956 struct pci_dev
*bridge
;
1958 if (!pci_is_pcie(dev
) || dev
->devfn
)
1961 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1965 bridge
= dev
->bus
->self
;
1966 if (!bridge
|| !pci_is_pcie(bridge
))
1969 pos
= pci_pcie_cap(bridge
);
1973 /* ARI is a PCIe v2 feature */
1974 pci_read_config_word(bridge
, pos
+ PCI_EXP_FLAGS
, &flags
);
1975 if ((flags
& PCI_EXP_FLAGS_VERS
) < 2)
1978 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1979 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1982 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1983 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1984 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1986 bridge
->ari_enabled
= 1;
1990 * pci_enable_ido - enable ID-based ordering on a device
1991 * @dev: the PCI device
1992 * @type: which types of IDO to enable
1994 * Enable ID-based ordering on @dev. @type can contain the bits
1995 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1996 * which types of transactions are allowed to be re-ordered.
1998 void pci_enable_ido(struct pci_dev
*dev
, unsigned long type
)
2003 pos
= pci_pcie_cap(dev
);
2007 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2008 if (type
& PCI_EXP_IDO_REQUEST
)
2009 ctrl
|= PCI_EXP_IDO_REQ_EN
;
2010 if (type
& PCI_EXP_IDO_COMPLETION
)
2011 ctrl
|= PCI_EXP_IDO_CMP_EN
;
2012 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2014 EXPORT_SYMBOL(pci_enable_ido
);
2017 * pci_disable_ido - disable ID-based ordering on a device
2018 * @dev: the PCI device
2019 * @type: which types of IDO to disable
2021 void pci_disable_ido(struct pci_dev
*dev
, unsigned long type
)
2026 if (!pci_is_pcie(dev
))
2029 pos
= pci_pcie_cap(dev
);
2033 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2034 if (type
& PCI_EXP_IDO_REQUEST
)
2035 ctrl
&= ~PCI_EXP_IDO_REQ_EN
;
2036 if (type
& PCI_EXP_IDO_COMPLETION
)
2037 ctrl
&= ~PCI_EXP_IDO_CMP_EN
;
2038 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2040 EXPORT_SYMBOL(pci_disable_ido
);
2043 * pci_enable_obff - enable optimized buffer flush/fill
2045 * @type: type of signaling to use
2047 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2048 * signaling if possible, falling back to message signaling only if
2049 * WAKE# isn't supported. @type should indicate whether the PCIe link
2050 * be brought out of L0s or L1 to send the message. It should be either
2051 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2053 * If your device can benefit from receiving all messages, even at the
2054 * power cost of bringing the link back up from a low power state, use
2055 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2059 * Zero on success, appropriate error number on failure.
2061 int pci_enable_obff(struct pci_dev
*dev
, enum pci_obff_signal_type type
)
2068 if (!pci_is_pcie(dev
))
2071 pos
= pci_pcie_cap(dev
);
2075 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2076 if (!(cap
& PCI_EXP_OBFF_MASK
))
2077 return -ENOTSUPP
; /* no OBFF support at all */
2079 /* Make sure the topology supports OBFF as well */
2081 ret
= pci_enable_obff(dev
->bus
->self
, type
);
2086 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2087 if (cap
& PCI_EXP_OBFF_WAKE
)
2088 ctrl
|= PCI_EXP_OBFF_WAKE_EN
;
2091 case PCI_EXP_OBFF_SIGNAL_L0
:
2092 if (!(ctrl
& PCI_EXP_OBFF_WAKE_EN
))
2093 ctrl
|= PCI_EXP_OBFF_MSGA_EN
;
2095 case PCI_EXP_OBFF_SIGNAL_ALWAYS
:
2096 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
2097 ctrl
|= PCI_EXP_OBFF_MSGB_EN
;
2100 WARN(1, "bad OBFF signal type\n");
2104 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2108 EXPORT_SYMBOL(pci_enable_obff
);
2111 * pci_disable_obff - disable optimized buffer flush/fill
2114 * Disable OBFF on @dev.
2116 void pci_disable_obff(struct pci_dev
*dev
)
2121 if (!pci_is_pcie(dev
))
2124 pos
= pci_pcie_cap(dev
);
2128 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2129 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
2130 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2132 EXPORT_SYMBOL(pci_disable_obff
);
2135 * pci_ltr_supported - check whether a device supports LTR
2139 * True if @dev supports latency tolerance reporting, false otherwise.
2141 bool pci_ltr_supported(struct pci_dev
*dev
)
2146 if (!pci_is_pcie(dev
))
2149 pos
= pci_pcie_cap(dev
);
2153 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2155 return cap
& PCI_EXP_DEVCAP2_LTR
;
2157 EXPORT_SYMBOL(pci_ltr_supported
);
2160 * pci_enable_ltr - enable latency tolerance reporting
2163 * Enable LTR on @dev if possible, which means enabling it first on
2167 * Zero on success, errno on failure.
2169 int pci_enable_ltr(struct pci_dev
*dev
)
2175 if (!pci_ltr_supported(dev
))
2178 pos
= pci_pcie_cap(dev
);
2182 /* Only primary function can enable/disable LTR */
2183 if (PCI_FUNC(dev
->devfn
) != 0)
2186 /* Enable upstream ports first */
2188 ret
= pci_enable_ltr(dev
->bus
->self
);
2193 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2194 ctrl
|= PCI_EXP_LTR_EN
;
2195 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2199 EXPORT_SYMBOL(pci_enable_ltr
);
2202 * pci_disable_ltr - disable latency tolerance reporting
2205 void pci_disable_ltr(struct pci_dev
*dev
)
2210 if (!pci_ltr_supported(dev
))
2213 pos
= pci_pcie_cap(dev
);
2217 /* Only primary function can enable/disable LTR */
2218 if (PCI_FUNC(dev
->devfn
) != 0)
2221 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2222 ctrl
&= ~PCI_EXP_LTR_EN
;
2223 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2225 EXPORT_SYMBOL(pci_disable_ltr
);
2227 static int __pci_ltr_scale(int *val
)
2231 while (*val
> 1023) {
2232 *val
= (*val
+ 31) / 32;
2239 * pci_set_ltr - set LTR latency values
2241 * @snoop_lat_ns: snoop latency in nanoseconds
2242 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2244 * Figure out the scale and set the LTR values accordingly.
2246 int pci_set_ltr(struct pci_dev
*dev
, int snoop_lat_ns
, int nosnoop_lat_ns
)
2248 int pos
, ret
, snoop_scale
, nosnoop_scale
;
2251 if (!pci_ltr_supported(dev
))
2254 snoop_scale
= __pci_ltr_scale(&snoop_lat_ns
);
2255 nosnoop_scale
= __pci_ltr_scale(&nosnoop_lat_ns
);
2257 if (snoop_lat_ns
> PCI_LTR_VALUE_MASK
||
2258 nosnoop_lat_ns
> PCI_LTR_VALUE_MASK
)
2261 if ((snoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)) ||
2262 (nosnoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)))
2265 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
2269 val
= (snoop_scale
<< PCI_LTR_SCALE_SHIFT
) | snoop_lat_ns
;
2270 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_SNOOP_LAT
, val
);
2274 val
= (nosnoop_scale
<< PCI_LTR_SCALE_SHIFT
) | nosnoop_lat_ns
;
2275 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_NOSNOOP_LAT
, val
);
2281 EXPORT_SYMBOL(pci_set_ltr
);
2283 static int pci_acs_enable
;
2286 * pci_request_acs - ask for ACS to be enabled if supported
2288 void pci_request_acs(void)
2294 * pci_enable_acs - enable ACS if hardware support it
2295 * @dev: the PCI device
2297 void pci_enable_acs(struct pci_dev
*dev
)
2303 if (!pci_acs_enable
)
2306 if (!pci_is_pcie(dev
))
2309 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2313 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2314 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2316 /* Source Validation */
2317 ctrl
|= (cap
& PCI_ACS_SV
);
2319 /* P2P Request Redirect */
2320 ctrl
|= (cap
& PCI_ACS_RR
);
2322 /* P2P Completion Redirect */
2323 ctrl
|= (cap
& PCI_ACS_CR
);
2325 /* Upstream Forwarding */
2326 ctrl
|= (cap
& PCI_ACS_UF
);
2328 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2332 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2333 * @dev: the PCI device
2334 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2336 * Perform INTx swizzling for a device behind one level of bridge. This is
2337 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2338 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2339 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2340 * the PCI Express Base Specification, Revision 2.1)
2342 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
2346 if (pci_ari_enabled(dev
->bus
))
2349 slot
= PCI_SLOT(dev
->devfn
);
2351 return (((pin
- 1) + slot
) % 4) + 1;
2355 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2363 while (!pci_is_root_bus(dev
->bus
)) {
2364 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2365 dev
= dev
->bus
->self
;
2372 * pci_common_swizzle - swizzle INTx all the way to root bridge
2373 * @dev: the PCI device
2374 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2376 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2377 * bridges all the way up to a PCI root bus.
2379 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2383 while (!pci_is_root_bus(dev
->bus
)) {
2384 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2385 dev
= dev
->bus
->self
;
2388 return PCI_SLOT(dev
->devfn
);
2392 * pci_release_region - Release a PCI bar
2393 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2394 * @bar: BAR to release
2396 * Releases the PCI I/O and memory resources previously reserved by a
2397 * successful call to pci_request_region. Call this function only
2398 * after all use of the PCI regions has ceased.
2400 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2402 struct pci_devres
*dr
;
2404 if (pci_resource_len(pdev
, bar
) == 0)
2406 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2407 release_region(pci_resource_start(pdev
, bar
),
2408 pci_resource_len(pdev
, bar
));
2409 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2410 release_mem_region(pci_resource_start(pdev
, bar
),
2411 pci_resource_len(pdev
, bar
));
2413 dr
= find_pci_dr(pdev
);
2415 dr
->region_mask
&= ~(1 << bar
);
2419 * __pci_request_region - Reserved PCI I/O and memory resource
2420 * @pdev: PCI device whose resources are to be reserved
2421 * @bar: BAR to be reserved
2422 * @res_name: Name to be associated with resource.
2423 * @exclusive: whether the region access is exclusive or not
2425 * Mark the PCI region associated with PCI device @pdev BR @bar as
2426 * being reserved by owner @res_name. Do not access any
2427 * address inside the PCI regions unless this call returns
2430 * If @exclusive is set, then the region is marked so that userspace
2431 * is explicitly not allowed to map the resource via /dev/mem or
2432 * sysfs MMIO access.
2434 * Returns 0 on success, or %EBUSY on error. A warning
2435 * message is also printed on failure.
2437 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
2440 struct pci_devres
*dr
;
2442 if (pci_resource_len(pdev
, bar
) == 0)
2445 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2446 if (!request_region(pci_resource_start(pdev
, bar
),
2447 pci_resource_len(pdev
, bar
), res_name
))
2450 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2451 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2452 pci_resource_len(pdev
, bar
), res_name
,
2457 dr
= find_pci_dr(pdev
);
2459 dr
->region_mask
|= 1 << bar
;
2464 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2465 &pdev
->resource
[bar
]);
2470 * pci_request_region - Reserve PCI I/O and memory resource
2471 * @pdev: PCI device whose resources are to be reserved
2472 * @bar: BAR to be reserved
2473 * @res_name: Name to be associated with resource
2475 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2476 * being reserved by owner @res_name. Do not access any
2477 * address inside the PCI regions unless this call returns
2480 * Returns 0 on success, or %EBUSY on error. A warning
2481 * message is also printed on failure.
2483 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2485 return __pci_request_region(pdev
, bar
, res_name
, 0);
2489 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2490 * @pdev: PCI device whose resources are to be reserved
2491 * @bar: BAR to be reserved
2492 * @res_name: Name to be associated with resource.
2494 * Mark the PCI region associated with PCI device @pdev BR @bar as
2495 * being reserved by owner @res_name. Do not access any
2496 * address inside the PCI regions unless this call returns
2499 * Returns 0 on success, or %EBUSY on error. A warning
2500 * message is also printed on failure.
2502 * The key difference that _exclusive makes it that userspace is
2503 * explicitly not allowed to map the resource via /dev/mem or
2506 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2508 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2511 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2512 * @pdev: PCI device whose resources were previously reserved
2513 * @bars: Bitmask of BARs to be released
2515 * Release selected PCI I/O and memory resources previously reserved.
2516 * Call this function only after all use of the PCI regions has ceased.
2518 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2522 for (i
= 0; i
< 6; i
++)
2523 if (bars
& (1 << i
))
2524 pci_release_region(pdev
, i
);
2527 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2528 const char *res_name
, int excl
)
2532 for (i
= 0; i
< 6; i
++)
2533 if (bars
& (1 << i
))
2534 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2540 if (bars
& (1 << i
))
2541 pci_release_region(pdev
, i
);
2548 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2549 * @pdev: PCI device whose resources are to be reserved
2550 * @bars: Bitmask of BARs to be requested
2551 * @res_name: Name to be associated with resource
2553 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2554 const char *res_name
)
2556 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2559 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2560 int bars
, const char *res_name
)
2562 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2563 IORESOURCE_EXCLUSIVE
);
2567 * pci_release_regions - Release reserved PCI I/O and memory resources
2568 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2570 * Releases all PCI I/O and memory resources previously reserved by a
2571 * successful call to pci_request_regions. Call this function only
2572 * after all use of the PCI regions has ceased.
2575 void pci_release_regions(struct pci_dev
*pdev
)
2577 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2581 * pci_request_regions - Reserved PCI I/O and memory resources
2582 * @pdev: PCI device whose resources are to be reserved
2583 * @res_name: Name to be associated with resource.
2585 * Mark all PCI regions associated with PCI device @pdev as
2586 * being reserved by owner @res_name. Do not access any
2587 * address inside the PCI regions unless this call returns
2590 * Returns 0 on success, or %EBUSY on error. A warning
2591 * message is also printed on failure.
2593 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2595 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2599 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2600 * @pdev: PCI device whose resources are to be reserved
2601 * @res_name: Name to be associated with resource.
2603 * Mark all PCI regions associated with PCI device @pdev as
2604 * being reserved by owner @res_name. Do not access any
2605 * address inside the PCI regions unless this call returns
2608 * pci_request_regions_exclusive() will mark the region so that
2609 * /dev/mem and the sysfs MMIO access will not be allowed.
2611 * Returns 0 on success, or %EBUSY on error. A warning
2612 * message is also printed on failure.
2614 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2616 return pci_request_selected_regions_exclusive(pdev
,
2617 ((1 << 6) - 1), res_name
);
2620 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2624 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2626 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2628 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2629 if (cmd
!= old_cmd
) {
2630 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2631 enable
? "enabling" : "disabling");
2632 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2634 dev
->is_busmaster
= enable
;
2638 * pcibios_set_master - enable PCI bus-mastering for device dev
2639 * @dev: the PCI device to enable
2641 * Enables PCI bus-mastering for the device. This is the default
2642 * implementation. Architecture specific implementations can override
2643 * this if necessary.
2645 void __weak
pcibios_set_master(struct pci_dev
*dev
)
2649 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2650 if (pci_is_pcie(dev
))
2653 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
2655 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
2656 else if (lat
> pcibios_max_latency
)
2657 lat
= pcibios_max_latency
;
2660 dev_printk(KERN_DEBUG
, &dev
->dev
, "setting latency timer to %d\n", lat
);
2661 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
2665 * pci_set_master - enables bus-mastering for device dev
2666 * @dev: the PCI device to enable
2668 * Enables bus-mastering on the device and calls pcibios_set_master()
2669 * to do the needed arch specific settings.
2671 void pci_set_master(struct pci_dev
*dev
)
2673 __pci_set_master(dev
, true);
2674 pcibios_set_master(dev
);
2678 * pci_clear_master - disables bus-mastering for device dev
2679 * @dev: the PCI device to disable
2681 void pci_clear_master(struct pci_dev
*dev
)
2683 __pci_set_master(dev
, false);
2687 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2688 * @dev: the PCI device for which MWI is to be enabled
2690 * Helper function for pci_set_mwi.
2691 * Originally copied from drivers/net/acenic.c.
2692 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2694 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2696 int pci_set_cacheline_size(struct pci_dev
*dev
)
2700 if (!pci_cache_line_size
)
2703 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2704 equal to or multiple of the right value. */
2705 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2706 if (cacheline_size
>= pci_cache_line_size
&&
2707 (cacheline_size
% pci_cache_line_size
) == 0)
2710 /* Write the correct value. */
2711 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2713 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2714 if (cacheline_size
== pci_cache_line_size
)
2717 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2718 "supported\n", pci_cache_line_size
<< 2);
2722 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2724 #ifdef PCI_DISABLE_MWI
2725 int pci_set_mwi(struct pci_dev
*dev
)
2730 int pci_try_set_mwi(struct pci_dev
*dev
)
2735 void pci_clear_mwi(struct pci_dev
*dev
)
2742 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2743 * @dev: the PCI device for which MWI is enabled
2745 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2747 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2750 pci_set_mwi(struct pci_dev
*dev
)
2755 rc
= pci_set_cacheline_size(dev
);
2759 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2760 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2761 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2762 cmd
|= PCI_COMMAND_INVALIDATE
;
2763 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2770 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2771 * @dev: the PCI device for which MWI is enabled
2773 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2774 * Callers are not required to check the return value.
2776 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2778 int pci_try_set_mwi(struct pci_dev
*dev
)
2780 int rc
= pci_set_mwi(dev
);
2785 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2786 * @dev: the PCI device to disable
2788 * Disables PCI Memory-Write-Invalidate transaction on the device
2791 pci_clear_mwi(struct pci_dev
*dev
)
2795 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2796 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2797 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2798 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2801 #endif /* ! PCI_DISABLE_MWI */
2804 * pci_intx - enables/disables PCI INTx for device dev
2805 * @pdev: the PCI device to operate on
2806 * @enable: boolean: whether to enable or disable PCI INTx
2808 * Enables/disables PCI INTx for device dev
2811 pci_intx(struct pci_dev
*pdev
, int enable
)
2813 u16 pci_command
, new;
2815 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2818 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2820 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2823 if (new != pci_command
) {
2824 struct pci_devres
*dr
;
2826 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2828 dr
= find_pci_dr(pdev
);
2829 if (dr
&& !dr
->restore_intx
) {
2830 dr
->restore_intx
= 1;
2831 dr
->orig_intx
= !enable
;
2837 * pci_intx_mask_supported - probe for INTx masking support
2838 * @dev: the PCI device to operate on
2840 * Check if the device dev support INTx masking via the config space
2843 bool pci_intx_mask_supported(struct pci_dev
*dev
)
2845 bool mask_supported
= false;
2848 pci_cfg_access_lock(dev
);
2850 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
2851 pci_write_config_word(dev
, PCI_COMMAND
,
2852 orig
^ PCI_COMMAND_INTX_DISABLE
);
2853 pci_read_config_word(dev
, PCI_COMMAND
, &new);
2856 * There's no way to protect against hardware bugs or detect them
2857 * reliably, but as long as we know what the value should be, let's
2858 * go ahead and check it.
2860 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
2861 dev_err(&dev
->dev
, "Command register changed from "
2862 "0x%x to 0x%x: driver or hardware bug?\n", orig
, new);
2863 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
2864 mask_supported
= true;
2865 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
2868 pci_cfg_access_unlock(dev
);
2869 return mask_supported
;
2871 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
2873 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
2875 struct pci_bus
*bus
= dev
->bus
;
2876 bool mask_updated
= true;
2877 u32 cmd_status_dword
;
2878 u16 origcmd
, newcmd
;
2879 unsigned long flags
;
2883 * We do a single dword read to retrieve both command and status.
2884 * Document assumptions that make this possible.
2886 BUILD_BUG_ON(PCI_COMMAND
% 4);
2887 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
2889 raw_spin_lock_irqsave(&pci_lock
, flags
);
2891 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
2893 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
2896 * Check interrupt status register to see whether our device
2897 * triggered the interrupt (when masking) or the next IRQ is
2898 * already pending (when unmasking).
2900 if (mask
!= irq_pending
) {
2901 mask_updated
= false;
2905 origcmd
= cmd_status_dword
;
2906 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
2908 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
2909 if (newcmd
!= origcmd
)
2910 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
2913 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
2915 return mask_updated
;
2919 * pci_check_and_mask_intx - mask INTx on pending interrupt
2920 * @dev: the PCI device to operate on
2922 * Check if the device dev has its INTx line asserted, mask it and
2923 * return true in that case. False is returned if not interrupt was
2926 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
2928 return pci_check_and_set_intx_mask(dev
, true);
2930 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
2933 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
2934 * @dev: the PCI device to operate on
2936 * Check if the device dev has its INTx line asserted, unmask it if not
2937 * and return true. False is returned and the mask remains active if
2938 * there was still an interrupt pending.
2940 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
2942 return pci_check_and_set_intx_mask(dev
, false);
2944 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
2947 * pci_msi_off - disables any msi or msix capabilities
2948 * @dev: the PCI device to operate on
2950 * If you want to use msi see pci_enable_msi and friends.
2951 * This is a lower level primitive that allows us to disable
2952 * msi operation at the device level.
2954 void pci_msi_off(struct pci_dev
*dev
)
2959 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2961 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2962 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2963 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2965 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2967 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2968 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2969 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2972 EXPORT_SYMBOL_GPL(pci_msi_off
);
2974 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2976 return dma_set_max_seg_size(&dev
->dev
, size
);
2978 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2980 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2982 return dma_set_seg_boundary(&dev
->dev
, mask
);
2984 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2986 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2991 u16 status
, control
;
2993 pos
= pci_pcie_cap(dev
);
2997 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
2998 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3004 /* Wait for Transaction Pending bit clean */
3005 for (i
= 0; i
< 4; i
++) {
3007 msleep((1 << (i
- 1)) * 100);
3009 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
3010 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
3014 dev_err(&dev
->dev
, "transaction is not cleared; "
3015 "proceeding with reset anyway\n");
3018 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &control
);
3019 control
|= PCI_EXP_DEVCTL_BCR_FLR
;
3020 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, control
);
3027 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3034 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3038 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3039 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3045 /* Wait for Transaction Pending bit clean */
3046 for (i
= 0; i
< 4; i
++) {
3048 msleep((1 << (i
- 1)) * 100);
3050 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
3051 if (!(status
& PCI_AF_STATUS_TP
))
3055 dev_err(&dev
->dev
, "transaction is not cleared; "
3056 "proceeding with reset anyway\n");
3059 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3066 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3067 * @dev: Device to reset.
3068 * @probe: If set, only check if the device can be reset this way.
3070 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3071 * unset, it will be reinitialized internally when going from PCI_D3hot to
3072 * PCI_D0. If that's the case and the device is not in a low-power state
3073 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3075 * NOTE: This causes the caller to sleep for twice the device power transition
3076 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3077 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3078 * Moreover, only devices in D0 can be reset by this function.
3080 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3087 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3088 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3094 if (dev
->current_state
!= PCI_D0
)
3097 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3099 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3100 pci_dev_d3_sleep(dev
);
3102 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3104 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3105 pci_dev_d3_sleep(dev
);
3110 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3113 struct pci_dev
*pdev
;
3115 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
3118 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3125 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
3126 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3127 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
3130 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3131 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
3137 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3144 pci_cfg_access_lock(dev
);
3145 /* block PM suspend, driver probe, etc. */
3146 device_lock(&dev
->dev
);
3149 rc
= pci_dev_specific_reset(dev
, probe
);
3153 rc
= pcie_flr(dev
, probe
);
3157 rc
= pci_af_flr(dev
, probe
);
3161 rc
= pci_pm_reset(dev
, probe
);
3165 rc
= pci_parent_bus_reset(dev
, probe
);
3168 device_unlock(&dev
->dev
);
3169 pci_cfg_access_unlock(dev
);
3176 * __pci_reset_function - reset a PCI device function
3177 * @dev: PCI device to reset
3179 * Some devices allow an individual function to be reset without affecting
3180 * other functions in the same device. The PCI device must be responsive
3181 * to PCI config space in order to use this function.
3183 * The device function is presumed to be unused when this function is called.
3184 * Resetting the device will make the contents of PCI configuration space
3185 * random, so any caller of this must be prepared to reinitialise the
3186 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3189 * Returns 0 if the device function was successfully reset or negative if the
3190 * device doesn't support resetting a single function.
3192 int __pci_reset_function(struct pci_dev
*dev
)
3194 return pci_dev_reset(dev
, 0);
3196 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3199 * __pci_reset_function_locked - reset a PCI device function while holding
3200 * the @dev mutex lock.
3201 * @dev: PCI device to reset
3203 * Some devices allow an individual function to be reset without affecting
3204 * other functions in the same device. The PCI device must be responsive
3205 * to PCI config space in order to use this function.
3207 * The device function is presumed to be unused and the caller is holding
3208 * the device mutex lock when this function is called.
3209 * Resetting the device will make the contents of PCI configuration space
3210 * random, so any caller of this must be prepared to reinitialise the
3211 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3214 * Returns 0 if the device function was successfully reset or negative if the
3215 * device doesn't support resetting a single function.
3217 int __pci_reset_function_locked(struct pci_dev
*dev
)
3219 return pci_dev_reset(dev
, 1);
3221 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3224 * pci_probe_reset_function - check whether the device can be safely reset
3225 * @dev: PCI device to reset
3227 * Some devices allow an individual function to be reset without affecting
3228 * other functions in the same device. The PCI device must be responsive
3229 * to PCI config space in order to use this function.
3231 * Returns 0 if the device function can be reset or negative if the
3232 * device doesn't support resetting a single function.
3234 int pci_probe_reset_function(struct pci_dev
*dev
)
3236 return pci_dev_reset(dev
, 1);
3240 * pci_reset_function - quiesce and reset a PCI device function
3241 * @dev: PCI device to reset
3243 * Some devices allow an individual function to be reset without affecting
3244 * other functions in the same device. The PCI device must be responsive
3245 * to PCI config space in order to use this function.
3247 * This function does not just reset the PCI portion of a device, but
3248 * clears all the state associated with the device. This function differs
3249 * from __pci_reset_function in that it saves and restores device state
3252 * Returns 0 if the device function was successfully reset or negative if the
3253 * device doesn't support resetting a single function.
3255 int pci_reset_function(struct pci_dev
*dev
)
3259 rc
= pci_dev_reset(dev
, 1);
3263 pci_save_state(dev
);
3266 * both INTx and MSI are disabled after the Interrupt Disable bit
3267 * is set and the Bus Master bit is cleared.
3269 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3271 rc
= pci_dev_reset(dev
, 0);
3273 pci_restore_state(dev
);
3277 EXPORT_SYMBOL_GPL(pci_reset_function
);
3280 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3281 * @dev: PCI device to query
3283 * Returns mmrbc: maximum designed memory read count in bytes
3284 * or appropriate error value.
3286 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
3291 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3295 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3298 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
3300 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
3303 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3304 * @dev: PCI device to query
3306 * Returns mmrbc: maximum memory read count in bytes
3307 * or appropriate error value.
3309 int pcix_get_mmrbc(struct pci_dev
*dev
)
3314 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3318 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3321 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
3323 EXPORT_SYMBOL(pcix_get_mmrbc
);
3326 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3327 * @dev: PCI device to query
3328 * @mmrbc: maximum memory read count in bytes
3329 * valid values are 512, 1024, 2048, 4096
3331 * If possible sets maximum memory read byte count, some bridges have erratas
3332 * that prevent this.
3334 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
3340 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
3343 v
= ffs(mmrbc
) - 10;
3345 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3349 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3352 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
3355 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3358 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
3360 if (v
> o
&& dev
->bus
&&
3361 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
3364 cmd
&= ~PCI_X_CMD_MAX_READ
;
3366 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
3371 EXPORT_SYMBOL(pcix_set_mmrbc
);
3374 * pcie_get_readrq - get PCI Express read request size
3375 * @dev: PCI device to query
3377 * Returns maximum memory read request in bytes
3378 * or appropriate error value.
3380 int pcie_get_readrq(struct pci_dev
*dev
)
3385 cap
= pci_pcie_cap(dev
);
3389 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3391 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
3395 EXPORT_SYMBOL(pcie_get_readrq
);
3398 * pcie_set_readrq - set PCI Express maximum memory read request
3399 * @dev: PCI device to query
3400 * @rq: maximum memory read count in bytes
3401 * valid values are 128, 256, 512, 1024, 2048, 4096
3403 * If possible sets maximum memory read request in bytes
3405 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
3407 int cap
, err
= -EINVAL
;
3410 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
3413 cap
= pci_pcie_cap(dev
);
3417 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3421 * If using the "performance" PCIe config, we clamp the
3422 * read rq size to the max packet size to prevent the
3423 * host bridge generating requests larger than we can
3426 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
3427 int mps
= pcie_get_mps(dev
);
3435 v
= (ffs(rq
) - 8) << 12;
3437 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
3438 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
3440 err
= pci_write_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3446 EXPORT_SYMBOL(pcie_set_readrq
);
3449 * pcie_get_mps - get PCI Express maximum payload size
3450 * @dev: PCI device to query
3452 * Returns maximum payload size in bytes
3453 * or appropriate error value.
3455 int pcie_get_mps(struct pci_dev
*dev
)
3460 cap
= pci_pcie_cap(dev
);
3464 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3466 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
3472 * pcie_set_mps - set PCI Express maximum payload size
3473 * @dev: PCI device to query
3474 * @mps: maximum payload size in bytes
3475 * valid values are 128, 256, 512, 1024, 2048, 4096
3477 * If possible sets maximum payload size
3479 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
3481 int cap
, err
= -EINVAL
;
3484 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
3488 if (v
> dev
->pcie_mpss
)
3492 cap
= pci_pcie_cap(dev
);
3496 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3500 if ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) != v
) {
3501 ctl
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
3503 err
= pci_write_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3510 * pci_select_bars - Make BAR mask from the type of resource
3511 * @dev: the PCI device for which BAR mask is made
3512 * @flags: resource type mask to be selected
3514 * This helper routine makes bar mask from the type of resource.
3516 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
3519 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
3520 if (pci_resource_flags(dev
, i
) & flags
)
3526 * pci_resource_bar - get position of the BAR associated with a resource
3527 * @dev: the PCI device
3528 * @resno: the resource number
3529 * @type: the BAR type to be filled in
3531 * Returns BAR position in config space, or 0 if the BAR is invalid.
3533 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
3537 if (resno
< PCI_ROM_RESOURCE
) {
3538 *type
= pci_bar_unknown
;
3539 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
3540 } else if (resno
== PCI_ROM_RESOURCE
) {
3541 *type
= pci_bar_mem32
;
3542 return dev
->rom_base_reg
;
3543 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
3544 /* device specific resource */
3545 reg
= pci_iov_resource_bar(dev
, resno
, type
);
3550 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
3554 /* Some architectures require additional programming to enable VGA */
3555 static arch_set_vga_state_t arch_set_vga_state
;
3557 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
3559 arch_set_vga_state
= func
; /* NULL disables */
3562 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
3563 unsigned int command_bits
, u32 flags
)
3565 if (arch_set_vga_state
)
3566 return arch_set_vga_state(dev
, decode
, command_bits
,
3572 * pci_set_vga_state - set VGA decode state on device and parents if requested
3573 * @dev: the PCI device
3574 * @decode: true = enable decoding, false = disable decoding
3575 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3576 * @flags: traverse ancestors and change bridges
3577 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3579 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
3580 unsigned int command_bits
, u32 flags
)
3582 struct pci_bus
*bus
;
3583 struct pci_dev
*bridge
;
3587 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) & (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
3589 /* ARCH specific VGA enables */
3590 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
3594 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
3595 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3597 cmd
|= command_bits
;
3599 cmd
&= ~command_bits
;
3600 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3603 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
3610 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3613 cmd
|= PCI_BRIDGE_CTL_VGA
;
3615 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
3616 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3624 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3625 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
3626 static DEFINE_SPINLOCK(resource_alignment_lock
);
3629 * pci_specified_resource_alignment - get resource alignment specified by user.
3630 * @dev: the PCI device to get
3632 * RETURNS: Resource alignment if it is specified.
3633 * Zero if it is not specified.
3635 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
3637 int seg
, bus
, slot
, func
, align_order
, count
;
3638 resource_size_t align
= 0;
3641 spin_lock(&resource_alignment_lock
);
3642 p
= resource_alignment_param
;
3645 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
3651 if (sscanf(p
, "%x:%x:%x.%x%n",
3652 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
3654 if (sscanf(p
, "%x:%x.%x%n",
3655 &bus
, &slot
, &func
, &count
) != 3) {
3656 /* Invalid format */
3657 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
3663 if (seg
== pci_domain_nr(dev
->bus
) &&
3664 bus
== dev
->bus
->number
&&
3665 slot
== PCI_SLOT(dev
->devfn
) &&
3666 func
== PCI_FUNC(dev
->devfn
)) {
3667 if (align_order
== -1) {
3670 align
= 1 << align_order
;
3675 if (*p
!= ';' && *p
!= ',') {
3676 /* End of param or invalid format */
3681 spin_unlock(&resource_alignment_lock
);
3686 * pci_is_reassigndev - check if specified PCI is target device to reassign
3687 * @dev: the PCI device to check
3689 * RETURNS: non-zero for PCI device is a target device to reassign,
3692 int pci_is_reassigndev(struct pci_dev
*dev
)
3694 return (pci_specified_resource_alignment(dev
) != 0);
3697 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
3699 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
3700 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
3701 spin_lock(&resource_alignment_lock
);
3702 strncpy(resource_alignment_param
, buf
, count
);
3703 resource_alignment_param
[count
] = '\0';
3704 spin_unlock(&resource_alignment_lock
);
3708 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
3711 spin_lock(&resource_alignment_lock
);
3712 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
3713 spin_unlock(&resource_alignment_lock
);
3717 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
3719 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
3722 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
3723 const char *buf
, size_t count
)
3725 return pci_set_resource_alignment_param(buf
, count
);
3728 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
3729 pci_resource_alignment_store
);
3731 static int __init
pci_resource_alignment_sysfs_init(void)
3733 return bus_create_file(&pci_bus_type
,
3734 &bus_attr_resource_alignment
);
3737 late_initcall(pci_resource_alignment_sysfs_init
);
3739 static void __devinit
pci_no_domains(void)
3741 #ifdef CONFIG_PCI_DOMAINS
3742 pci_domains_supported
= 0;
3747 * pci_ext_cfg_enabled - can we access extended PCI config space?
3748 * @dev: The PCI device of the root bridge.
3750 * Returns 1 if we can access PCI extended config space (offsets
3751 * greater than 0xff). This is the default implementation. Architecture
3752 * implementations can override this.
3754 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
3759 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
3762 EXPORT_SYMBOL(pci_fixup_cardbus
);
3764 static int __init
pci_setup(char *str
)
3767 char *k
= strchr(str
, ',');
3770 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
3771 if (!strcmp(str
, "nomsi")) {
3773 } else if (!strcmp(str
, "noaer")) {
3775 } else if (!strncmp(str
, "realloc=", 8)) {
3776 pci_realloc_get_opt(str
+ 8);
3777 } else if (!strncmp(str
, "realloc", 7)) {
3778 pci_realloc_get_opt("on");
3779 } else if (!strcmp(str
, "nodomains")) {
3781 } else if (!strncmp(str
, "cbiosize=", 9)) {
3782 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
3783 } else if (!strncmp(str
, "cbmemsize=", 10)) {
3784 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
3785 } else if (!strncmp(str
, "resource_alignment=", 19)) {
3786 pci_set_resource_alignment_param(str
+ 19,
3788 } else if (!strncmp(str
, "ecrc=", 5)) {
3789 pcie_ecrc_get_policy(str
+ 5);
3790 } else if (!strncmp(str
, "hpiosize=", 9)) {
3791 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
3792 } else if (!strncmp(str
, "hpmemsize=", 10)) {
3793 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
3794 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
3795 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
3796 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
3797 pcie_bus_config
= PCIE_BUS_SAFE
;
3798 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
3799 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
3800 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
3801 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
3803 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
3811 early_param("pci", pci_setup
);
3813 EXPORT_SYMBOL(pci_reenable_device
);
3814 EXPORT_SYMBOL(pci_enable_device_io
);
3815 EXPORT_SYMBOL(pci_enable_device_mem
);
3816 EXPORT_SYMBOL(pci_enable_device
);
3817 EXPORT_SYMBOL(pcim_enable_device
);
3818 EXPORT_SYMBOL(pcim_pin_device
);
3819 EXPORT_SYMBOL(pci_disable_device
);
3820 EXPORT_SYMBOL(pci_find_capability
);
3821 EXPORT_SYMBOL(pci_bus_find_capability
);
3822 EXPORT_SYMBOL(pci_release_regions
);
3823 EXPORT_SYMBOL(pci_request_regions
);
3824 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3825 EXPORT_SYMBOL(pci_release_region
);
3826 EXPORT_SYMBOL(pci_request_region
);
3827 EXPORT_SYMBOL(pci_request_region_exclusive
);
3828 EXPORT_SYMBOL(pci_release_selected_regions
);
3829 EXPORT_SYMBOL(pci_request_selected_regions
);
3830 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3831 EXPORT_SYMBOL(pci_set_master
);
3832 EXPORT_SYMBOL(pci_clear_master
);
3833 EXPORT_SYMBOL(pci_set_mwi
);
3834 EXPORT_SYMBOL(pci_try_set_mwi
);
3835 EXPORT_SYMBOL(pci_clear_mwi
);
3836 EXPORT_SYMBOL_GPL(pci_intx
);
3837 EXPORT_SYMBOL(pci_assign_resource
);
3838 EXPORT_SYMBOL(pci_find_parent_resource
);
3839 EXPORT_SYMBOL(pci_select_bars
);
3841 EXPORT_SYMBOL(pci_set_power_state
);
3842 EXPORT_SYMBOL(pci_save_state
);
3843 EXPORT_SYMBOL(pci_restore_state
);
3844 EXPORT_SYMBOL(pci_pme_capable
);
3845 EXPORT_SYMBOL(pci_pme_active
);
3846 EXPORT_SYMBOL(pci_wake_from_d3
);
3847 EXPORT_SYMBOL(pci_target_state
);
3848 EXPORT_SYMBOL(pci_prepare_to_sleep
);
3849 EXPORT_SYMBOL(pci_back_from_sleep
);
3850 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);