2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay
= 10;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported
= 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
35 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
46 struct list_head
*tmp
;
49 max
= bus
->subordinate
;
50 list_for_each(tmp
, &bus
->children
) {
51 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
59 #ifdef CONFIG_HAS_IOMEM
60 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
63 * Make sure the BAR is actually a memory resource, not an IO resource
65 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
69 return ioremap_nocache(pci_resource_start(pdev
, bar
),
70 pci_resource_len(pdev
, bar
));
72 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
77 * pci_max_busnr - returns maximum PCI bus number
79 * Returns the highest PCI bus number present in the system global list of
82 unsigned char __devinit
85 struct pci_bus
*bus
= NULL
;
89 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
90 n
= pci_bus_max_busnr(bus
);
99 #define PCI_FIND_CAP_TTL 48
101 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
102 u8 pos
, int cap
, int *ttl
)
107 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
111 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
117 pos
+= PCI_CAP_LIST_NEXT
;
122 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
125 int ttl
= PCI_FIND_CAP_TTL
;
127 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
130 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
132 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
133 pos
+ PCI_CAP_LIST_NEXT
, cap
);
135 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
137 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
138 unsigned int devfn
, u8 hdr_type
)
142 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
143 if (!(status
& PCI_STATUS_CAP_LIST
))
147 case PCI_HEADER_TYPE_NORMAL
:
148 case PCI_HEADER_TYPE_BRIDGE
:
149 return PCI_CAPABILITY_LIST
;
150 case PCI_HEADER_TYPE_CARDBUS
:
151 return PCI_CB_CAPABILITY_LIST
;
160 * pci_find_capability - query for devices' capabilities
161 * @dev: PCI device to query
162 * @cap: capability code
164 * Tell if a device supports a given PCI capability.
165 * Returns the address of the requested capability structure within the
166 * device's PCI configuration space or 0 in case the device does not
167 * support it. Possible values for @cap:
169 * %PCI_CAP_ID_PM Power Management
170 * %PCI_CAP_ID_AGP Accelerated Graphics Port
171 * %PCI_CAP_ID_VPD Vital Product Data
172 * %PCI_CAP_ID_SLOTID Slot Identification
173 * %PCI_CAP_ID_MSI Message Signalled Interrupts
174 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
175 * %PCI_CAP_ID_PCIX PCI-X
176 * %PCI_CAP_ID_EXP PCI Express
178 int pci_find_capability(struct pci_dev
*dev
, int cap
)
182 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
184 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
190 * pci_bus_find_capability - query for devices' capabilities
191 * @bus: the PCI bus to query
192 * @devfn: PCI device to query
193 * @cap: capability code
195 * Like pci_find_capability() but works for pci devices that do not have a
196 * pci_dev structure set up yet.
198 * Returns the address of the requested capability structure within the
199 * device's PCI configuration space or 0 in case the device does not
202 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
207 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
209 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
211 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
217 * pci_find_ext_capability - Find an extended capability
218 * @dev: PCI device to query
219 * @cap: capability code
221 * Returns the address of the requested extended capability structure
222 * within the device's PCI configuration space or 0 if the device does
223 * not support it. Possible values for @cap:
225 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
226 * %PCI_EXT_CAP_ID_VC Virtual Channel
227 * %PCI_EXT_CAP_ID_DSN Device Serial Number
228 * %PCI_EXT_CAP_ID_PWR Power Budgeting
230 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
234 int pos
= PCI_CFG_SPACE_SIZE
;
236 /* minimum 8 bytes per capability */
237 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
239 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
242 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
246 * If we have no capabilities, this is indicated by cap ID,
247 * cap version and next pointer all being 0.
253 if (PCI_EXT_CAP_ID(header
) == cap
)
256 pos
= PCI_EXT_CAP_NEXT(header
);
257 if (pos
< PCI_CFG_SPACE_SIZE
)
260 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
266 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
268 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
270 int rc
, ttl
= PCI_FIND_CAP_TTL
;
273 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
274 mask
= HT_3BIT_CAP_MASK
;
276 mask
= HT_5BIT_CAP_MASK
;
278 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
279 PCI_CAP_ID_HT
, &ttl
);
281 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
282 if (rc
!= PCIBIOS_SUCCESSFUL
)
285 if ((cap
& mask
) == ht_cap
)
288 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
289 pos
+ PCI_CAP_LIST_NEXT
,
290 PCI_CAP_ID_HT
, &ttl
);
296 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
297 * @dev: PCI device to query
298 * @pos: Position from which to continue searching
299 * @ht_cap: Hypertransport capability code
301 * To be used in conjunction with pci_find_ht_capability() to search for
302 * all capabilities matching @ht_cap. @pos should always be a value returned
303 * from pci_find_ht_capability().
305 * NB. To be 100% safe against broken PCI devices, the caller should take
306 * steps to avoid an infinite loop.
308 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
310 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
312 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
315 * pci_find_ht_capability - query a device's Hypertransport capabilities
316 * @dev: PCI device to query
317 * @ht_cap: Hypertransport capability code
319 * Tell if a device supports a given Hypertransport capability.
320 * Returns an address within the device's PCI configuration space
321 * or 0 in case the device does not support the request capability.
322 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
323 * which has a Hypertransport capability matching @ht_cap.
325 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
329 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
331 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
335 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
338 * pci_find_parent_resource - return resource region of parent bus of given region
339 * @dev: PCI device structure contains resources to be searched
340 * @res: child resource record for which parent is sought
342 * For given resource region of given device, return the resource
343 * region of parent bus the given region is contained in or where
344 * it should be allocated from.
347 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
349 const struct pci_bus
*bus
= dev
->bus
;
351 struct resource
*best
= NULL
;
353 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
354 struct resource
*r
= bus
->resource
[i
];
357 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
358 continue; /* Not contained */
359 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
360 continue; /* Wrong type */
361 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
362 return r
; /* Exact match */
363 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
364 best
= r
; /* Approximating prefetchable by non-prefetchable */
370 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
371 * @dev: PCI device to have its BARs restored
373 * Restore the BAR values for a given device, so as to make it
374 * accessible by its driver.
377 pci_restore_bars(struct pci_dev
*dev
)
381 switch (dev
->hdr_type
) {
382 case PCI_HEADER_TYPE_NORMAL
:
385 case PCI_HEADER_TYPE_BRIDGE
:
388 case PCI_HEADER_TYPE_CARDBUS
:
392 /* Should never get here, but just in case... */
396 for (i
= 0; i
< numres
; i
++)
397 pci_update_resource(dev
, i
);
400 static struct pci_platform_pm_ops
*pci_platform_pm
;
402 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
404 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
405 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
407 pci_platform_pm
= ops
;
411 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
413 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
416 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
419 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
422 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
424 return pci_platform_pm
?
425 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
428 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
430 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
433 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
435 return pci_platform_pm
?
436 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
440 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
442 * @dev: PCI device to handle.
443 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
446 * -EINVAL if the requested state is invalid.
447 * -EIO if device does not support PCI PM or its PM capabilities register has a
448 * wrong version, or device doesn't support the requested state.
449 * 0 if device already is in the requested state.
450 * 0 if device's power state has been successfully changed.
453 pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
456 bool need_restore
= false;
461 if (state
< PCI_D0
|| state
> PCI_D3hot
)
464 /* Validate current state:
465 * Can enter D0 from any state, but if we can only go deeper
466 * to sleep if we're already in a low power state
468 if (dev
->current_state
== state
) {
469 /* we're already there */
471 } else if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
472 && dev
->current_state
> state
) {
473 dev_err(&dev
->dev
, "invalid power transition "
474 "(from state %d to %d)\n", dev
->current_state
, state
);
478 /* check if this device supports the desired state */
479 if ((state
== PCI_D1
&& !dev
->d1_support
)
480 || (state
== PCI_D2
&& !dev
->d2_support
))
483 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
485 /* If we're (effectively) in D3, force entire word to 0.
486 * This doesn't affect PME_Status, disables PME_En, and
487 * sets PowerState to 0.
489 switch (dev
->current_state
) {
493 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
496 case PCI_UNKNOWN
: /* Boot-up */
497 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
498 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
500 /* Fall-through: force to D0 */
506 /* enter specified state */
507 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
509 /* Mandatory power management transition delays */
510 /* see PCI PM 1.1 5.6.1 table 18 */
511 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
512 msleep(pci_pm_d3_delay
);
513 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
516 dev
->current_state
= state
;
518 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
519 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
520 * from D3hot to D0 _may_ perform an internal reset, thereby
521 * going to "D0 Uninitialized" rather than "D0 Initialized".
522 * For example, at least some versions of the 3c905B and the
523 * 3c556B exhibit this behaviour.
525 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
526 * devices in a D3hot state at boot. Consequently, we need to
527 * restore at least the BARs so that the device will be
528 * accessible to its driver.
531 pci_restore_bars(dev
);
534 pcie_aspm_pm_state_change(dev
->bus
->self
);
540 * pci_update_current_state - Read PCI power state of given device from its
541 * PCI PM registers and cache it
542 * @dev: PCI device to handle.
544 static void pci_update_current_state(struct pci_dev
*dev
)
549 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
550 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
555 * pci_set_power_state - Set the power state of a PCI device
556 * @dev: PCI device to handle.
557 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
559 * Transition a device to a new power state, using the platform formware and/or
560 * the device's PCI PM registers.
563 * -EINVAL if the requested state is invalid.
564 * -EIO if device does not support PCI PM or its PM capabilities register has a
565 * wrong version, or device doesn't support the requested state.
566 * 0 if device already is in the requested state.
567 * 0 if device's power state has been successfully changed.
569 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
573 /* bound the state we're entering */
574 if (state
> PCI_D3hot
)
576 else if (state
< PCI_D0
)
578 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
580 * If the device or the parent bridge do not support PCI PM,
581 * ignore the request if we're doing anything other than putting
582 * it into D0 (which would only happen on boot).
586 if (state
== PCI_D0
&& platform_pci_power_manageable(dev
)) {
588 * Allow the platform to change the state, for example via ACPI
589 * _PR0, _PS0 and some such, but do not trust it.
591 int ret
= platform_pci_set_power_state(dev
, PCI_D0
);
593 pci_update_current_state(dev
);
595 /* This device is quirked not to be put into D3, so
596 don't put it in D3 */
597 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
600 error
= pci_raw_set_power_state(dev
, state
);
602 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
603 /* Allow the platform to finalize the transition */
604 int ret
= platform_pci_set_power_state(dev
, state
);
606 pci_update_current_state(dev
);
615 * pci_choose_state - Choose the power state of a PCI device
616 * @dev: PCI device to be suspended
617 * @state: target sleep state for the whole system. This is the value
618 * that is passed to suspend() function.
620 * Returns PCI power state suitable for given device and given system
624 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
628 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
631 ret
= platform_pci_choose_state(dev
);
632 if (ret
!= PCI_POWER_ERROR
)
635 switch (state
.event
) {
638 case PM_EVENT_FREEZE
:
639 case PM_EVENT_PRETHAW
:
640 /* REVISIT both freeze and pre-thaw "should" use D0 */
641 case PM_EVENT_SUSPEND
:
642 case PM_EVENT_HIBERNATE
:
645 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
652 EXPORT_SYMBOL(pci_choose_state
);
654 static int pci_save_pcie_state(struct pci_dev
*dev
)
657 struct pci_cap_saved_state
*save_state
;
660 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
664 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
666 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
669 cap
= (u16
*)&save_state
->data
[0];
671 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
672 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
673 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
674 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
679 static void pci_restore_pcie_state(struct pci_dev
*dev
)
682 struct pci_cap_saved_state
*save_state
;
685 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
686 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
687 if (!save_state
|| pos
<= 0)
689 cap
= (u16
*)&save_state
->data
[0];
691 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
692 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
693 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
694 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
698 static int pci_save_pcix_state(struct pci_dev
*dev
)
701 struct pci_cap_saved_state
*save_state
;
703 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
707 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
709 dev_err(&dev
->dev
, "buffer not found in %s\n", __FUNCTION__
);
713 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
718 static void pci_restore_pcix_state(struct pci_dev
*dev
)
721 struct pci_cap_saved_state
*save_state
;
724 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
725 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
726 if (!save_state
|| pos
<= 0)
728 cap
= (u16
*)&save_state
->data
[0];
730 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
735 * pci_save_state - save the PCI configuration space of a device before suspending
736 * @dev: - PCI device that we're dealing with
739 pci_save_state(struct pci_dev
*dev
)
742 /* XXX: 100% dword access ok here? */
743 for (i
= 0; i
< 16; i
++)
744 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
745 if ((i
= pci_save_pcie_state(dev
)) != 0)
747 if ((i
= pci_save_pcix_state(dev
)) != 0)
753 * pci_restore_state - Restore the saved state of a PCI device
754 * @dev: - PCI device that we're dealing with
757 pci_restore_state(struct pci_dev
*dev
)
762 /* PCI Express register must be restored first */
763 pci_restore_pcie_state(dev
);
766 * The Base Address register should be programmed before the command
769 for (i
= 15; i
>= 0; i
--) {
770 pci_read_config_dword(dev
, i
* 4, &val
);
771 if (val
!= dev
->saved_config_space
[i
]) {
772 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
773 "space at offset %#x (was %#x, writing %#x)\n",
774 i
, val
, (int)dev
->saved_config_space
[i
]);
775 pci_write_config_dword(dev
,i
* 4,
776 dev
->saved_config_space
[i
]);
779 pci_restore_pcix_state(dev
);
780 pci_restore_msi_state(dev
);
785 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
789 err
= pci_set_power_state(dev
, PCI_D0
);
790 if (err
< 0 && err
!= -EIO
)
792 err
= pcibios_enable_device(dev
, bars
);
795 pci_fixup_device(pci_fixup_enable
, dev
);
801 * pci_reenable_device - Resume abandoned device
802 * @dev: PCI device to be resumed
804 * Note this function is a backend of pci_default_resume and is not supposed
805 * to be called by normal code, write proper resume handler and use it instead.
807 int pci_reenable_device(struct pci_dev
*dev
)
809 if (atomic_read(&dev
->enable_cnt
))
810 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
814 static int __pci_enable_device_flags(struct pci_dev
*dev
,
815 resource_size_t flags
)
820 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
821 return 0; /* already enabled */
823 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
824 if (dev
->resource
[i
].flags
& flags
)
827 err
= do_pci_enable_device(dev
, bars
);
829 atomic_dec(&dev
->enable_cnt
);
834 * pci_enable_device_io - Initialize a device for use with IO space
835 * @dev: PCI device to be initialized
837 * Initialize device before it's used by a driver. Ask low-level code
838 * to enable I/O resources. Wake up the device if it was suspended.
839 * Beware, this function can fail.
841 int pci_enable_device_io(struct pci_dev
*dev
)
843 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
847 * pci_enable_device_mem - Initialize a device for use with Memory space
848 * @dev: PCI device to be initialized
850 * Initialize device before it's used by a driver. Ask low-level code
851 * to enable Memory resources. Wake up the device if it was suspended.
852 * Beware, this function can fail.
854 int pci_enable_device_mem(struct pci_dev
*dev
)
856 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
860 * pci_enable_device - Initialize device before it's used by a driver.
861 * @dev: PCI device to be initialized
863 * Initialize device before it's used by a driver. Ask low-level code
864 * to enable I/O and memory. Wake up the device if it was suspended.
865 * Beware, this function can fail.
867 * Note we don't actually enable the device many times if we call
868 * this function repeatedly (we just increment the count).
870 int pci_enable_device(struct pci_dev
*dev
)
872 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
876 * Managed PCI resources. This manages device on/off, intx/msi/msix
877 * on/off and BAR regions. pci_dev itself records msi/msix status, so
878 * there's no need to track it separately. pci_devres is initialized
879 * when a device is enabled using managed PCI device enable interface.
882 unsigned int enabled
:1;
883 unsigned int pinned
:1;
884 unsigned int orig_intx
:1;
885 unsigned int restore_intx
:1;
889 static void pcim_release(struct device
*gendev
, void *res
)
891 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
892 struct pci_devres
*this = res
;
895 if (dev
->msi_enabled
)
896 pci_disable_msi(dev
);
897 if (dev
->msix_enabled
)
898 pci_disable_msix(dev
);
900 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
901 if (this->region_mask
& (1 << i
))
902 pci_release_region(dev
, i
);
904 if (this->restore_intx
)
905 pci_intx(dev
, this->orig_intx
);
907 if (this->enabled
&& !this->pinned
)
908 pci_disable_device(dev
);
911 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
913 struct pci_devres
*dr
, *new_dr
;
915 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
919 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
922 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
925 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
927 if (pci_is_managed(pdev
))
928 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
933 * pcim_enable_device - Managed pci_enable_device()
934 * @pdev: PCI device to be initialized
936 * Managed pci_enable_device().
938 int pcim_enable_device(struct pci_dev
*pdev
)
940 struct pci_devres
*dr
;
943 dr
= get_pci_dr(pdev
);
949 rc
= pci_enable_device(pdev
);
951 pdev
->is_managed
= 1;
958 * pcim_pin_device - Pin managed PCI device
959 * @pdev: PCI device to pin
961 * Pin managed PCI device @pdev. Pinned device won't be disabled on
962 * driver detach. @pdev must have been enabled with
963 * pcim_enable_device().
965 void pcim_pin_device(struct pci_dev
*pdev
)
967 struct pci_devres
*dr
;
969 dr
= find_pci_dr(pdev
);
970 WARN_ON(!dr
|| !dr
->enabled
);
976 * pcibios_disable_device - disable arch specific PCI resources for device dev
977 * @dev: the PCI device to disable
979 * Disables architecture specific PCI resources for the device. This
980 * is the default implementation. Architecture implementations can
983 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
986 * pci_disable_device - Disable PCI device after use
987 * @dev: PCI device to be disabled
989 * Signal to the system that the PCI device is not in use by the system
990 * anymore. This only involves disabling PCI bus-mastering, if active.
992 * Note we don't actually disable the device until all callers of
993 * pci_device_enable() have called pci_device_disable().
996 pci_disable_device(struct pci_dev
*dev
)
998 struct pci_devres
*dr
;
1001 dr
= find_pci_dr(dev
);
1005 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1008 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1009 if (pci_command
& PCI_COMMAND_MASTER
) {
1010 pci_command
&= ~PCI_COMMAND_MASTER
;
1011 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1013 dev
->is_busmaster
= 0;
1015 pcibios_disable_device(dev
);
1019 * pcibios_set_pcie_reset_state - set reset state for device dev
1020 * @dev: the PCI-E device reset
1021 * @state: Reset state to enter into
1024 * Sets the PCI-E reset state for the device. This is the default
1025 * implementation. Architecture implementations can override this.
1027 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1028 enum pcie_reset_state state
)
1034 * pci_set_pcie_reset_state - set reset state for device dev
1035 * @dev: the PCI-E device reset
1036 * @state: Reset state to enter into
1039 * Sets the PCI reset state for the device.
1041 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1043 return pcibios_set_pcie_reset_state(dev
, state
);
1047 * pci_pme_capable - check the capability of PCI device to generate PME#
1048 * @dev: PCI device to handle.
1049 * @state: PCI state from which device will issue PME#.
1051 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1056 return !!(dev
->pme_support
& (1 << state
));
1060 * pci_pme_active - enable or disable PCI device's PME# function
1061 * @dev: PCI device to handle.
1062 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1064 * The caller must verify that the device is capable of generating PME# before
1065 * calling this function with @enable equal to 'true'.
1067 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1074 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1075 /* Clear PME_Status by writing 1 to it and enable PME# */
1076 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1078 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1080 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1082 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1083 enable
? "enabled" : "disabled");
1087 * pci_enable_wake - enable PCI device as wakeup event source
1088 * @dev: PCI device affected
1089 * @state: PCI state from which device will issue wakeup events
1090 * @enable: True to enable event generation; false to disable
1092 * This enables the device as a wakeup event source, or disables it.
1093 * When such events involves platform-specific hooks, those hooks are
1094 * called automatically by this routine.
1096 * Devices with legacy power management (no standard PCI PM capabilities)
1097 * always require such platform hooks.
1100 * 0 is returned on success
1101 * -EINVAL is returned if device is not supposed to wake up the system
1102 * Error code depending on the platform is returned if both the platform and
1103 * the native mechanism fail to enable the generation of wake-up events
1105 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1108 bool pme_done
= false;
1110 if (enable
&& !device_may_wakeup(&dev
->dev
))
1114 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1115 * Anderson we should be doing PME# wake enable followed by ACPI wake
1116 * enable. To disable wake-up we call the platform first, for symmetry.
1119 if (!enable
&& platform_pci_can_wakeup(dev
))
1120 error
= platform_pci_sleep_wake(dev
, false);
1122 if (!enable
|| pci_pme_capable(dev
, state
)) {
1123 pci_pme_active(dev
, enable
);
1127 if (enable
&& platform_pci_can_wakeup(dev
))
1128 error
= platform_pci_sleep_wake(dev
, true);
1130 return pme_done
? 0 : error
;
1134 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1135 * @dev: PCI device to prepare
1136 * @enable: True to enable wake-up event generation; false to disable
1138 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1139 * and this function allows them to set that up cleanly - pci_enable_wake()
1140 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1141 * ordering constraints.
1143 * This function only returns error code if the device is not capable of
1144 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1145 * enable wake-up power for it.
1147 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1149 return pci_pme_capable(dev
, PCI_D3cold
) ?
1150 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1151 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1155 * pci_target_state - find an appropriate low power state for a given PCI dev
1158 * Use underlying platform code to find a supported low power state for @dev.
1159 * If the platform can't manage @dev, return the deepest state from which it
1160 * can generate wake events, based on any available PME info.
1162 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1164 pci_power_t target_state
= PCI_D3hot
;
1166 if (platform_pci_power_manageable(dev
)) {
1168 * Call the platform to choose the target state of the device
1169 * and enable wake-up from this state if supported.
1171 pci_power_t state
= platform_pci_choose_state(dev
);
1174 case PCI_POWER_ERROR
:
1179 if (pci_no_d1d2(dev
))
1182 target_state
= state
;
1184 } else if (device_may_wakeup(&dev
->dev
)) {
1186 * Find the deepest state from which the device can generate
1187 * wake-up events, make it the target state and enable device
1191 return PCI_POWER_ERROR
;
1193 if (dev
->pme_support
) {
1195 && !(dev
->pme_support
& (1 << target_state
)))
1200 return target_state
;
1204 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1205 * @dev: Device to handle.
1207 * Choose the power state appropriate for the device depending on whether
1208 * it can wake up the system and/or is power manageable by the platform
1209 * (PCI_D3hot is the default) and put the device into that state.
1211 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1213 pci_power_t target_state
= pci_target_state(dev
);
1216 if (target_state
== PCI_POWER_ERROR
)
1219 pci_enable_wake(dev
, target_state
, true);
1221 error
= pci_set_power_state(dev
, target_state
);
1224 pci_enable_wake(dev
, target_state
, false);
1230 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1231 * @dev: Device to handle.
1233 * Disable device's sytem wake-up capability and put it into D0.
1235 int pci_back_from_sleep(struct pci_dev
*dev
)
1237 pci_enable_wake(dev
, PCI_D0
, false);
1238 return pci_set_power_state(dev
, PCI_D0
);
1242 * pci_pm_init - Initialize PM functions of given PCI device
1243 * @dev: PCI device to handle.
1245 void pci_pm_init(struct pci_dev
*dev
)
1252 /* find PCI PM capability in list */
1253 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1256 /* Check device's ability to generate PME# */
1257 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1259 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1260 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1261 pmc
& PCI_PM_CAP_VER_MASK
);
1267 dev
->d1_support
= false;
1268 dev
->d2_support
= false;
1269 if (!pci_no_d1d2(dev
)) {
1270 if (pmc
& PCI_PM_CAP_D1
)
1271 dev
->d1_support
= true;
1272 if (pmc
& PCI_PM_CAP_D2
)
1273 dev
->d2_support
= true;
1275 if (dev
->d1_support
|| dev
->d2_support
)
1276 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1277 dev
->d1_support
? " D1" : "",
1278 dev
->d2_support
? " D2" : "");
1281 pmc
&= PCI_PM_CAP_PME_MASK
;
1283 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1284 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1285 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1286 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1287 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1288 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1289 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1291 * Make device's PM flags reflect the wake-up capability, but
1292 * let the user space enable it to wake up the system as needed.
1294 device_set_wakeup_capable(&dev
->dev
, true);
1295 device_set_wakeup_enable(&dev
->dev
, false);
1296 /* Disable the PME# generation functionality */
1297 pci_pme_active(dev
, false);
1299 dev
->pme_support
= 0;
1304 * pci_add_save_buffer - allocate buffer for saving given capability registers
1305 * @dev: the PCI device
1306 * @cap: the capability to allocate the buffer for
1307 * @size: requested size of the buffer
1309 static int pci_add_cap_save_buffer(
1310 struct pci_dev
*dev
, char cap
, unsigned int size
)
1313 struct pci_cap_saved_state
*save_state
;
1315 pos
= pci_find_capability(dev
, cap
);
1319 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1323 save_state
->cap_nr
= cap
;
1324 pci_add_saved_cap(dev
, save_state
);
1330 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1331 * @dev: the PCI device
1333 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1337 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
, 4 * sizeof(u16
));
1340 "unable to preallocate PCI Express save buffer\n");
1342 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1345 "unable to preallocate PCI-X save buffer\n");
1349 * pci_enable_ari - enable ARI forwarding if hardware support it
1350 * @dev: the PCI device
1352 void pci_enable_ari(struct pci_dev
*dev
)
1357 struct pci_dev
*bridge
;
1359 if (!dev
->is_pcie
|| dev
->devfn
)
1362 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1366 bridge
= dev
->bus
->self
;
1367 if (!bridge
|| !bridge
->is_pcie
)
1370 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1374 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1375 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1378 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1379 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1380 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1382 bridge
->ari_enabled
= 1;
1386 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1387 * @dev: the PCI device
1388 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1390 * Perform INTx swizzling for a device behind one level of bridge. This is
1391 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1392 * behind bridges on add-in cards.
1394 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1396 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1400 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1408 while (dev
->bus
->self
) {
1409 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1410 dev
= dev
->bus
->self
;
1417 * pci_release_region - Release a PCI bar
1418 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1419 * @bar: BAR to release
1421 * Releases the PCI I/O and memory resources previously reserved by a
1422 * successful call to pci_request_region. Call this function only
1423 * after all use of the PCI regions has ceased.
1425 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1427 struct pci_devres
*dr
;
1429 if (pci_resource_len(pdev
, bar
) == 0)
1431 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1432 release_region(pci_resource_start(pdev
, bar
),
1433 pci_resource_len(pdev
, bar
));
1434 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1435 release_mem_region(pci_resource_start(pdev
, bar
),
1436 pci_resource_len(pdev
, bar
));
1438 dr
= find_pci_dr(pdev
);
1440 dr
->region_mask
&= ~(1 << bar
);
1444 * pci_request_region - Reserved PCI I/O and memory resource
1445 * @pdev: PCI device whose resources are to be reserved
1446 * @bar: BAR to be reserved
1447 * @res_name: Name to be associated with resource.
1449 * Mark the PCI region associated with PCI device @pdev BR @bar as
1450 * being reserved by owner @res_name. Do not access any
1451 * address inside the PCI regions unless this call returns
1454 * Returns 0 on success, or %EBUSY on error. A warning
1455 * message is also printed on failure.
1457 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1460 struct pci_devres
*dr
;
1462 if (pci_resource_len(pdev
, bar
) == 0)
1465 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1466 if (!request_region(pci_resource_start(pdev
, bar
),
1467 pci_resource_len(pdev
, bar
), res_name
))
1470 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1471 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1472 pci_resource_len(pdev
, bar
), res_name
,
1477 dr
= find_pci_dr(pdev
);
1479 dr
->region_mask
|= 1 << bar
;
1484 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1486 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1487 &pdev
->resource
[bar
]);
1492 * pci_request_region - Reserved PCI I/O and memory resource
1493 * @pdev: PCI device whose resources are to be reserved
1494 * @bar: BAR to be reserved
1495 * @res_name: Name to be associated with resource.
1497 * Mark the PCI region associated with PCI device @pdev BR @bar as
1498 * being reserved by owner @res_name. Do not access any
1499 * address inside the PCI regions unless this call returns
1502 * Returns 0 on success, or %EBUSY on error. A warning
1503 * message is also printed on failure.
1505 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1507 return __pci_request_region(pdev
, bar
, res_name
, 0);
1511 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1512 * @pdev: PCI device whose resources are to be reserved
1513 * @bar: BAR to be reserved
1514 * @res_name: Name to be associated with resource.
1516 * Mark the PCI region associated with PCI device @pdev BR @bar as
1517 * being reserved by owner @res_name. Do not access any
1518 * address inside the PCI regions unless this call returns
1521 * Returns 0 on success, or %EBUSY on error. A warning
1522 * message is also printed on failure.
1524 * The key difference that _exclusive makes it that userspace is
1525 * explicitly not allowed to map the resource via /dev/mem or
1528 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1530 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1533 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1534 * @pdev: PCI device whose resources were previously reserved
1535 * @bars: Bitmask of BARs to be released
1537 * Release selected PCI I/O and memory resources previously reserved.
1538 * Call this function only after all use of the PCI regions has ceased.
1540 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1544 for (i
= 0; i
< 6; i
++)
1545 if (bars
& (1 << i
))
1546 pci_release_region(pdev
, i
);
1549 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1550 const char *res_name
, int excl
)
1554 for (i
= 0; i
< 6; i
++)
1555 if (bars
& (1 << i
))
1556 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1562 if (bars
& (1 << i
))
1563 pci_release_region(pdev
, i
);
1570 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1571 * @pdev: PCI device whose resources are to be reserved
1572 * @bars: Bitmask of BARs to be requested
1573 * @res_name: Name to be associated with resource
1575 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1576 const char *res_name
)
1578 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1581 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1582 int bars
, const char *res_name
)
1584 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1585 IORESOURCE_EXCLUSIVE
);
1589 * pci_release_regions - Release reserved PCI I/O and memory resources
1590 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1592 * Releases all PCI I/O and memory resources previously reserved by a
1593 * successful call to pci_request_regions. Call this function only
1594 * after all use of the PCI regions has ceased.
1597 void pci_release_regions(struct pci_dev
*pdev
)
1599 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1603 * pci_request_regions - Reserved PCI I/O and memory resources
1604 * @pdev: PCI device whose resources are to be reserved
1605 * @res_name: Name to be associated with resource.
1607 * Mark all PCI regions associated with PCI device @pdev as
1608 * being reserved by owner @res_name. Do not access any
1609 * address inside the PCI regions unless this call returns
1612 * Returns 0 on success, or %EBUSY on error. A warning
1613 * message is also printed on failure.
1615 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1617 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1621 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1622 * @pdev: PCI device whose resources are to be reserved
1623 * @res_name: Name to be associated with resource.
1625 * Mark all PCI regions associated with PCI device @pdev as
1626 * being reserved by owner @res_name. Do not access any
1627 * address inside the PCI regions unless this call returns
1630 * pci_request_regions_exclusive() will mark the region so that
1631 * /dev/mem and the sysfs MMIO access will not be allowed.
1633 * Returns 0 on success, or %EBUSY on error. A warning
1634 * message is also printed on failure.
1636 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1638 return pci_request_selected_regions_exclusive(pdev
,
1639 ((1 << 6) - 1), res_name
);
1644 * pci_set_master - enables bus-mastering for device dev
1645 * @dev: the PCI device to enable
1647 * Enables bus-mastering on the device and calls pcibios_set_master()
1648 * to do the needed arch specific settings.
1651 pci_set_master(struct pci_dev
*dev
)
1655 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1656 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1657 dev_dbg(&dev
->dev
, "enabling bus mastering\n");
1658 cmd
|= PCI_COMMAND_MASTER
;
1659 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1661 dev
->is_busmaster
= 1;
1662 pcibios_set_master(dev
);
1665 #ifdef PCI_DISABLE_MWI
1666 int pci_set_mwi(struct pci_dev
*dev
)
1671 int pci_try_set_mwi(struct pci_dev
*dev
)
1676 void pci_clear_mwi(struct pci_dev
*dev
)
1682 #ifndef PCI_CACHE_LINE_BYTES
1683 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1686 /* This can be overridden by arch code. */
1687 /* Don't forget this is measured in 32-bit words, not bytes */
1688 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1691 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1692 * @dev: the PCI device for which MWI is to be enabled
1694 * Helper function for pci_set_mwi.
1695 * Originally copied from drivers/net/acenic.c.
1696 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1698 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1701 pci_set_cacheline_size(struct pci_dev
*dev
)
1705 if (!pci_cache_line_size
)
1706 return -EINVAL
; /* The system doesn't support MWI. */
1708 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1709 equal to or multiple of the right value. */
1710 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1711 if (cacheline_size
>= pci_cache_line_size
&&
1712 (cacheline_size
% pci_cache_line_size
) == 0)
1715 /* Write the correct value. */
1716 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1718 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1719 if (cacheline_size
== pci_cache_line_size
)
1722 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1723 "supported\n", pci_cache_line_size
<< 2);
1729 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1730 * @dev: the PCI device for which MWI is enabled
1732 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1734 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1737 pci_set_mwi(struct pci_dev
*dev
)
1742 rc
= pci_set_cacheline_size(dev
);
1746 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1747 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1748 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1749 cmd
|= PCI_COMMAND_INVALIDATE
;
1750 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1757 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1758 * @dev: the PCI device for which MWI is enabled
1760 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1761 * Callers are not required to check the return value.
1763 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1765 int pci_try_set_mwi(struct pci_dev
*dev
)
1767 int rc
= pci_set_mwi(dev
);
1772 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1773 * @dev: the PCI device to disable
1775 * Disables PCI Memory-Write-Invalidate transaction on the device
1778 pci_clear_mwi(struct pci_dev
*dev
)
1782 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1783 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1784 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1785 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1788 #endif /* ! PCI_DISABLE_MWI */
1791 * pci_intx - enables/disables PCI INTx for device dev
1792 * @pdev: the PCI device to operate on
1793 * @enable: boolean: whether to enable or disable PCI INTx
1795 * Enables/disables PCI INTx for device dev
1798 pci_intx(struct pci_dev
*pdev
, int enable
)
1800 u16 pci_command
, new;
1802 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1805 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1807 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1810 if (new != pci_command
) {
1811 struct pci_devres
*dr
;
1813 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1815 dr
= find_pci_dr(pdev
);
1816 if (dr
&& !dr
->restore_intx
) {
1817 dr
->restore_intx
= 1;
1818 dr
->orig_intx
= !enable
;
1824 * pci_msi_off - disables any msi or msix capabilities
1825 * @dev: the PCI device to operate on
1827 * If you want to use msi see pci_enable_msi and friends.
1828 * This is a lower level primitive that allows us to disable
1829 * msi operation at the device level.
1831 void pci_msi_off(struct pci_dev
*dev
)
1836 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1838 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1839 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1840 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1842 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1844 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1845 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1846 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1850 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1852 * These can be overridden by arch-specific implementations
1855 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1857 if (!pci_dma_supported(dev
, mask
))
1860 dev
->dma_mask
= mask
;
1866 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1868 if (!pci_dma_supported(dev
, mask
))
1871 dev
->dev
.coherent_dma_mask
= mask
;
1877 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1878 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1880 return dma_set_max_seg_size(&dev
->dev
, size
);
1882 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1885 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1886 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1888 return dma_set_seg_boundary(&dev
->dev
, mask
);
1890 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1893 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
1897 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1901 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
1902 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
1908 pci_block_user_cfg_access(dev
);
1910 /* Wait for Transaction Pending bit clean */
1912 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1913 if (status
& PCI_EXP_DEVSTA_TRPND
) {
1914 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
1915 "sleeping for 1 second\n");
1917 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
1918 if (status
& PCI_EXP_DEVSTA_TRPND
)
1919 dev_info(&dev
->dev
, "Still busy after 1s; "
1920 "proceeding with reset anyway\n");
1923 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
1924 PCI_EXP_DEVCTL_BCR_FLR
);
1927 pci_unblock_user_cfg_access(dev
);
1931 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
1933 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
1939 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
1940 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
1946 pci_block_user_cfg_access(dev
);
1948 /* Wait for Transaction Pending bit clean */
1950 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
1951 if (status
& PCI_AF_STATUS_TP
) {
1952 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
1953 " reset; sleeping for 1 second\n");
1955 pci_read_config_byte(dev
,
1956 cappos
+ PCI_AF_STATUS
, &status
);
1957 if (status
& PCI_AF_STATUS_TP
)
1958 dev_info(&dev
->dev
, "Still busy after 1s; "
1959 "proceeding with reset anyway\n");
1961 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
1964 pci_unblock_user_cfg_access(dev
);
1968 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
1972 res
= __pcie_flr(pdev
, probe
);
1976 res
= __pci_af_flr(pdev
, probe
);
1984 * pci_execute_reset_function() - Reset a PCI device function
1985 * @dev: Device function to reset
1987 * Some devices allow an individual function to be reset without affecting
1988 * other functions in the same device. The PCI device must be responsive
1989 * to PCI config space in order to use this function.
1991 * The device function is presumed to be unused when this function is called.
1992 * Resetting the device will make the contents of PCI configuration space
1993 * random, so any caller of this must be prepared to reinitialise the
1994 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
1997 * Returns 0 if the device function was successfully reset or -ENOTTY if the
1998 * device doesn't support resetting a single function.
2000 int pci_execute_reset_function(struct pci_dev
*dev
)
2002 return __pci_reset_function(dev
, 0);
2004 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
2007 * pci_reset_function() - quiesce and reset a PCI device function
2008 * @dev: Device function to reset
2010 * Some devices allow an individual function to be reset without affecting
2011 * other functions in the same device. The PCI device must be responsive
2012 * to PCI config space in order to use this function.
2014 * This function does not just reset the PCI portion of a device, but
2015 * clears all the state associated with the device. This function differs
2016 * from pci_execute_reset_function in that it saves and restores device state
2019 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2020 * device doesn't support resetting a single function.
2022 int pci_reset_function(struct pci_dev
*dev
)
2024 int r
= __pci_reset_function(dev
, 1);
2029 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2030 disable_irq(dev
->irq
);
2031 pci_save_state(dev
);
2033 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2035 r
= pci_execute_reset_function(dev
);
2037 pci_restore_state(dev
);
2038 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2039 enable_irq(dev
->irq
);
2043 EXPORT_SYMBOL_GPL(pci_reset_function
);
2046 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2047 * @dev: PCI device to query
2049 * Returns mmrbc: maximum designed memory read count in bytes
2050 * or appropriate error value.
2052 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2057 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2061 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2065 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2067 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2070 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2071 * @dev: PCI device to query
2073 * Returns mmrbc: maximum memory read count in bytes
2074 * or appropriate error value.
2076 int pcix_get_mmrbc(struct pci_dev
*dev
)
2081 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2085 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2087 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2091 EXPORT_SYMBOL(pcix_get_mmrbc
);
2094 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2095 * @dev: PCI device to query
2096 * @mmrbc: maximum memory read count in bytes
2097 * valid values are 512, 1024, 2048, 4096
2099 * If possible sets maximum memory read byte count, some bridges have erratas
2100 * that prevent this.
2102 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2104 int cap
, err
= -EINVAL
;
2105 u32 stat
, cmd
, v
, o
;
2107 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2110 v
= ffs(mmrbc
) - 10;
2112 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2116 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2120 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2123 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2127 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2129 if (v
> o
&& dev
->bus
&&
2130 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2133 cmd
&= ~PCI_X_CMD_MAX_READ
;
2135 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2140 EXPORT_SYMBOL(pcix_set_mmrbc
);
2143 * pcie_get_readrq - get PCI Express read request size
2144 * @dev: PCI device to query
2146 * Returns maximum memory read request in bytes
2147 * or appropriate error value.
2149 int pcie_get_readrq(struct pci_dev
*dev
)
2154 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2158 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2160 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2164 EXPORT_SYMBOL(pcie_get_readrq
);
2167 * pcie_set_readrq - set PCI Express maximum memory read request
2168 * @dev: PCI device to query
2169 * @rq: maximum memory read count in bytes
2170 * valid values are 128, 256, 512, 1024, 2048, 4096
2172 * If possible sets maximum read byte count
2174 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2176 int cap
, err
= -EINVAL
;
2179 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2182 v
= (ffs(rq
) - 8) << 12;
2184 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2188 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2192 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2193 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2195 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2201 EXPORT_SYMBOL(pcie_set_readrq
);
2204 * pci_select_bars - Make BAR mask from the type of resource
2205 * @dev: the PCI device for which BAR mask is made
2206 * @flags: resource type mask to be selected
2208 * This helper routine makes bar mask from the type of resource.
2210 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2213 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2214 if (pci_resource_flags(dev
, i
) & flags
)
2219 static void __devinit
pci_no_domains(void)
2221 #ifdef CONFIG_PCI_DOMAINS
2222 pci_domains_supported
= 0;
2227 * pci_ext_cfg_enabled - can we access extended PCI config space?
2228 * @dev: The PCI device of the root bridge.
2230 * Returns 1 if we can access PCI extended config space (offsets
2231 * greater than 0xff). This is the default implementation. Architecture
2232 * implementations can override this.
2234 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2239 static int __devinit
pci_init(void)
2241 struct pci_dev
*dev
= NULL
;
2243 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2244 pci_fixup_device(pci_fixup_final
, dev
);
2250 static int __init
pci_setup(char *str
)
2253 char *k
= strchr(str
, ',');
2256 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2257 if (!strcmp(str
, "nomsi")) {
2259 } else if (!strcmp(str
, "noaer")) {
2261 } else if (!strcmp(str
, "nodomains")) {
2263 } else if (!strncmp(str
, "cbiosize=", 9)) {
2264 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2265 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2266 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2268 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2276 early_param("pci", pci_setup
);
2278 device_initcall(pci_init
);
2280 EXPORT_SYMBOL(pci_reenable_device
);
2281 EXPORT_SYMBOL(pci_enable_device_io
);
2282 EXPORT_SYMBOL(pci_enable_device_mem
);
2283 EXPORT_SYMBOL(pci_enable_device
);
2284 EXPORT_SYMBOL(pcim_enable_device
);
2285 EXPORT_SYMBOL(pcim_pin_device
);
2286 EXPORT_SYMBOL(pci_disable_device
);
2287 EXPORT_SYMBOL(pci_find_capability
);
2288 EXPORT_SYMBOL(pci_bus_find_capability
);
2289 EXPORT_SYMBOL(pci_release_regions
);
2290 EXPORT_SYMBOL(pci_request_regions
);
2291 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2292 EXPORT_SYMBOL(pci_release_region
);
2293 EXPORT_SYMBOL(pci_request_region
);
2294 EXPORT_SYMBOL(pci_request_region_exclusive
);
2295 EXPORT_SYMBOL(pci_release_selected_regions
);
2296 EXPORT_SYMBOL(pci_request_selected_regions
);
2297 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2298 EXPORT_SYMBOL(pci_set_master
);
2299 EXPORT_SYMBOL(pci_set_mwi
);
2300 EXPORT_SYMBOL(pci_try_set_mwi
);
2301 EXPORT_SYMBOL(pci_clear_mwi
);
2302 EXPORT_SYMBOL_GPL(pci_intx
);
2303 EXPORT_SYMBOL(pci_set_dma_mask
);
2304 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2305 EXPORT_SYMBOL(pci_assign_resource
);
2306 EXPORT_SYMBOL(pci_find_parent_resource
);
2307 EXPORT_SYMBOL(pci_select_bars
);
2309 EXPORT_SYMBOL(pci_set_power_state
);
2310 EXPORT_SYMBOL(pci_save_state
);
2311 EXPORT_SYMBOL(pci_restore_state
);
2312 EXPORT_SYMBOL(pci_pme_capable
);
2313 EXPORT_SYMBOL(pci_pme_active
);
2314 EXPORT_SYMBOL(pci_enable_wake
);
2315 EXPORT_SYMBOL(pci_wake_from_d3
);
2316 EXPORT_SYMBOL(pci_target_state
);
2317 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2318 EXPORT_SYMBOL(pci_back_from_sleep
);
2319 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);