drivers/pci/pci.h

   1 #ifndef DRIVERS_PCI_H
   2 #define DRIVERS_PCI_H
   3
   4 #include <linux/workqueue.h>
   5
   6 #define PCI_CFG_SPACE_SIZE      256
   7 #define PCI_CFG_SPACE_EXP_SIZE  4096
   8
   9 /* Functions internal to the PCI core code */
  10
  11 extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
  12 extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  13 extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  14 #ifndef CONFIG_DMI
  15 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  16 { return; }
  17 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  18 { return; }
  19 #else
  20 extern void pci_create_firmware_label_files(struct pci_dev *pdev);
  21 extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
  22 #endif
  23 extern void pci_cleanup_rom(struct pci_dev *dev);
  24 #ifdef HAVE_PCI_MMAP
  25 enum pci_mmap_api {
  26         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  27         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  28 };
  29 extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
  30                          struct vm_area_struct *vmai,
  31                          enum pci_mmap_api mmap_api);
  32 #endif
  33 int pci_probe_reset_function(struct pci_dev *dev);
  34
  35 /**
  36  * struct pci_platform_pm_ops - Firmware PM callbacks
  37  *
  38  * @is_manageable: returns 'true' if given device is power manageable by the
  39  *                 platform firmware
  40  *
  41  * @set_state: invokes the platform firmware to set the device's power state
  42  *
  43  * @choose_state: returns PCI power state of given device preferred by the
  44  *                platform; to be used during system-wide transitions from a
  45  *                sleeping state to the working state and vice versa
  46  *
  47  * @can_wakeup: returns 'true' if given device is capable of waking up the
  48  *              system from a sleeping state
  49  *
  50  * @sleep_wake: enables/disables the system wake up capability of given device
  51  *
  52  * @run_wake: enables/disables the platform to generate run-time wake-up events
  53  *              for given device (the device's wake-up capability has to be
  54  *              enabled by @sleep_wake for this feature to work)
  55  *
  56  * If given platform is generally capable of power managing PCI devices, all of
  57  * these callbacks are mandatory.
  58  */
  59 struct pci_platform_pm_ops {
  60         bool (*is_manageable)(struct pci_dev *dev);
  61         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  62         pci_power_t (*choose_state)(struct pci_dev *dev);
  63         bool (*can_wakeup)(struct pci_dev *dev);
  64         int (*sleep_wake)(struct pci_dev *dev, bool enable);
  65         int (*run_wake)(struct pci_dev *dev, bool enable);
  66 };
  67
  68 extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
  69 extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  70 extern void pci_disable_enabled_device(struct pci_dev *dev);
  71 extern int pci_finish_runtime_suspend(struct pci_dev *dev);
  72 extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  73 extern void pci_pm_init(struct pci_dev *dev);
  74 extern void platform_pci_wakeup_init(struct pci_dev *dev);
  75 extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  76
  77 static inline bool pci_is_bridge(struct pci_dev *pci_dev)
  78 {
  79         return !!(pci_dev->subordinate);
  80 }
  81
  82 extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
  83 extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
  84 extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
  85 extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
  86 extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
  87 extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
  88
  89 struct pci_vpd_ops {
  90         ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  91         ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  92         void (*release)(struct pci_dev *dev);
  93 };
  94
  95 struct pci_vpd {
  96         unsigned int len;
  97         const struct pci_vpd_ops *ops;
  98         struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
  99 };
 100
 101 extern int pci_vpd_pci22_init(struct pci_dev *dev);
 102 static inline void pci_vpd_release(struct pci_dev *dev)
 103 {
 104         if (dev->vpd)
 105                 dev->vpd->ops->release(dev);
 106 }
 107
 108 /* PCI /proc functions */
 109 #ifdef CONFIG_PROC_FS
 110 extern int pci_proc_attach_device(struct pci_dev *dev);
 111 extern int pci_proc_detach_device(struct pci_dev *dev);
 112 extern int pci_proc_detach_bus(struct pci_bus *bus);
 113 #else
 114 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 115 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 116 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 117 #endif
 118
 119 /* Functions for PCI Hotplug drivers to use */
 120 extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
 121
 122 #ifdef HAVE_PCI_LEGACY
 123 extern void pci_create_legacy_files(struct pci_bus *bus);
 124 extern void pci_remove_legacy_files(struct pci_bus *bus);
 125 #else
 126 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 127 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 128 #endif
 129
 130 /* Lock for read/write access to pci device and bus lists */
 131 extern struct rw_semaphore pci_bus_sem;
 132
 133 extern unsigned int pci_pm_d3_delay;
 134
 135 #ifdef CONFIG_PCI_MSI
 136 void pci_no_msi(void);
 137 extern void pci_msi_init_pci_dev(struct pci_dev *dev);
 138 #else
 139 static inline void pci_no_msi(void) { }
 140 static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
 141 #endif
 142
 143 static inline int pci_no_d1d2(struct pci_dev *dev)
 144 {
 145         unsigned int parent_dstates = 0;
 146
 147         if (dev->bus->self)
 148                 parent_dstates = dev->bus->self->no_d1d2;
 149         return (dev->no_d1d2 || parent_dstates);
 150
 151 }
 152 extern struct device_attribute pci_dev_attrs[];
 153 extern struct device_attribute dev_attr_cpuaffinity;
 154 extern struct device_attribute dev_attr_cpulistaffinity;
 155 #ifdef CONFIG_HOTPLUG
 156 extern struct bus_attribute pci_bus_attrs[];
 157 #else
 158 #define pci_bus_attrs   NULL
 159 #endif
 160
 161
 162 /**
 163  * pci_match_one_device - Tell if a PCI device structure has a matching
 164  *                        PCI device id structure
 165  * @id: single PCI device id structure to match
 166  * @dev: the PCI device structure to match against
 167  *
 168  * Returns the matching pci_device_id structure or %NULL if there is no match.
 169  */
 170 static inline const struct pci_device_id *
 171 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 172 {
 173         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 174             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 175             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 176             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 177             !((id->class ^ dev->class) & id->class_mask))
 178                 return id;
 179         return NULL;
 180 }
 181
 182 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
 183
 184 /* PCI slot sysfs helper code */
 185 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 186
 187 extern struct kset *pci_slots_kset;
 188
 189 struct pci_slot_attribute {
 190         struct attribute attr;
 191         ssize_t (*show)(struct pci_slot *, char *);
 192         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 193 };
 194 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 195
 196 enum pci_bar_type {
 197         pci_bar_unknown,        /* Standard PCI BAR probe */
 198         pci_bar_io,             /* An io port BAR */
 199         pci_bar_mem32,          /* A 32-bit memory BAR */
 200         pci_bar_mem64,          /* A 64-bit memory BAR */
 201 };
 202
 203 extern int pci_setup_device(struct pci_dev *dev);
 204 extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 205                                 struct resource *res, unsigned int reg);
 206 extern int pci_resource_bar(struct pci_dev *dev, int resno,
 207                             enum pci_bar_type *type);
 208 extern int pci_bus_add_child(struct pci_bus *bus);
 209 extern void pci_enable_ari(struct pci_dev *dev);
 210 /**
 211  * pci_ari_enabled - query ARI forwarding status
 212  * @bus: the PCI bus
 213  *
 214  * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 215  */
 216 static inline int pci_ari_enabled(struct pci_bus *bus)
 217 {
 218         return bus->self && bus->self->ari_enabled;
 219 }
 220
 221 #ifdef CONFIG_PCI_QUIRKS
 222 extern int pci_is_reassigndev(struct pci_dev *dev);
 223 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
 224 extern void pci_disable_bridge_window(struct pci_dev *dev);
 225 #endif
 226
 227 /* Single Root I/O Virtualization */
 228 struct pci_sriov {
 229         int pos;                /* capability position */
 230         int nres;               /* number of resources */
 231         u32 cap;                /* SR-IOV Capabilities */
 232         u16 ctrl;               /* SR-IOV Control */
 233         u16 total;              /* total VFs associated with the PF */
 234         u16 initial;            /* initial VFs associated with the PF */
 235         u16 nr_virtfn;          /* number of VFs available */
 236         u16 offset;             /* first VF Routing ID offset */
 237         u16 stride;             /* following VF stride */
 238         u32 pgsz;               /* page size for BAR alignment */
 239         u8 link;                /* Function Dependency Link */
 240         struct pci_dev *dev;    /* lowest numbered PF */
 241         struct pci_dev *self;   /* this PF */
 242         struct mutex lock;      /* lock for VF bus */
 243         struct work_struct mtask; /* VF Migration task */
 244         u8 __iomem *mstate;     /* VF Migration State Array */
 245 };
 246
 247 /* Address Translation Service */
 248 struct pci_ats {
 249         int pos;        /* capability position */
 250         int stu;        /* Smallest Translation Unit */
 251         int qdep;       /* Invalidate Queue Depth */
 252         int ref_cnt;    /* Physical Function reference count */
 253         unsigned int is_enabled:1;      /* Enable bit is set */
 254 };
 255
 256 #ifdef CONFIG_PCI_IOV
 257 extern int pci_iov_init(struct pci_dev *dev);
 258 extern void pci_iov_release(struct pci_dev *dev);
 259 extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
 260                                 enum pci_bar_type *type);
 261 extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
 262                                                     int resno);
 263 extern void pci_restore_iov_state(struct pci_dev *dev);
 264 extern int pci_iov_bus_range(struct pci_bus *bus);
 265
 266 extern int pci_enable_ats(struct pci_dev *dev, int ps);
 267 extern void pci_disable_ats(struct pci_dev *dev);
 268 extern int pci_ats_queue_depth(struct pci_dev *dev);
 269 /**
 270  * pci_ats_enabled - query the ATS status
 271  * @dev: the PCI device
 272  *
 273  * Returns 1 if ATS capability is enabled, or 0 if not.
 274  */
 275 static inline int pci_ats_enabled(struct pci_dev *dev)
 276 {
 277         return dev->ats && dev->ats->is_enabled;
 278 }
 279 #else
 280 static inline int pci_iov_init(struct pci_dev *dev)
 281 {
 282         return -ENODEV;
 283 }
 284 static inline void pci_iov_release(struct pci_dev *dev)
 285
 286 {
 287 }
 288 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
 289                                        enum pci_bar_type *type)
 290 {
 291         return 0;
 292 }
 293 static inline void pci_restore_iov_state(struct pci_dev *dev)
 294 {
 295 }
 296 static inline int pci_iov_bus_range(struct pci_bus *bus)
 297 {
 298         return 0;
 299 }
 300
 301 static inline int pci_enable_ats(struct pci_dev *dev, int ps)
 302 {
 303         return -ENODEV;
 304 }
 305 static inline void pci_disable_ats(struct pci_dev *dev)
 306 {
 307 }
 308 static inline int pci_ats_queue_depth(struct pci_dev *dev)
 309 {
 310         return -ENODEV;
 311 }
 312 static inline int pci_ats_enabled(struct pci_dev *dev)
 313 {
 314         return 0;
 315 }
 316 #endif /* CONFIG_PCI_IOV */
 317
 318 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 319                                          struct resource *res)
 320 {
 321 #ifdef CONFIG_PCI_IOV
 322         int resno = res - dev->resource;
 323
 324         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 325                 return pci_sriov_resource_alignment(dev, resno);
 326 #endif
 327         return resource_alignment(res);
 328 }
 329
 330 extern void pci_enable_acs(struct pci_dev *dev);
 331
 332 struct pci_dev_reset_methods {
 333         u16 vendor;
 334         u16 device;
 335         int (*reset)(struct pci_dev *dev, int probe);
 336 };
 337
 338 #ifdef CONFIG_PCI_QUIRKS
 339 extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 340 #else
 341 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 342 {
 343         return -ENOTTY;
 344 }
 345 #endif
 346
 347 #endif /* DRIVERS_PCI_H */