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sysfs: kill unnecessary attribute->owner
[deliverable/linux.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 #ifdef HAVE_PCI_LEGACY
26 /**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34 static void pci_create_legacy_files(struct pci_bus *b)
35 {
36 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 b->legacy_io->attr.name = "legacy_io";
40 b->legacy_io->size = 0xffff;
41 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
42 b->legacy_io->read = pci_read_legacy_io;
43 b->legacy_io->write = pci_write_legacy_io;
44 class_device_create_bin_file(&b->class_dev, b->legacy_io);
45
46 /* Allocated above after the legacy_io struct */
47 b->legacy_mem = b->legacy_io + 1;
48 b->legacy_mem->attr.name = "legacy_mem";
49 b->legacy_mem->size = 1024*1024;
50 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
51 b->legacy_mem->mmap = pci_mmap_legacy_mem;
52 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
53 }
54 }
55
56 void pci_remove_legacy_files(struct pci_bus *b)
57 {
58 if (b->legacy_io) {
59 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
60 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
61 kfree(b->legacy_io); /* both are allocated here */
62 }
63 }
64 #else /* !HAVE_PCI_LEGACY */
65 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
66 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
67 #endif /* HAVE_PCI_LEGACY */
68
69 /*
70 * PCI Bus Class Devices
71 */
72 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
73 char *buf)
74 {
75 int ret;
76 cpumask_t cpumask;
77
78 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
79 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
80 if (ret < PAGE_SIZE)
81 buf[ret++] = '\n';
82 return ret;
83 }
84 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
85
86 /*
87 * PCI Bus Class
88 */
89 static void release_pcibus_dev(struct class_device *class_dev)
90 {
91 struct pci_bus *pci_bus = to_pci_bus(class_dev);
92
93 if (pci_bus->bridge)
94 put_device(pci_bus->bridge);
95 kfree(pci_bus);
96 }
97
98 static struct class pcibus_class = {
99 .name = "pci_bus",
100 .release = &release_pcibus_dev,
101 };
102
103 static int __init pcibus_class_init(void)
104 {
105 return class_register(&pcibus_class);
106 }
107 postcore_initcall(pcibus_class_init);
108
109 /*
110 * Translate the low bits of the PCI base
111 * to the resource type
112 */
113 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
114 {
115 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
116 return IORESOURCE_IO;
117
118 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
119 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
120
121 return IORESOURCE_MEM;
122 }
123
124 /*
125 * Find the extent of a PCI decode..
126 */
127 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
128 {
129 u32 size = mask & maxbase; /* Find the significant bits */
130 if (!size)
131 return 0;
132
133 /* Get the lowest of them to find the decode size, and
134 from that the extent. */
135 size = (size & ~(size-1)) - 1;
136
137 /* base == maxbase can be valid only if the BAR has
138 already been programmed with all 1s. */
139 if (base == maxbase && ((base | size) & mask) != mask)
140 return 0;
141
142 return size;
143 }
144
145 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
146 {
147 u64 size = mask & maxbase; /* Find the significant bits */
148 if (!size)
149 return 0;
150
151 /* Get the lowest of them to find the decode size, and
152 from that the extent. */
153 size = (size & ~(size-1)) - 1;
154
155 /* base == maxbase can be valid only if the BAR has
156 already been programmed with all 1s. */
157 if (base == maxbase && ((base | size) & mask) != mask)
158 return 0;
159
160 return size;
161 }
162
163 static inline int is_64bit_memory(u32 mask)
164 {
165 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
166 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
167 return 1;
168 return 0;
169 }
170
171 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
172 {
173 unsigned int pos, reg, next;
174 u32 l, sz;
175 struct resource *res;
176
177 for(pos=0; pos<howmany; pos = next) {
178 u64 l64;
179 u64 sz64;
180 u32 raw_sz;
181
182 next = pos+1;
183 res = &dev->resource[pos];
184 res->name = pci_name(dev);
185 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
186 pci_read_config_dword(dev, reg, &l);
187 pci_write_config_dword(dev, reg, ~0);
188 pci_read_config_dword(dev, reg, &sz);
189 pci_write_config_dword(dev, reg, l);
190 if (!sz || sz == 0xffffffff)
191 continue;
192 if (l == 0xffffffff)
193 l = 0;
194 raw_sz = sz;
195 if ((l & PCI_BASE_ADDRESS_SPACE) ==
196 PCI_BASE_ADDRESS_SPACE_MEMORY) {
197 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
198 /*
199 * For 64bit prefetchable memory sz could be 0, if the
200 * real size is bigger than 4G, so we need to check
201 * szhi for that.
202 */
203 if (!is_64bit_memory(l) && !sz)
204 continue;
205 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
206 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
207 } else {
208 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
209 if (!sz)
210 continue;
211 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
212 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
213 }
214 res->end = res->start + (unsigned long) sz;
215 res->flags |= pci_calc_resource_flags(l);
216 if (is_64bit_memory(l)) {
217 u32 szhi, lhi;
218
219 pci_read_config_dword(dev, reg+4, &lhi);
220 pci_write_config_dword(dev, reg+4, ~0);
221 pci_read_config_dword(dev, reg+4, &szhi);
222 pci_write_config_dword(dev, reg+4, lhi);
223 sz64 = ((u64)szhi << 32) | raw_sz;
224 l64 = ((u64)lhi << 32) | l;
225 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
226 next++;
227 #if BITS_PER_LONG == 64
228 if (!sz64) {
229 res->start = 0;
230 res->end = 0;
231 res->flags = 0;
232 continue;
233 }
234 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
235 res->end = res->start + sz64;
236 #else
237 if (sz64 > 0x100000000ULL) {
238 printk(KERN_ERR "PCI: Unable to handle 64-bit "
239 "BAR for device %s\n", pci_name(dev));
240 res->start = 0;
241 res->flags = 0;
242 } else if (lhi) {
243 /* 64-bit wide address, treat as disabled */
244 pci_write_config_dword(dev, reg,
245 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
246 pci_write_config_dword(dev, reg+4, 0);
247 res->start = 0;
248 res->end = sz;
249 }
250 #endif
251 }
252 }
253 if (rom) {
254 dev->rom_base_reg = rom;
255 res = &dev->resource[PCI_ROM_RESOURCE];
256 res->name = pci_name(dev);
257 pci_read_config_dword(dev, rom, &l);
258 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
259 pci_read_config_dword(dev, rom, &sz);
260 pci_write_config_dword(dev, rom, l);
261 if (l == 0xffffffff)
262 l = 0;
263 if (sz && sz != 0xffffffff) {
264 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
265 if (sz) {
266 res->flags = (l & IORESOURCE_ROM_ENABLE) |
267 IORESOURCE_MEM | IORESOURCE_PREFETCH |
268 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
269 res->start = l & PCI_ROM_ADDRESS_MASK;
270 res->end = res->start + (unsigned long) sz;
271 }
272 }
273 }
274 }
275
276 void __devinit pci_read_bridge_bases(struct pci_bus *child)
277 {
278 struct pci_dev *dev = child->self;
279 u8 io_base_lo, io_limit_lo;
280 u16 mem_base_lo, mem_limit_lo;
281 unsigned long base, limit;
282 struct resource *res;
283 int i;
284
285 if (!dev) /* It's a host bus, nothing to read */
286 return;
287
288 if (dev->transparent) {
289 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
290 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
291 child->resource[i] = child->parent->resource[i - 3];
292 }
293
294 for(i=0; i<3; i++)
295 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
296
297 res = child->resource[0];
298 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
299 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
300 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
301 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
302
303 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
304 u16 io_base_hi, io_limit_hi;
305 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
306 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
307 base |= (io_base_hi << 16);
308 limit |= (io_limit_hi << 16);
309 }
310
311 if (base <= limit) {
312 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
313 if (!res->start)
314 res->start = base;
315 if (!res->end)
316 res->end = limit + 0xfff;
317 }
318
319 res = child->resource[1];
320 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
321 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
322 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
323 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
324 if (base <= limit) {
325 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
326 res->start = base;
327 res->end = limit + 0xfffff;
328 }
329
330 res = child->resource[2];
331 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
332 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
333 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
334 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
335
336 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
337 u32 mem_base_hi, mem_limit_hi;
338 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
339 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
340
341 /*
342 * Some bridges set the base > limit by default, and some
343 * (broken) BIOSes do not initialize them. If we find
344 * this, just assume they are not being used.
345 */
346 if (mem_base_hi <= mem_limit_hi) {
347 #if BITS_PER_LONG == 64
348 base |= ((long) mem_base_hi) << 32;
349 limit |= ((long) mem_limit_hi) << 32;
350 #else
351 if (mem_base_hi || mem_limit_hi) {
352 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
353 return;
354 }
355 #endif
356 }
357 }
358 if (base <= limit) {
359 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
360 res->start = base;
361 res->end = limit + 0xfffff;
362 }
363 }
364
365 static struct pci_bus * pci_alloc_bus(void)
366 {
367 struct pci_bus *b;
368
369 b = kzalloc(sizeof(*b), GFP_KERNEL);
370 if (b) {
371 INIT_LIST_HEAD(&b->node);
372 INIT_LIST_HEAD(&b->children);
373 INIT_LIST_HEAD(&b->devices);
374 }
375 return b;
376 }
377
378 static struct pci_bus * __devinit
379 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
380 {
381 struct pci_bus *child;
382 int i;
383 int retval;
384
385 /*
386 * Allocate a new bus, and inherit stuff from the parent..
387 */
388 child = pci_alloc_bus();
389 if (!child)
390 return NULL;
391
392 child->self = bridge;
393 child->parent = parent;
394 child->ops = parent->ops;
395 child->sysdata = parent->sysdata;
396 child->bus_flags = parent->bus_flags;
397 child->bridge = get_device(&bridge->dev);
398
399 child->class_dev.class = &pcibus_class;
400 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
401 retval = class_device_register(&child->class_dev);
402 if (retval)
403 goto error_register;
404 retval = class_device_create_file(&child->class_dev,
405 &class_device_attr_cpuaffinity);
406 if (retval)
407 goto error_file_create;
408
409 /*
410 * Set up the primary, secondary and subordinate
411 * bus numbers.
412 */
413 child->number = child->secondary = busnr;
414 child->primary = parent->secondary;
415 child->subordinate = 0xff;
416
417 /* Set up default resource pointers and names.. */
418 for (i = 0; i < 4; i++) {
419 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
420 child->resource[i]->name = child->name;
421 }
422 bridge->subordinate = child;
423
424 return child;
425
426 error_file_create:
427 class_device_unregister(&child->class_dev);
428 error_register:
429 kfree(child);
430 return NULL;
431 }
432
433 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
434 {
435 struct pci_bus *child;
436
437 child = pci_alloc_child_bus(parent, dev, busnr);
438 if (child) {
439 down_write(&pci_bus_sem);
440 list_add_tail(&child->node, &parent->children);
441 up_write(&pci_bus_sem);
442 }
443 return child;
444 }
445
446 static void pci_enable_crs(struct pci_dev *dev)
447 {
448 u16 cap, rpctl;
449 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
450 if (!rpcap)
451 return;
452
453 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
454 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
455 return;
456
457 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
458 rpctl |= PCI_EXP_RTCTL_CRSSVE;
459 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
460 }
461
462 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
463 {
464 struct pci_bus *parent = child->parent;
465
466 /* Attempts to fix that up are really dangerous unless
467 we're going to re-assign all bus numbers. */
468 if (!pcibios_assign_all_busses())
469 return;
470
471 while (parent->parent && parent->subordinate < max) {
472 parent->subordinate = max;
473 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
474 parent = parent->parent;
475 }
476 }
477
478 unsigned int pci_scan_child_bus(struct pci_bus *bus);
479
480 /*
481 * If it's a bridge, configure it and scan the bus behind it.
482 * For CardBus bridges, we don't scan behind as the devices will
483 * be handled by the bridge driver itself.
484 *
485 * We need to process bridges in two passes -- first we scan those
486 * already configured by the BIOS and after we are done with all of
487 * them, we proceed to assigning numbers to the remaining buses in
488 * order to avoid overlaps between old and new bus numbers.
489 */
490 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
491 {
492 struct pci_bus *child;
493 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
494 u32 buses, i, j = 0;
495 u16 bctl;
496
497 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
498
499 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
500 pci_name(dev), buses & 0xffffff, pass);
501
502 /* Disable MasterAbortMode during probing to avoid reporting
503 of bus errors (in some architectures) */
504 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
505 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
506 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
507
508 pci_enable_crs(dev);
509
510 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
511 unsigned int cmax, busnr;
512 /*
513 * Bus already configured by firmware, process it in the first
514 * pass and just note the configuration.
515 */
516 if (pass)
517 goto out;
518 busnr = (buses >> 8) & 0xFF;
519
520 /*
521 * If we already got to this bus through a different bridge,
522 * ignore it. This can happen with the i450NX chipset.
523 */
524 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
525 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
526 pci_domain_nr(bus), busnr);
527 goto out;
528 }
529
530 child = pci_add_new_bus(bus, dev, busnr);
531 if (!child)
532 goto out;
533 child->primary = buses & 0xFF;
534 child->subordinate = (buses >> 16) & 0xFF;
535 child->bridge_ctl = bctl;
536
537 cmax = pci_scan_child_bus(child);
538 if (cmax > max)
539 max = cmax;
540 if (child->subordinate > max)
541 max = child->subordinate;
542 } else {
543 /*
544 * We need to assign a number to this bus which we always
545 * do in the second pass.
546 */
547 if (!pass) {
548 if (pcibios_assign_all_busses())
549 /* Temporarily disable forwarding of the
550 configuration cycles on all bridges in
551 this bus segment to avoid possible
552 conflicts in the second pass between two
553 bridges programmed with overlapping
554 bus ranges. */
555 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
556 buses & ~0xffffff);
557 goto out;
558 }
559
560 /* Clear errors */
561 pci_write_config_word(dev, PCI_STATUS, 0xffff);
562
563 /* Prevent assigning a bus number that already exists.
564 * This can happen when a bridge is hot-plugged */
565 if (pci_find_bus(pci_domain_nr(bus), max+1))
566 goto out;
567 child = pci_add_new_bus(bus, dev, ++max);
568 buses = (buses & 0xff000000)
569 | ((unsigned int)(child->primary) << 0)
570 | ((unsigned int)(child->secondary) << 8)
571 | ((unsigned int)(child->subordinate) << 16);
572
573 /*
574 * yenta.c forces a secondary latency timer of 176.
575 * Copy that behaviour here.
576 */
577 if (is_cardbus) {
578 buses &= ~0xff000000;
579 buses |= CARDBUS_LATENCY_TIMER << 24;
580 }
581
582 /*
583 * We need to blast all three values with a single write.
584 */
585 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
586
587 if (!is_cardbus) {
588 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
589 /*
590 * Adjust subordinate busnr in parent buses.
591 * We do this before scanning for children because
592 * some devices may not be detected if the bios
593 * was lazy.
594 */
595 pci_fixup_parent_subordinate_busnr(child, max);
596 /* Now we can scan all subordinate buses... */
597 max = pci_scan_child_bus(child);
598 /*
599 * now fix it up again since we have found
600 * the real value of max.
601 */
602 pci_fixup_parent_subordinate_busnr(child, max);
603 } else {
604 /*
605 * For CardBus bridges, we leave 4 bus numbers
606 * as cards with a PCI-to-PCI bridge can be
607 * inserted later.
608 */
609 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
610 struct pci_bus *parent = bus;
611 if (pci_find_bus(pci_domain_nr(bus),
612 max+i+1))
613 break;
614 while (parent->parent) {
615 if ((!pcibios_assign_all_busses()) &&
616 (parent->subordinate > max) &&
617 (parent->subordinate <= max+i)) {
618 j = 1;
619 }
620 parent = parent->parent;
621 }
622 if (j) {
623 /*
624 * Often, there are two cardbus bridges
625 * -- try to leave one valid bus number
626 * for each one.
627 */
628 i /= 2;
629 break;
630 }
631 }
632 max += i;
633 pci_fixup_parent_subordinate_busnr(child, max);
634 }
635 /*
636 * Set the subordinate bus number to its real value.
637 */
638 child->subordinate = max;
639 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
640 }
641
642 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
643
644 while (bus->parent) {
645 if ((child->subordinate > bus->subordinate) ||
646 (child->number > bus->subordinate) ||
647 (child->number < bus->number) ||
648 (child->subordinate < bus->number)) {
649 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) is "
650 "hidden behind%s bridge #%02x (-#%02x)%s\n",
651 child->number, child->subordinate,
652 bus->self->transparent ? " transparent" : " ",
653 bus->number, bus->subordinate,
654 pcibios_assign_all_busses() ? " " :
655 " (try 'pci=assign-busses')");
656 printk(KERN_WARNING "Please report the result to "
657 "linux-kernel to fix this permanently\n");
658 }
659 bus = bus->parent;
660 }
661
662 out:
663 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
664
665 return max;
666 }
667
668 /*
669 * Read interrupt line and base address registers.
670 * The architecture-dependent code can tweak these, of course.
671 */
672 static void pci_read_irq(struct pci_dev *dev)
673 {
674 unsigned char irq;
675
676 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
677 dev->pin = irq;
678 if (irq)
679 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
680 dev->irq = irq;
681 }
682
683 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
684
685 /**
686 * pci_setup_device - fill in class and map information of a device
687 * @dev: the device structure to fill
688 *
689 * Initialize the device structure with information about the device's
690 * vendor,class,memory and IO-space addresses,IRQ lines etc.
691 * Called at initialisation of the PCI subsystem and by CardBus services.
692 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
693 * or CardBus).
694 */
695 static int pci_setup_device(struct pci_dev * dev)
696 {
697 u32 class;
698
699 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
700 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
701
702 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
703 class >>= 8; /* upper 3 bytes */
704 dev->class = class;
705 class >>= 8;
706
707 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
708 dev->vendor, dev->device, class, dev->hdr_type);
709
710 /* "Unknown power state" */
711 dev->current_state = PCI_UNKNOWN;
712
713 /* Early fixups, before probing the BARs */
714 pci_fixup_device(pci_fixup_early, dev);
715 class = dev->class >> 8;
716
717 switch (dev->hdr_type) { /* header type */
718 case PCI_HEADER_TYPE_NORMAL: /* standard header */
719 if (class == PCI_CLASS_BRIDGE_PCI)
720 goto bad;
721 pci_read_irq(dev);
722 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
723 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
724 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
725
726 /*
727 * Do the ugly legacy mode stuff here rather than broken chip
728 * quirk code. Legacy mode ATA controllers have fixed
729 * addresses. These are not always echoed in BAR0-3, and
730 * BAR0-3 in a few cases contain junk!
731 */
732 if (class == PCI_CLASS_STORAGE_IDE) {
733 u8 progif;
734 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
735 if ((progif & 1) == 0) {
736 dev->resource[0].start = 0x1F0;
737 dev->resource[0].end = 0x1F7;
738 dev->resource[0].flags = LEGACY_IO_RESOURCE;
739 dev->resource[1].start = 0x3F6;
740 dev->resource[1].end = 0x3F6;
741 dev->resource[1].flags = LEGACY_IO_RESOURCE;
742 }
743 if ((progif & 4) == 0) {
744 dev->resource[2].start = 0x170;
745 dev->resource[2].end = 0x177;
746 dev->resource[2].flags = LEGACY_IO_RESOURCE;
747 dev->resource[3].start = 0x376;
748 dev->resource[3].end = 0x376;
749 dev->resource[3].flags = LEGACY_IO_RESOURCE;
750 }
751 }
752 break;
753
754 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
755 if (class != PCI_CLASS_BRIDGE_PCI)
756 goto bad;
757 /* The PCI-to-PCI bridge spec requires that subtractive
758 decoding (i.e. transparent) bridge must have programming
759 interface code of 0x01. */
760 pci_read_irq(dev);
761 dev->transparent = ((dev->class & 0xff) == 1);
762 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
763 break;
764
765 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
766 if (class != PCI_CLASS_BRIDGE_CARDBUS)
767 goto bad;
768 pci_read_irq(dev);
769 pci_read_bases(dev, 1, 0);
770 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
771 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
772 break;
773
774 default: /* unknown header */
775 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
776 pci_name(dev), dev->hdr_type);
777 return -1;
778
779 bad:
780 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
781 pci_name(dev), class, dev->hdr_type);
782 dev->class = PCI_CLASS_NOT_DEFINED;
783 }
784
785 /* We found a fine healthy device, go go go... */
786 return 0;
787 }
788
789 /**
790 * pci_release_dev - free a pci device structure when all users of it are finished.
791 * @dev: device that's been disconnected
792 *
793 * Will be called only by the device core when all users of this pci device are
794 * done.
795 */
796 static void pci_release_dev(struct device *dev)
797 {
798 struct pci_dev *pci_dev;
799
800 pci_dev = to_pci_dev(dev);
801 kfree(pci_dev);
802 }
803
804 /**
805 * pci_cfg_space_size - get the configuration space size of the PCI device.
806 * @dev: PCI device
807 *
808 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
809 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
810 * access it. Maybe we don't have a way to generate extended config space
811 * accesses, or the device is behind a reverse Express bridge. So we try
812 * reading the dword at 0x100 which must either be 0 or a valid extended
813 * capability header.
814 */
815 int pci_cfg_space_size(struct pci_dev *dev)
816 {
817 int pos;
818 u32 status;
819
820 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
821 if (!pos) {
822 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
823 if (!pos)
824 goto fail;
825
826 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
827 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
828 goto fail;
829 }
830
831 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
832 goto fail;
833 if (status == 0xffffffff)
834 goto fail;
835
836 return PCI_CFG_SPACE_EXP_SIZE;
837
838 fail:
839 return PCI_CFG_SPACE_SIZE;
840 }
841
842 static void pci_release_bus_bridge_dev(struct device *dev)
843 {
844 kfree(dev);
845 }
846
847 struct pci_dev *alloc_pci_dev(void)
848 {
849 struct pci_dev *dev;
850
851 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
852 if (!dev)
853 return NULL;
854
855 INIT_LIST_HEAD(&dev->global_list);
856 INIT_LIST_HEAD(&dev->bus_list);
857
858 pci_msi_init_pci_dev(dev);
859
860 return dev;
861 }
862 EXPORT_SYMBOL(alloc_pci_dev);
863
864 /*
865 * Read the config data for a PCI device, sanity-check it
866 * and fill in the dev structure...
867 */
868 static struct pci_dev * __devinit
869 pci_scan_device(struct pci_bus *bus, int devfn)
870 {
871 struct pci_dev *dev;
872 u32 l;
873 u8 hdr_type;
874 int delay = 1;
875
876 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
877 return NULL;
878
879 /* some broken boards return 0 or ~0 if a slot is empty: */
880 if (l == 0xffffffff || l == 0x00000000 ||
881 l == 0x0000ffff || l == 0xffff0000)
882 return NULL;
883
884 /* Configuration request Retry Status */
885 while (l == 0xffff0001) {
886 msleep(delay);
887 delay *= 2;
888 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
889 return NULL;
890 /* Card hasn't responded in 60 seconds? Must be stuck. */
891 if (delay > 60 * 1000) {
892 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
893 "responding\n", pci_domain_nr(bus),
894 bus->number, PCI_SLOT(devfn),
895 PCI_FUNC(devfn));
896 return NULL;
897 }
898 }
899
900 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
901 return NULL;
902
903 dev = alloc_pci_dev();
904 if (!dev)
905 return NULL;
906
907 dev->bus = bus;
908 dev->sysdata = bus->sysdata;
909 dev->dev.parent = bus->bridge;
910 dev->dev.bus = &pci_bus_type;
911 dev->devfn = devfn;
912 dev->hdr_type = hdr_type & 0x7f;
913 dev->multifunction = !!(hdr_type & 0x80);
914 dev->vendor = l & 0xffff;
915 dev->device = (l >> 16) & 0xffff;
916 dev->cfg_size = pci_cfg_space_size(dev);
917 dev->error_state = pci_channel_io_normal;
918
919 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
920 set this higher, assuming the system even supports it. */
921 dev->dma_mask = 0xffffffff;
922 if (pci_setup_device(dev) < 0) {
923 kfree(dev);
924 return NULL;
925 }
926
927 return dev;
928 }
929
930 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
931 {
932 device_initialize(&dev->dev);
933 dev->dev.release = pci_release_dev;
934 pci_dev_get(dev);
935
936 set_dev_node(&dev->dev, pcibus_to_node(bus));
937 dev->dev.dma_mask = &dev->dma_mask;
938 dev->dev.coherent_dma_mask = 0xffffffffull;
939
940 /* Fix up broken headers */
941 pci_fixup_device(pci_fixup_header, dev);
942
943 /*
944 * Add the device to our list of discovered devices
945 * and the bus list for fixup functions, etc.
946 */
947 INIT_LIST_HEAD(&dev->global_list);
948 down_write(&pci_bus_sem);
949 list_add_tail(&dev->bus_list, &bus->devices);
950 up_write(&pci_bus_sem);
951 }
952
953 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
954 {
955 struct pci_dev *dev;
956
957 dev = pci_scan_device(bus, devfn);
958 if (!dev)
959 return NULL;
960
961 pci_device_add(dev, bus);
962
963 return dev;
964 }
965
966 /**
967 * pci_scan_slot - scan a PCI slot on a bus for devices.
968 * @bus: PCI bus to scan
969 * @devfn: slot number to scan (must have zero function.)
970 *
971 * Scan a PCI slot on the specified PCI bus for devices, adding
972 * discovered devices to the @bus->devices list. New devices
973 * will have an empty dev->global_list head.
974 */
975 int pci_scan_slot(struct pci_bus *bus, int devfn)
976 {
977 int func, nr = 0;
978 int scan_all_fns;
979
980 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
981
982 for (func = 0; func < 8; func++, devfn++) {
983 struct pci_dev *dev;
984
985 dev = pci_scan_single_device(bus, devfn);
986 if (dev) {
987 nr++;
988
989 /*
990 * If this is a single function device,
991 * don't scan past the first function.
992 */
993 if (!dev->multifunction) {
994 if (func > 0) {
995 dev->multifunction = 1;
996 } else {
997 break;
998 }
999 }
1000 } else {
1001 if (func == 0 && !scan_all_fns)
1002 break;
1003 }
1004 }
1005 return nr;
1006 }
1007
1008 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1009 {
1010 unsigned int devfn, pass, max = bus->secondary;
1011 struct pci_dev *dev;
1012
1013 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1014
1015 /* Go find them, Rover! */
1016 for (devfn = 0; devfn < 0x100; devfn += 8)
1017 pci_scan_slot(bus, devfn);
1018
1019 /*
1020 * After performing arch-dependent fixup of the bus, look behind
1021 * all PCI-to-PCI bridges on this bus.
1022 */
1023 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1024 pcibios_fixup_bus(bus);
1025 for (pass=0; pass < 2; pass++)
1026 list_for_each_entry(dev, &bus->devices, bus_list) {
1027 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1028 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1029 max = pci_scan_bridge(bus, dev, max, pass);
1030 }
1031
1032 /*
1033 * We've scanned the bus and so we know all about what's on
1034 * the other side of any bridges that may be on this bus plus
1035 * any devices.
1036 *
1037 * Return how far we've got finding sub-buses.
1038 */
1039 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1040 pci_domain_nr(bus), bus->number, max);
1041 return max;
1042 }
1043
1044 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
1045 {
1046 unsigned int max;
1047
1048 max = pci_scan_child_bus(bus);
1049
1050 /*
1051 * Make the discovered devices available.
1052 */
1053 pci_bus_add_devices(bus);
1054
1055 return max;
1056 }
1057
1058 struct pci_bus * pci_create_bus(struct device *parent,
1059 int bus, struct pci_ops *ops, void *sysdata)
1060 {
1061 int error;
1062 struct pci_bus *b;
1063 struct device *dev;
1064
1065 b = pci_alloc_bus();
1066 if (!b)
1067 return NULL;
1068
1069 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1070 if (!dev){
1071 kfree(b);
1072 return NULL;
1073 }
1074
1075 b->sysdata = sysdata;
1076 b->ops = ops;
1077
1078 if (pci_find_bus(pci_domain_nr(b), bus)) {
1079 /* If we already got to this bus through a different bridge, ignore it */
1080 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1081 goto err_out;
1082 }
1083
1084 down_write(&pci_bus_sem);
1085 list_add_tail(&b->node, &pci_root_buses);
1086 up_write(&pci_bus_sem);
1087
1088 memset(dev, 0, sizeof(*dev));
1089 dev->parent = parent;
1090 dev->release = pci_release_bus_bridge_dev;
1091 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1092 error = device_register(dev);
1093 if (error)
1094 goto dev_reg_err;
1095 b->bridge = get_device(dev);
1096
1097 b->class_dev.class = &pcibus_class;
1098 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1099 error = class_device_register(&b->class_dev);
1100 if (error)
1101 goto class_dev_reg_err;
1102 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1103 if (error)
1104 goto class_dev_create_file_err;
1105
1106 /* Create legacy_io and legacy_mem files for this bus */
1107 pci_create_legacy_files(b);
1108
1109 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1110 if (error)
1111 goto sys_create_link_err;
1112
1113 b->number = b->secondary = bus;
1114 b->resource[0] = &ioport_resource;
1115 b->resource[1] = &iomem_resource;
1116
1117 return b;
1118
1119 sys_create_link_err:
1120 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1121 class_dev_create_file_err:
1122 class_device_unregister(&b->class_dev);
1123 class_dev_reg_err:
1124 device_unregister(dev);
1125 dev_reg_err:
1126 down_write(&pci_bus_sem);
1127 list_del(&b->node);
1128 up_write(&pci_bus_sem);
1129 err_out:
1130 kfree(dev);
1131 kfree(b);
1132 return NULL;
1133 }
1134 EXPORT_SYMBOL_GPL(pci_create_bus);
1135
1136 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1137 int bus, struct pci_ops *ops, void *sysdata)
1138 {
1139 struct pci_bus *b;
1140
1141 b = pci_create_bus(parent, bus, ops, sysdata);
1142 if (b)
1143 b->subordinate = pci_scan_child_bus(b);
1144 return b;
1145 }
1146 EXPORT_SYMBOL(pci_scan_bus_parented);
1147
1148 #ifdef CONFIG_HOTPLUG
1149 EXPORT_SYMBOL(pci_add_new_bus);
1150 EXPORT_SYMBOL(pci_do_scan_bus);
1151 EXPORT_SYMBOL(pci_scan_slot);
1152 EXPORT_SYMBOL(pci_scan_bridge);
1153 EXPORT_SYMBOL(pci_scan_single_device);
1154 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1155 #endif
1156
1157 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1158 {
1159 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1160 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1161
1162 if (a->bus->number < b->bus->number) return -1;
1163 else if (a->bus->number > b->bus->number) return 1;
1164
1165 if (a->devfn < b->devfn) return -1;
1166 else if (a->devfn > b->devfn) return 1;
1167
1168 return 0;
1169 }
1170
1171 /*
1172 * Yes, this forcably breaks the klist abstraction temporarily. It
1173 * just wants to sort the klist, not change reference counts and
1174 * take/drop locks rapidly in the process. It does all this while
1175 * holding the lock for the list, so objects can't otherwise be
1176 * added/removed while we're swizzling.
1177 */
1178 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1179 {
1180 struct list_head *pos;
1181 struct klist_node *n;
1182 struct device *dev;
1183 struct pci_dev *b;
1184
1185 list_for_each(pos, list) {
1186 n = container_of(pos, struct klist_node, n_node);
1187 dev = container_of(n, struct device, knode_bus);
1188 b = to_pci_dev(dev);
1189 if (pci_sort_bf_cmp(a, b) <= 0) {
1190 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1191 return;
1192 }
1193 }
1194 list_move_tail(&a->dev.knode_bus.n_node, list);
1195 }
1196
1197 static void __init pci_sort_breadthfirst_klist(void)
1198 {
1199 LIST_HEAD(sorted_devices);
1200 struct list_head *pos, *tmp;
1201 struct klist_node *n;
1202 struct device *dev;
1203 struct pci_dev *pdev;
1204
1205 spin_lock(&pci_bus_type.klist_devices.k_lock);
1206 list_for_each_safe(pos, tmp, &pci_bus_type.klist_devices.k_list) {
1207 n = container_of(pos, struct klist_node, n_node);
1208 dev = container_of(n, struct device, knode_bus);
1209 pdev = to_pci_dev(dev);
1210 pci_insertion_sort_klist(pdev, &sorted_devices);
1211 }
1212 list_splice(&sorted_devices, &pci_bus_type.klist_devices.k_list);
1213 spin_unlock(&pci_bus_type.klist_devices.k_lock);
1214 }
1215
1216 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1217 {
1218 struct pci_dev *b;
1219
1220 list_for_each_entry(b, list, global_list) {
1221 if (pci_sort_bf_cmp(a, b) <= 0) {
1222 list_move_tail(&a->global_list, &b->global_list);
1223 return;
1224 }
1225 }
1226 list_move_tail(&a->global_list, list);
1227 }
1228
1229 static void __init pci_sort_breadthfirst_devices(void)
1230 {
1231 LIST_HEAD(sorted_devices);
1232 struct pci_dev *dev, *tmp;
1233
1234 down_write(&pci_bus_sem);
1235 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1236 pci_insertion_sort_devices(dev, &sorted_devices);
1237 }
1238 list_splice(&sorted_devices, &pci_devices);
1239 up_write(&pci_bus_sem);
1240 }
1241
1242 void __init pci_sort_breadthfirst(void)
1243 {
1244 pci_sort_breadthfirst_devices();
1245 pci_sort_breadthfirst_klist();
1246 }
1247
Linux kernel - Deliverables
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