2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci_hotplug.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/cpumask.h>
14 #include <linux/pci-aspm.h>
15 #include <asm-generic/pci-bridge.h>
18 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
19 #define CARDBUS_RESERVE_BUSNR 3
21 static struct resource busn_resource
= {
25 .flags
= IORESOURCE_BUS
,
28 /* Ugh. Need to stop exporting this to modules. */
29 LIST_HEAD(pci_root_buses
);
30 EXPORT_SYMBOL(pci_root_buses
);
32 static LIST_HEAD(pci_domain_busn_res_list
);
34 struct pci_domain_busn_res
{
35 struct list_head list
;
40 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
42 struct pci_domain_busn_res
*r
;
44 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
45 if (r
->domain_nr
== domain_nr
)
48 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
52 r
->domain_nr
= domain_nr
;
55 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
57 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
62 static int find_anything(struct device
*dev
, void *data
)
68 * Some device drivers need know if pci is initiated.
69 * Basically, we think pci is not initiated when there
70 * is no device to be found on the pci_bus_type.
72 int no_pci_devices(void)
77 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
78 no_devices
= (dev
== NULL
);
82 EXPORT_SYMBOL(no_pci_devices
);
87 static void release_pcibus_dev(struct device
*dev
)
89 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
91 put_device(pci_bus
->bridge
);
92 pci_bus_remove_resources(pci_bus
);
93 pci_release_bus_of_node(pci_bus
);
97 static struct class pcibus_class
= {
99 .dev_release
= &release_pcibus_dev
,
100 .dev_groups
= pcibus_groups
,
103 static int __init
pcibus_class_init(void)
105 return class_register(&pcibus_class
);
107 postcore_initcall(pcibus_class_init
);
109 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
111 u64 size
= mask
& maxbase
; /* Find the significant bits */
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size
= (size
& ~(size
-1)) - 1;
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
127 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
132 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
133 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
134 flags
|= IORESOURCE_IO
;
138 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
139 flags
|= IORESOURCE_MEM
;
140 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
141 flags
|= IORESOURCE_PREFETCH
;
143 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
145 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
148 /* 1M mem BAR treated as 32-bit BAR */
150 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
151 flags
|= IORESOURCE_MEM_64
;
154 /* mem unknown type treated as 32-bit BAR */
160 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
172 struct resource
*res
, unsigned int pos
)
175 u64 l64
, sz64
, mask64
;
177 struct pci_bus_region region
, inverted_region
;
179 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
181 /* No printks while decoding is disabled! */
182 if (!dev
->mmio_always_on
) {
183 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
184 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
185 pci_write_config_word(dev
, PCI_COMMAND
,
186 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
190 res
->name
= pci_name(dev
);
192 pci_read_config_dword(dev
, pos
, &l
);
193 pci_write_config_dword(dev
, pos
, l
| mask
);
194 pci_read_config_dword(dev
, pos
, &sz
);
195 pci_write_config_dword(dev
, pos
, l
);
198 * All bits set in sz means the device isn't working properly.
199 * If the BAR isn't implemented, all bits must be 0. If it's a
200 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
203 if (sz
== 0xffffffff)
207 * I don't know how l can have all bits set. Copied from old code.
208 * Maybe it fixes a bug on some ancient platform.
213 if (type
== pci_bar_unknown
) {
214 res
->flags
= decode_bar(dev
, l
);
215 res
->flags
|= IORESOURCE_SIZEALIGN
;
216 if (res
->flags
& IORESOURCE_IO
) {
217 l64
= l
& PCI_BASE_ADDRESS_IO_MASK
;
218 sz64
= sz
& PCI_BASE_ADDRESS_IO_MASK
;
219 mask64
= PCI_BASE_ADDRESS_IO_MASK
& (u32
)IO_SPACE_LIMIT
;
221 l64
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
222 sz64
= sz
& PCI_BASE_ADDRESS_MEM_MASK
;
223 mask64
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
226 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
227 l64
= l
& PCI_ROM_ADDRESS_MASK
;
228 sz64
= sz
& PCI_ROM_ADDRESS_MASK
;
229 mask64
= (u32
)PCI_ROM_ADDRESS_MASK
;
232 if (res
->flags
& IORESOURCE_MEM_64
) {
233 pci_read_config_dword(dev
, pos
+ 4, &l
);
234 pci_write_config_dword(dev
, pos
+ 4, ~0);
235 pci_read_config_dword(dev
, pos
+ 4, &sz
);
236 pci_write_config_dword(dev
, pos
+ 4, l
);
238 l64
|= ((u64
)l
<< 32);
239 sz64
|= ((u64
)sz
<< 32);
240 mask64
|= ((u64
)~0 << 32);
243 if (!dev
->mmio_always_on
&& (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
244 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
249 sz64
= pci_size(l64
, sz64
, mask64
);
251 dev_info(&dev
->dev
, FW_BUG
"reg 0x%x: invalid BAR (can't size)\n",
256 if (res
->flags
& IORESOURCE_MEM_64
) {
257 if ((sizeof(pci_bus_addr_t
) < 8 || sizeof(resource_size_t
) < 8)
258 && sz64
> 0x100000000ULL
) {
259 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
262 dev_err(&dev
->dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
263 pos
, (unsigned long long)sz64
);
267 if ((sizeof(pci_bus_addr_t
) < 8) && l
) {
268 /* Above 32-bit boundary; try to reallocate */
269 res
->flags
|= IORESOURCE_UNSET
;
272 dev_info(&dev
->dev
, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
273 pos
, (unsigned long long)l64
);
279 region
.end
= l64
+ sz64
;
281 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
282 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
285 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
286 * the corresponding resource address (the physical address used by
287 * the CPU. Converting that resource address back to a bus address
288 * should yield the original BAR value:
290 * resource_to_bus(bus_to_resource(A)) == A
292 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
293 * be claimed by the device.
295 if (inverted_region
.start
!= region
.start
) {
296 res
->flags
|= IORESOURCE_UNSET
;
298 res
->end
= region
.end
- region
.start
;
299 dev_info(&dev
->dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
300 pos
, (unsigned long long)region
.start
);
310 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg 0x%x: %pR\n", pos
, res
);
312 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
315 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
317 unsigned int pos
, reg
;
319 for (pos
= 0; pos
< howmany
; pos
++) {
320 struct resource
*res
= &dev
->resource
[pos
];
321 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
322 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
326 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
327 dev
->rom_base_reg
= rom
;
328 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
329 IORESOURCE_READONLY
| IORESOURCE_SIZEALIGN
;
330 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
334 static void pci_read_bridge_io(struct pci_bus
*child
)
336 struct pci_dev
*dev
= child
->self
;
337 u8 io_base_lo
, io_limit_lo
;
338 unsigned long io_mask
, io_granularity
, base
, limit
;
339 struct pci_bus_region region
;
340 struct resource
*res
;
342 io_mask
= PCI_IO_RANGE_MASK
;
343 io_granularity
= 0x1000;
344 if (dev
->io_window_1k
) {
345 /* Support 1K I/O space granularity */
346 io_mask
= PCI_IO_1K_RANGE_MASK
;
347 io_granularity
= 0x400;
350 res
= child
->resource
[0];
351 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
352 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
353 base
= (io_base_lo
& io_mask
) << 8;
354 limit
= (io_limit_lo
& io_mask
) << 8;
356 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
357 u16 io_base_hi
, io_limit_hi
;
359 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
360 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
361 base
|= ((unsigned long) io_base_hi
<< 16);
362 limit
|= ((unsigned long) io_limit_hi
<< 16);
366 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
368 region
.end
= limit
+ io_granularity
- 1;
369 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
370 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
374 static void pci_read_bridge_mmio(struct pci_bus
*child
)
376 struct pci_dev
*dev
= child
->self
;
377 u16 mem_base_lo
, mem_limit_lo
;
378 unsigned long base
, limit
;
379 struct pci_bus_region region
;
380 struct resource
*res
;
382 res
= child
->resource
[1];
383 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
384 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
385 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
386 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
388 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
390 region
.end
= limit
+ 0xfffff;
391 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
392 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
396 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
398 struct pci_dev
*dev
= child
->self
;
399 u16 mem_base_lo
, mem_limit_lo
;
401 pci_bus_addr_t base
, limit
;
402 struct pci_bus_region region
;
403 struct resource
*res
;
405 res
= child
->resource
[2];
406 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
407 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
408 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
409 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
411 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
412 u32 mem_base_hi
, mem_limit_hi
;
414 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
415 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
418 * Some bridges set the base > limit by default, and some
419 * (broken) BIOSes do not initialize them. If we find
420 * this, just assume they are not being used.
422 if (mem_base_hi
<= mem_limit_hi
) {
423 base64
|= (u64
) mem_base_hi
<< 32;
424 limit64
|= (u64
) mem_limit_hi
<< 32;
428 base
= (pci_bus_addr_t
) base64
;
429 limit
= (pci_bus_addr_t
) limit64
;
431 if (base
!= base64
) {
432 dev_err(&dev
->dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
433 (unsigned long long) base64
);
438 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
439 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
440 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
441 res
->flags
|= IORESOURCE_MEM_64
;
443 region
.end
= limit
+ 0xfffff;
444 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
445 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
449 void pci_read_bridge_bases(struct pci_bus
*child
)
451 struct pci_dev
*dev
= child
->self
;
452 struct resource
*res
;
455 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
458 dev_info(&dev
->dev
, "PCI bridge to %pR%s\n",
460 dev
->transparent
? " (subtractive decode)" : "");
462 pci_bus_remove_resources(child
);
463 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
464 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
466 pci_read_bridge_io(child
);
467 pci_read_bridge_mmio(child
);
468 pci_read_bridge_mmio_pref(child
);
470 if (dev
->transparent
) {
471 pci_bus_for_each_resource(child
->parent
, res
, i
) {
472 if (res
&& res
->flags
) {
473 pci_bus_add_resource(child
, res
,
474 PCI_SUBTRACTIVE_DECODE
);
475 dev_printk(KERN_DEBUG
, &dev
->dev
,
476 " bridge window %pR (subtractive decode)\n",
483 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
487 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
491 INIT_LIST_HEAD(&b
->node
);
492 INIT_LIST_HEAD(&b
->children
);
493 INIT_LIST_HEAD(&b
->devices
);
494 INIT_LIST_HEAD(&b
->slots
);
495 INIT_LIST_HEAD(&b
->resources
);
496 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
497 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
498 #ifdef CONFIG_PCI_DOMAINS_GENERIC
500 b
->domain_nr
= parent
->domain_nr
;
505 static void pci_release_host_bridge_dev(struct device
*dev
)
507 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
509 if (bridge
->release_fn
)
510 bridge
->release_fn(bridge
);
512 pci_free_resource_list(&bridge
->windows
);
517 static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus
*b
)
519 struct pci_host_bridge
*bridge
;
521 bridge
= kzalloc(sizeof(*bridge
), GFP_KERNEL
);
525 INIT_LIST_HEAD(&bridge
->windows
);
530 static const unsigned char pcix_bus_speed
[] = {
531 PCI_SPEED_UNKNOWN
, /* 0 */
532 PCI_SPEED_66MHz_PCIX
, /* 1 */
533 PCI_SPEED_100MHz_PCIX
, /* 2 */
534 PCI_SPEED_133MHz_PCIX
, /* 3 */
535 PCI_SPEED_UNKNOWN
, /* 4 */
536 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
537 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
538 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
539 PCI_SPEED_UNKNOWN
, /* 8 */
540 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
541 PCI_SPEED_100MHz_PCIX_266
, /* A */
542 PCI_SPEED_133MHz_PCIX_266
, /* B */
543 PCI_SPEED_UNKNOWN
, /* C */
544 PCI_SPEED_66MHz_PCIX_533
, /* D */
545 PCI_SPEED_100MHz_PCIX_533
, /* E */
546 PCI_SPEED_133MHz_PCIX_533
/* F */
549 const unsigned char pcie_link_speed
[] = {
550 PCI_SPEED_UNKNOWN
, /* 0 */
551 PCIE_SPEED_2_5GT
, /* 1 */
552 PCIE_SPEED_5_0GT
, /* 2 */
553 PCIE_SPEED_8_0GT
, /* 3 */
554 PCI_SPEED_UNKNOWN
, /* 4 */
555 PCI_SPEED_UNKNOWN
, /* 5 */
556 PCI_SPEED_UNKNOWN
, /* 6 */
557 PCI_SPEED_UNKNOWN
, /* 7 */
558 PCI_SPEED_UNKNOWN
, /* 8 */
559 PCI_SPEED_UNKNOWN
, /* 9 */
560 PCI_SPEED_UNKNOWN
, /* A */
561 PCI_SPEED_UNKNOWN
, /* B */
562 PCI_SPEED_UNKNOWN
, /* C */
563 PCI_SPEED_UNKNOWN
, /* D */
564 PCI_SPEED_UNKNOWN
, /* E */
565 PCI_SPEED_UNKNOWN
/* F */
568 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
570 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
572 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
574 static unsigned char agp_speeds
[] = {
582 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
588 else if (agpstat
& 2)
590 else if (agpstat
& 1)
602 return agp_speeds
[index
];
605 static void pci_set_bus_speed(struct pci_bus
*bus
)
607 struct pci_dev
*bridge
= bus
->self
;
610 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
612 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
616 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
617 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
619 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
620 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
623 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
626 enum pci_bus_speed max
;
628 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
631 if (status
& PCI_X_SSTATUS_533MHZ
) {
632 max
= PCI_SPEED_133MHz_PCIX_533
;
633 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
634 max
= PCI_SPEED_133MHz_PCIX_266
;
635 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
636 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
637 max
= PCI_SPEED_133MHz_PCIX_ECC
;
639 max
= PCI_SPEED_133MHz_PCIX
;
641 max
= PCI_SPEED_66MHz_PCIX
;
644 bus
->max_bus_speed
= max
;
645 bus
->cur_bus_speed
= pcix_bus_speed
[
646 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
651 if (pci_is_pcie(bridge
)) {
655 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
656 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
658 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
659 pcie_update_link_speed(bus
, linksta
);
663 static struct irq_domain
*pci_host_bridge_msi_domain(struct pci_bus
*bus
)
665 struct irq_domain
*d
;
668 * Any firmware interface that can resolve the msi_domain
669 * should be called from here.
671 d
= pci_host_bridge_of_msi_domain(bus
);
676 static void pci_set_bus_msi_domain(struct pci_bus
*bus
)
678 struct irq_domain
*d
;
681 * Either bus is the root, and we must obtain it from the
682 * firmware, or we inherit it from the bridge device.
684 if (pci_is_root_bus(bus
))
685 d
= pci_host_bridge_msi_domain(bus
);
687 d
= dev_get_msi_domain(&bus
->self
->dev
);
689 dev_set_msi_domain(&bus
->dev
, d
);
692 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
693 struct pci_dev
*bridge
, int busnr
)
695 struct pci_bus
*child
;
700 * Allocate a new bus, and inherit stuff from the parent..
702 child
= pci_alloc_bus(parent
);
706 child
->parent
= parent
;
707 child
->ops
= parent
->ops
;
708 child
->msi
= parent
->msi
;
709 child
->sysdata
= parent
->sysdata
;
710 child
->bus_flags
= parent
->bus_flags
;
712 /* initialize some portions of the bus device, but don't register it
713 * now as the parent is not properly set up yet.
715 child
->dev
.class = &pcibus_class
;
716 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
719 * Set up the primary, secondary and subordinate
722 child
->number
= child
->busn_res
.start
= busnr
;
723 child
->primary
= parent
->busn_res
.start
;
724 child
->busn_res
.end
= 0xff;
727 child
->dev
.parent
= parent
->bridge
;
731 child
->self
= bridge
;
732 child
->bridge
= get_device(&bridge
->dev
);
733 child
->dev
.parent
= child
->bridge
;
734 pci_set_bus_of_node(child
);
735 pci_set_bus_speed(child
);
737 /* Set up default resource pointers and names.. */
738 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
739 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
740 child
->resource
[i
]->name
= child
->name
;
742 bridge
->subordinate
= child
;
745 pci_set_bus_msi_domain(child
);
746 ret
= device_register(&child
->dev
);
749 pcibios_add_bus(child
);
751 /* Create legacy_io and legacy_mem files for this bus */
752 pci_create_legacy_files(child
);
757 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
760 struct pci_bus
*child
;
762 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
764 down_write(&pci_bus_sem
);
765 list_add_tail(&child
->node
, &parent
->children
);
766 up_write(&pci_bus_sem
);
770 EXPORT_SYMBOL(pci_add_new_bus
);
772 static void pci_enable_crs(struct pci_dev
*pdev
)
776 /* Enable CRS Software Visibility if supported */
777 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
778 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
779 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
780 PCI_EXP_RTCTL_CRSSVE
);
784 * If it's a bridge, configure it and scan the bus behind it.
785 * For CardBus bridges, we don't scan behind as the devices will
786 * be handled by the bridge driver itself.
788 * We need to process bridges in two passes -- first we scan those
789 * already configured by the BIOS and after we are done with all of
790 * them, we proceed to assigning numbers to the remaining buses in
791 * order to avoid overlaps between old and new bus numbers.
793 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
795 struct pci_bus
*child
;
796 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
799 u8 primary
, secondary
, subordinate
;
802 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
803 primary
= buses
& 0xFF;
804 secondary
= (buses
>> 8) & 0xFF;
805 subordinate
= (buses
>> 16) & 0xFF;
807 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
808 secondary
, subordinate
, pass
);
810 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
811 dev_warn(&dev
->dev
, "Primary bus is hard wired to 0\n");
812 primary
= bus
->number
;
815 /* Check if setup is sensible at all */
817 (primary
!= bus
->number
|| secondary
<= bus
->number
||
818 secondary
> subordinate
)) {
819 dev_info(&dev
->dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
820 secondary
, subordinate
);
824 /* Disable MasterAbortMode during probing to avoid reporting
825 of bus errors (in some architectures) */
826 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
827 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
828 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
832 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
833 !is_cardbus
&& !broken
) {
836 * Bus already configured by firmware, process it in the first
837 * pass and just note the configuration.
843 * The bus might already exist for two reasons: Either we are
844 * rescanning the bus or the bus is reachable through more than
845 * one bridge. The second case can happen with the i450NX
848 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
850 child
= pci_add_new_bus(bus
, dev
, secondary
);
853 child
->primary
= primary
;
854 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
855 child
->bridge_ctl
= bctl
;
858 /* Read and initialize bridge resources */
859 pci_read_bridge_bases(child
);
861 cmax
= pci_scan_child_bus(child
);
862 if (cmax
> subordinate
)
863 dev_warn(&dev
->dev
, "bridge has subordinate %02x but max busn %02x\n",
865 /* subordinate should equal child->busn_res.end */
866 if (subordinate
> max
)
870 * We need to assign a number to this bus which we always
871 * do in the second pass.
874 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
875 /* Temporarily disable forwarding of the
876 configuration cycles on all bridges in
877 this bus segment to avoid possible
878 conflicts in the second pass between two
879 bridges programmed with overlapping
881 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
887 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
889 /* Prevent assigning a bus number that already exists.
890 * This can happen when a bridge is hot-plugged, so in
891 * this case we only re-scan this bus. */
892 child
= pci_find_bus(pci_domain_nr(bus
), max
+1);
894 child
= pci_add_new_bus(bus
, dev
, max
+1);
897 pci_bus_insert_busn_res(child
, max
+1, 0xff);
900 buses
= (buses
& 0xff000000)
901 | ((unsigned int)(child
->primary
) << 0)
902 | ((unsigned int)(child
->busn_res
.start
) << 8)
903 | ((unsigned int)(child
->busn_res
.end
) << 16);
906 * yenta.c forces a secondary latency timer of 176.
907 * Copy that behaviour here.
910 buses
&= ~0xff000000;
911 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
915 * We need to blast all three values with a single write.
917 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
920 child
->bridge_ctl
= bctl
;
922 /* Read and initialize bridge resources */
923 pci_read_bridge_bases(child
);
924 max
= pci_scan_child_bus(child
);
927 * For CardBus bridges, we leave 4 bus numbers
928 * as cards with a PCI-to-PCI bridge can be
931 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
932 struct pci_bus
*parent
= bus
;
933 if (pci_find_bus(pci_domain_nr(bus
),
936 while (parent
->parent
) {
937 if ((!pcibios_assign_all_busses()) &&
938 (parent
->busn_res
.end
> max
) &&
939 (parent
->busn_res
.end
<= max
+i
)) {
942 parent
= parent
->parent
;
946 * Often, there are two cardbus bridges
947 * -- try to leave one valid bus number
957 * Set the subordinate bus number to its real value.
959 pci_bus_update_busn_res_end(child
, max
);
960 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
964 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
965 pci_domain_nr(bus
), child
->number
);
967 /* Has only triggered on CardBus, fixup is in yenta_socket */
968 while (bus
->parent
) {
969 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
970 (child
->number
> bus
->busn_res
.end
) ||
971 (child
->number
< bus
->number
) ||
972 (child
->busn_res
.end
< bus
->number
)) {
973 dev_info(&child
->dev
, "%pR %s hidden behind%s bridge %s %pR\n",
975 (bus
->number
> child
->busn_res
.end
&&
976 bus
->busn_res
.end
< child
->number
) ?
977 "wholly" : "partially",
978 bus
->self
->transparent
? " transparent" : "",
986 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
990 EXPORT_SYMBOL(pci_scan_bridge
);
993 * Read interrupt line and base address registers.
994 * The architecture-dependent code can tweak these, of course.
996 static void pci_read_irq(struct pci_dev
*dev
)
1000 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
1003 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1007 void set_pcie_port_type(struct pci_dev
*pdev
)
1012 struct pci_dev
*parent
;
1014 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1017 pdev
->pcie_cap
= pos
;
1018 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
1019 pdev
->pcie_flags_reg
= reg16
;
1020 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
1021 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
1024 * A Root Port is always the upstream end of a Link. No PCIe
1025 * component has two Links. Two Links are connected by a Switch
1026 * that has a Port on each Link and internal logic to connect the
1029 type
= pci_pcie_type(pdev
);
1030 if (type
== PCI_EXP_TYPE_ROOT_PORT
)
1031 pdev
->has_secondary_link
= 1;
1032 else if (type
== PCI_EXP_TYPE_UPSTREAM
||
1033 type
== PCI_EXP_TYPE_DOWNSTREAM
) {
1034 parent
= pci_upstream_bridge(pdev
);
1037 * Usually there's an upstream device (Root Port or Switch
1038 * Downstream Port), but we can't assume one exists.
1040 if (parent
&& !parent
->has_secondary_link
)
1041 pdev
->has_secondary_link
= 1;
1045 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1049 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1050 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1051 pdev
->is_hotplug_bridge
= 1;
1055 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1058 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1059 * when forwarding a type1 configuration request the bridge must check that
1060 * the extended register address field is zero. The bridge is not permitted
1061 * to forward the transactions and must handle it as an Unsupported Request.
1062 * Some bridges do not follow this rule and simply drop the extended register
1063 * bits, resulting in the standard config space being aliased, every 256
1064 * bytes across the entire configuration space. Test for this condition by
1065 * comparing the first dword of each potential alias to the vendor/device ID.
1067 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1068 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1070 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1072 #ifdef CONFIG_PCI_QUIRKS
1076 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1078 for (pos
= PCI_CFG_SPACE_SIZE
;
1079 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1080 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1092 * pci_cfg_space_size - get the configuration space size of the PCI device.
1095 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1096 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1097 * access it. Maybe we don't have a way to generate extended config space
1098 * accesses, or the device is behind a reverse Express bridge. So we try
1099 * reading the dword at 0x100 which must either be 0 or a valid extended
1100 * capability header.
1102 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1105 int pos
= PCI_CFG_SPACE_SIZE
;
1107 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1109 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1112 return PCI_CFG_SPACE_EXP_SIZE
;
1115 return PCI_CFG_SPACE_SIZE
;
1118 int pci_cfg_space_size(struct pci_dev
*dev
)
1124 class = dev
->class >> 8;
1125 if (class == PCI_CLASS_BRIDGE_HOST
)
1126 return pci_cfg_space_size_ext(dev
);
1128 if (!pci_is_pcie(dev
)) {
1129 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1133 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1134 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
1138 return pci_cfg_space_size_ext(dev
);
1141 return PCI_CFG_SPACE_SIZE
;
1144 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1146 void pci_msi_setup_pci_dev(struct pci_dev
*dev
)
1149 * Disable the MSI hardware to avoid screaming interrupts
1150 * during boot. This is the power on reset default so
1151 * usually this should be a noop.
1153 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1155 pci_msi_set_enable(dev
, 0);
1157 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1159 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1163 * pci_setup_device - fill in class and map information of a device
1164 * @dev: the device structure to fill
1166 * Initialize the device structure with information about the device's
1167 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1168 * Called at initialisation of the PCI subsystem and by CardBus services.
1169 * Returns 0 on success and negative if unknown type of device (not normal,
1170 * bridge or CardBus).
1172 int pci_setup_device(struct pci_dev
*dev
)
1177 struct pci_bus_region region
;
1178 struct resource
*res
;
1180 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
1183 dev
->sysdata
= dev
->bus
->sysdata
;
1184 dev
->dev
.parent
= dev
->bus
->bridge
;
1185 dev
->dev
.bus
= &pci_bus_type
;
1186 dev
->hdr_type
= hdr_type
& 0x7f;
1187 dev
->multifunction
= !!(hdr_type
& 0x80);
1188 dev
->error_state
= pci_channel_io_normal
;
1189 set_pcie_port_type(dev
);
1191 pci_dev_assign_slot(dev
);
1192 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1193 set this higher, assuming the system even supports it. */
1194 dev
->dma_mask
= 0xffffffff;
1196 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1197 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1198 PCI_FUNC(dev
->devfn
));
1200 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1201 dev
->revision
= class & 0xff;
1202 dev
->class = class >> 8; /* upper 3 bytes */
1204 dev_printk(KERN_DEBUG
, &dev
->dev
, "[%04x:%04x] type %02x class %#08x\n",
1205 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1207 /* need to have dev->class ready */
1208 dev
->cfg_size
= pci_cfg_space_size(dev
);
1210 /* "Unknown power state" */
1211 dev
->current_state
= PCI_UNKNOWN
;
1213 pci_msi_setup_pci_dev(dev
);
1215 /* Early fixups, before probing the BARs */
1216 pci_fixup_device(pci_fixup_early
, dev
);
1217 /* device class may be changed after fixup */
1218 class = dev
->class >> 8;
1220 switch (dev
->hdr_type
) { /* header type */
1221 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1222 if (class == PCI_CLASS_BRIDGE_PCI
)
1225 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1226 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1227 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1230 * Do the ugly legacy mode stuff here rather than broken chip
1231 * quirk code. Legacy mode ATA controllers have fixed
1232 * addresses. These are not always echoed in BAR0-3, and
1233 * BAR0-3 in a few cases contain junk!
1235 if (class == PCI_CLASS_STORAGE_IDE
) {
1237 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1238 if ((progif
& 1) == 0) {
1239 region
.start
= 0x1F0;
1241 res
= &dev
->resource
[0];
1242 res
->flags
= LEGACY_IO_RESOURCE
;
1243 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1244 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1246 region
.start
= 0x3F6;
1248 res
= &dev
->resource
[1];
1249 res
->flags
= LEGACY_IO_RESOURCE
;
1250 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1251 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1254 if ((progif
& 4) == 0) {
1255 region
.start
= 0x170;
1257 res
= &dev
->resource
[2];
1258 res
->flags
= LEGACY_IO_RESOURCE
;
1259 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1260 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1262 region
.start
= 0x376;
1264 res
= &dev
->resource
[3];
1265 res
->flags
= LEGACY_IO_RESOURCE
;
1266 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1267 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1273 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1274 if (class != PCI_CLASS_BRIDGE_PCI
)
1276 /* The PCI-to-PCI bridge spec requires that subtractive
1277 decoding (i.e. transparent) bridge must have programming
1278 interface code of 0x01. */
1280 dev
->transparent
= ((dev
->class & 0xff) == 1);
1281 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1282 set_pcie_hotplug_bridge(dev
);
1283 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1285 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1286 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1290 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1291 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1294 pci_read_bases(dev
, 1, 0);
1295 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1296 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1299 default: /* unknown header */
1300 dev_err(&dev
->dev
, "unknown header type %02x, ignoring device\n",
1305 dev_err(&dev
->dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
1306 dev
->class, dev
->hdr_type
);
1307 dev
->class = PCI_CLASS_NOT_DEFINED
<< 8;
1310 /* We found a fine healthy device, go go go... */
1314 static void pci_configure_mps(struct pci_dev
*dev
)
1316 struct pci_dev
*bridge
= pci_upstream_bridge(dev
);
1319 if (!pci_is_pcie(dev
) || !bridge
|| !pci_is_pcie(bridge
))
1322 mps
= pcie_get_mps(dev
);
1323 p_mps
= pcie_get_mps(bridge
);
1328 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
1329 dev_warn(&dev
->dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1330 mps
, pci_name(bridge
), p_mps
);
1335 * Fancier MPS configuration is done later by
1336 * pcie_bus_configure_settings()
1338 if (pcie_bus_config
!= PCIE_BUS_DEFAULT
)
1341 rc
= pcie_set_mps(dev
, p_mps
);
1343 dev_warn(&dev
->dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1348 dev_info(&dev
->dev
, "Max Payload Size set to %d (was %d, max %d)\n",
1349 p_mps
, mps
, 128 << dev
->pcie_mpss
);
1352 static struct hpp_type0 pci_default_type0
= {
1354 .cache_line_size
= 8,
1355 .latency_timer
= 0x40,
1360 static void program_hpp_type0(struct pci_dev
*dev
, struct hpp_type0
*hpp
)
1362 u16 pci_cmd
, pci_bctl
;
1365 hpp
= &pci_default_type0
;
1367 if (hpp
->revision
> 1) {
1369 "PCI settings rev %d not supported; using defaults\n",
1371 hpp
= &pci_default_type0
;
1374 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, hpp
->cache_line_size
);
1375 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, hpp
->latency_timer
);
1376 pci_read_config_word(dev
, PCI_COMMAND
, &pci_cmd
);
1377 if (hpp
->enable_serr
)
1378 pci_cmd
|= PCI_COMMAND_SERR
;
1379 if (hpp
->enable_perr
)
1380 pci_cmd
|= PCI_COMMAND_PARITY
;
1381 pci_write_config_word(dev
, PCI_COMMAND
, pci_cmd
);
1383 /* Program bridge control value */
1384 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1385 pci_write_config_byte(dev
, PCI_SEC_LATENCY_TIMER
,
1386 hpp
->latency_timer
);
1387 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &pci_bctl
);
1388 if (hpp
->enable_serr
)
1389 pci_bctl
|= PCI_BRIDGE_CTL_SERR
;
1390 if (hpp
->enable_perr
)
1391 pci_bctl
|= PCI_BRIDGE_CTL_PARITY
;
1392 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, pci_bctl
);
1396 static void program_hpp_type1(struct pci_dev
*dev
, struct hpp_type1
*hpp
)
1399 dev_warn(&dev
->dev
, "PCI-X settings not supported\n");
1402 static void program_hpp_type2(struct pci_dev
*dev
, struct hpp_type2
*hpp
)
1410 if (hpp
->revision
> 1) {
1411 dev_warn(&dev
->dev
, "PCIe settings rev %d not supported\n",
1417 * Don't allow _HPX to change MPS or MRRS settings. We manage
1418 * those to make sure they're consistent with the rest of the
1421 hpp
->pci_exp_devctl_and
|= PCI_EXP_DEVCTL_PAYLOAD
|
1422 PCI_EXP_DEVCTL_READRQ
;
1423 hpp
->pci_exp_devctl_or
&= ~(PCI_EXP_DEVCTL_PAYLOAD
|
1424 PCI_EXP_DEVCTL_READRQ
);
1426 /* Initialize Device Control Register */
1427 pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
1428 ~hpp
->pci_exp_devctl_and
, hpp
->pci_exp_devctl_or
);
1430 /* Initialize Link Control Register */
1431 if (pcie_cap_has_lnkctl(dev
))
1432 pcie_capability_clear_and_set_word(dev
, PCI_EXP_LNKCTL
,
1433 ~hpp
->pci_exp_lnkctl_and
, hpp
->pci_exp_lnkctl_or
);
1435 /* Find Advanced Error Reporting Enhanced Capability */
1436 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
1440 /* Initialize Uncorrectable Error Mask Register */
1441 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, ®32
);
1442 reg32
= (reg32
& hpp
->unc_err_mask_and
) | hpp
->unc_err_mask_or
;
1443 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, reg32
);
1445 /* Initialize Uncorrectable Error Severity Register */
1446 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, ®32
);
1447 reg32
= (reg32
& hpp
->unc_err_sever_and
) | hpp
->unc_err_sever_or
;
1448 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, reg32
);
1450 /* Initialize Correctable Error Mask Register */
1451 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®32
);
1452 reg32
= (reg32
& hpp
->cor_err_mask_and
) | hpp
->cor_err_mask_or
;
1453 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg32
);
1455 /* Initialize Advanced Error Capabilities and Control Register */
1456 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
1457 reg32
= (reg32
& hpp
->adv_err_cap_and
) | hpp
->adv_err_cap_or
;
1458 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
1461 * FIXME: The following two registers are not supported yet.
1463 * o Secondary Uncorrectable Error Severity Register
1464 * o Secondary Uncorrectable Error Mask Register
1468 static void pci_configure_device(struct pci_dev
*dev
)
1470 struct hotplug_params hpp
;
1473 pci_configure_mps(dev
);
1475 memset(&hpp
, 0, sizeof(hpp
));
1476 ret
= pci_get_hp_params(dev
, &hpp
);
1480 program_hpp_type2(dev
, hpp
.t2
);
1481 program_hpp_type1(dev
, hpp
.t1
);
1482 program_hpp_type0(dev
, hpp
.t0
);
1485 static void pci_release_capabilities(struct pci_dev
*dev
)
1487 pci_vpd_release(dev
);
1488 pci_iov_release(dev
);
1489 pci_free_cap_save_buffers(dev
);
1493 * pci_release_dev - free a pci device structure when all users of it are finished.
1494 * @dev: device that's been disconnected
1496 * Will be called only by the device core when all users of this pci device are
1499 static void pci_release_dev(struct device
*dev
)
1501 struct pci_dev
*pci_dev
;
1503 pci_dev
= to_pci_dev(dev
);
1504 pci_release_capabilities(pci_dev
);
1505 pci_release_of_node(pci_dev
);
1506 pcibios_release_device(pci_dev
);
1507 pci_bus_put(pci_dev
->bus
);
1508 kfree(pci_dev
->driver_override
);
1512 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
1514 struct pci_dev
*dev
;
1516 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1520 INIT_LIST_HEAD(&dev
->bus_list
);
1521 dev
->dev
.type
= &pci_dev_type
;
1522 dev
->bus
= pci_bus_get(bus
);
1526 EXPORT_SYMBOL(pci_alloc_dev
);
1528 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
1533 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1536 /* some broken boards return 0 or ~0 if a slot is empty: */
1537 if (*l
== 0xffffffff || *l
== 0x00000000 ||
1538 *l
== 0x0000ffff || *l
== 0xffff0000)
1542 * Configuration Request Retry Status. Some root ports return the
1543 * actual device ID instead of the synthetic ID (0xFFFF) required
1544 * by the PCIe spec. Ignore the device ID and only check for
1547 while ((*l
& 0xffff) == 0x0001) {
1553 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1555 /* Card hasn't responded in 60 seconds? Must be stuck. */
1556 if (delay
> crs_timeout
) {
1557 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not responding\n",
1558 pci_domain_nr(bus
), bus
->number
, PCI_SLOT(devfn
),
1566 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
1569 * Read the config data for a PCI device, sanity-check it
1570 * and fill in the dev structure...
1572 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1574 struct pci_dev
*dev
;
1577 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
1580 dev
= pci_alloc_dev(bus
);
1585 dev
->vendor
= l
& 0xffff;
1586 dev
->device
= (l
>> 16) & 0xffff;
1588 pci_set_of_node(dev
);
1590 if (pci_setup_device(dev
)) {
1591 pci_bus_put(dev
->bus
);
1599 static void pci_init_capabilities(struct pci_dev
*dev
)
1601 /* MSI/MSI-X list */
1602 pci_msi_init_pci_dev(dev
);
1604 /* Buffers for saving PCIe and PCI-X capabilities */
1605 pci_allocate_cap_save_buffers(dev
);
1607 /* Power Management */
1610 /* Vital Product Data */
1611 pci_vpd_pci22_init(dev
);
1613 /* Alternative Routing-ID Forwarding */
1614 pci_configure_ari(dev
);
1616 /* Single Root I/O Virtualization */
1619 /* Address Translation Services */
1622 /* Enable ACS P2P upstream forwarding */
1623 pci_enable_acs(dev
);
1626 static void pci_set_msi_domain(struct pci_dev
*dev
)
1629 * If no domain has been set through the pcibios_add_device
1630 * callback, inherit the default from the bus device.
1632 if (!dev_get_msi_domain(&dev
->dev
))
1633 dev_set_msi_domain(&dev
->dev
,
1634 dev_get_msi_domain(&dev
->bus
->dev
));
1637 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1641 pci_configure_device(dev
);
1643 device_initialize(&dev
->dev
);
1644 dev
->dev
.release
= pci_release_dev
;
1646 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
1647 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1648 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1649 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1650 of_pci_dma_configure(dev
);
1652 pci_set_dma_max_seg_size(dev
, 65536);
1653 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1655 /* Fix up broken headers */
1656 pci_fixup_device(pci_fixup_header
, dev
);
1658 /* moved out from quirk header fixup code */
1659 pci_reassigndev_resource_alignment(dev
);
1661 /* Clear the state_saved flag. */
1662 dev
->state_saved
= false;
1664 /* Initialize various capabilities */
1665 pci_init_capabilities(dev
);
1668 * Add the device to our list of discovered devices
1669 * and the bus list for fixup functions, etc.
1671 down_write(&pci_bus_sem
);
1672 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1673 up_write(&pci_bus_sem
);
1675 ret
= pcibios_add_device(dev
);
1678 /* Setup MSI irq domain */
1679 pci_set_msi_domain(dev
);
1681 /* Notifier could use PCI capabilities */
1682 dev
->match_driver
= false;
1683 ret
= device_add(&dev
->dev
);
1687 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1689 struct pci_dev
*dev
;
1691 dev
= pci_get_slot(bus
, devfn
);
1697 dev
= pci_scan_device(bus
, devfn
);
1701 pci_device_add(dev
, bus
);
1705 EXPORT_SYMBOL(pci_scan_single_device
);
1707 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
1713 if (pci_ari_enabled(bus
)) {
1716 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1720 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
1721 next_fn
= PCI_ARI_CAP_NFN(cap
);
1723 return 0; /* protect against malformed list */
1728 /* dev may be NULL for non-contiguous multifunction devices */
1729 if (!dev
|| dev
->multifunction
)
1730 return (fn
+ 1) % 8;
1735 static int only_one_child(struct pci_bus
*bus
)
1737 struct pci_dev
*parent
= bus
->self
;
1739 if (!parent
|| !pci_is_pcie(parent
))
1741 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_ROOT_PORT
)
1743 if (parent
->has_secondary_link
&&
1744 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
1750 * pci_scan_slot - scan a PCI slot on a bus for devices.
1751 * @bus: PCI bus to scan
1752 * @devfn: slot number to scan (must have zero function.)
1754 * Scan a PCI slot on the specified PCI bus for devices, adding
1755 * discovered devices to the @bus->devices list. New devices
1756 * will not have is_added set.
1758 * Returns the number of new devices found.
1760 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1762 unsigned fn
, nr
= 0;
1763 struct pci_dev
*dev
;
1765 if (only_one_child(bus
) && (devfn
> 0))
1766 return 0; /* Already scanned the entire slot */
1768 dev
= pci_scan_single_device(bus
, devfn
);
1774 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
1775 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1779 dev
->multifunction
= 1;
1783 /* only one slot has pcie device */
1784 if (bus
->self
&& nr
)
1785 pcie_aspm_init_link_state(bus
->self
);
1789 EXPORT_SYMBOL(pci_scan_slot
);
1791 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
1795 if (!pci_is_pcie(dev
))
1799 * We don't have a way to change MPS settings on devices that have
1800 * drivers attached. A hot-added device might support only the minimum
1801 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1802 * where devices may be hot-added, we limit the fabric MPS to 128 so
1803 * hot-added devices will work correctly.
1805 * However, if we hot-add a device to a slot directly below a Root
1806 * Port, it's impossible for there to be other existing devices below
1807 * the port. We don't limit the MPS in this case because we can
1808 * reconfigure MPS on both the Root Port and the hot-added device,
1809 * and there are no other devices involved.
1811 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1813 if (dev
->is_hotplug_bridge
&&
1814 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
1817 if (*smpss
> dev
->pcie_mpss
)
1818 *smpss
= dev
->pcie_mpss
;
1823 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
1827 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
1828 mps
= 128 << dev
->pcie_mpss
;
1830 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
1832 /* For "Performance", the assumption is made that
1833 * downstream communication will never be larger than
1834 * the MRRS. So, the MPS only needs to be configured
1835 * for the upstream communication. This being the case,
1836 * walk from the top down and set the MPS of the child
1837 * to that of the parent bus.
1839 * Configure the device MPS with the smaller of the
1840 * device MPSS or the bridge MPS (which is assumed to be
1841 * properly configured at this point to the largest
1842 * allowable MPS based on its parent bus).
1844 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
1847 rc
= pcie_set_mps(dev
, mps
);
1849 dev_err(&dev
->dev
, "Failed attempting to set the MPS\n");
1852 static void pcie_write_mrrs(struct pci_dev
*dev
)
1856 /* In the "safe" case, do not configure the MRRS. There appear to be
1857 * issues with setting MRRS to 0 on a number of devices.
1859 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
1862 /* For Max performance, the MRRS must be set to the largest supported
1863 * value. However, it cannot be configured larger than the MPS the
1864 * device or the bus can support. This should already be properly
1865 * configured by a prior call to pcie_write_mps.
1867 mrrs
= pcie_get_mps(dev
);
1869 /* MRRS is a R/W register. Invalid values can be written, but a
1870 * subsequent read will verify if the value is acceptable or not.
1871 * If the MRRS value provided is not acceptable (e.g., too large),
1872 * shrink the value until it is acceptable to the HW.
1874 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
1875 rc
= pcie_set_readrq(dev
, mrrs
);
1879 dev_warn(&dev
->dev
, "Failed attempting to set the MRRS\n");
1884 dev_err(&dev
->dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1887 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
1891 if (!pci_is_pcie(dev
))
1894 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
1895 pcie_bus_config
== PCIE_BUS_DEFAULT
)
1898 mps
= 128 << *(u8
*)data
;
1899 orig_mps
= pcie_get_mps(dev
);
1901 pcie_write_mps(dev
, mps
);
1902 pcie_write_mrrs(dev
);
1904 dev_info(&dev
->dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1905 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
1906 orig_mps
, pcie_get_readrq(dev
));
1911 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1912 * parents then children fashion. If this changes, then this code will not
1915 void pcie_bus_configure_settings(struct pci_bus
*bus
)
1922 if (!pci_is_pcie(bus
->self
))
1925 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1926 * to be aware of the MPS of the destination. To work around this,
1927 * simply force the MPS of the entire system to the smallest possible.
1929 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
1932 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
1933 smpss
= bus
->self
->pcie_mpss
;
1935 pcie_find_smpss(bus
->self
, &smpss
);
1936 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
1939 pcie_bus_configure_set(bus
->self
, &smpss
);
1940 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
1942 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
1944 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
1946 unsigned int devfn
, pass
, max
= bus
->busn_res
.start
;
1947 struct pci_dev
*dev
;
1949 dev_dbg(&bus
->dev
, "scanning bus\n");
1951 /* Go find them, Rover! */
1952 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1953 pci_scan_slot(bus
, devfn
);
1955 /* Reserve buses for SR-IOV capability. */
1956 max
+= pci_iov_bus_range(bus
);
1959 * After performing arch-dependent fixup of the bus, look behind
1960 * all PCI-to-PCI bridges on this bus.
1962 if (!bus
->is_added
) {
1963 dev_dbg(&bus
->dev
, "fixups for bus\n");
1964 pcibios_fixup_bus(bus
);
1968 for (pass
= 0; pass
< 2; pass
++)
1969 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1970 if (pci_is_bridge(dev
))
1971 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1975 * We've scanned the bus and so we know all about what's on
1976 * the other side of any bridges that may be on this bus plus
1979 * Return how far we've got finding sub-buses.
1981 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1984 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1987 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1988 * @bridge: Host bridge to set up.
1990 * Default empty implementation. Replace with an architecture-specific setup
1991 * routine, if necessary.
1993 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
1998 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
2002 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
2006 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
2007 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2010 struct pci_host_bridge
*bridge
;
2011 struct pci_bus
*b
, *b2
;
2012 struct resource_entry
*window
, *n
;
2013 struct resource
*res
;
2014 resource_size_t offset
;
2018 b
= pci_alloc_bus(NULL
);
2022 b
->sysdata
= sysdata
;
2024 b
->number
= b
->busn_res
.start
= bus
;
2025 pci_bus_assign_domain_nr(b
, parent
);
2026 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
2028 /* If we already got to this bus through a different bridge, ignore it */
2029 dev_dbg(&b2
->dev
, "bus already known\n");
2033 bridge
= pci_alloc_host_bridge(b
);
2037 bridge
->dev
.parent
= parent
;
2038 bridge
->dev
.release
= pci_release_host_bridge_dev
;
2039 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
2040 error
= pcibios_root_bridge_prepare(bridge
);
2046 error
= device_register(&bridge
->dev
);
2048 put_device(&bridge
->dev
);
2051 b
->bridge
= get_device(&bridge
->dev
);
2052 device_enable_async_suspend(b
->bridge
);
2053 pci_set_bus_of_node(b
);
2054 pci_set_bus_msi_domain(b
);
2057 set_dev_node(b
->bridge
, pcibus_to_node(b
));
2059 b
->dev
.class = &pcibus_class
;
2060 b
->dev
.parent
= b
->bridge
;
2061 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
2062 error
= device_register(&b
->dev
);
2064 goto class_dev_reg_err
;
2068 /* Create legacy_io and legacy_mem files for this bus */
2069 pci_create_legacy_files(b
);
2072 dev_info(parent
, "PCI host bridge to bus %s\n", dev_name(&b
->dev
));
2074 printk(KERN_INFO
"PCI host bridge to bus %s\n", dev_name(&b
->dev
));
2076 /* Add initial resources to the bus */
2077 resource_list_for_each_entry_safe(window
, n
, resources
) {
2078 list_move_tail(&window
->node
, &bridge
->windows
);
2080 offset
= window
->offset
;
2081 if (res
->flags
& IORESOURCE_BUS
)
2082 pci_bus_insert_busn_res(b
, bus
, res
->end
);
2084 pci_bus_add_resource(b
, res
, 0);
2086 if (resource_type(res
) == IORESOURCE_IO
)
2087 fmt
= " (bus address [%#06llx-%#06llx])";
2089 fmt
= " (bus address [%#010llx-%#010llx])";
2090 snprintf(bus_addr
, sizeof(bus_addr
), fmt
,
2091 (unsigned long long) (res
->start
- offset
),
2092 (unsigned long long) (res
->end
- offset
));
2095 dev_info(&b
->dev
, "root bus resource %pR%s\n", res
, bus_addr
);
2098 down_write(&pci_bus_sem
);
2099 list_add_tail(&b
->node
, &pci_root_buses
);
2100 up_write(&pci_bus_sem
);
2105 put_device(&bridge
->dev
);
2106 device_unregister(&bridge
->dev
);
2111 EXPORT_SYMBOL_GPL(pci_create_root_bus
);
2113 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
2115 struct resource
*res
= &b
->busn_res
;
2116 struct resource
*parent_res
, *conflict
;
2120 res
->flags
= IORESOURCE_BUS
;
2122 if (!pci_is_root_bus(b
))
2123 parent_res
= &b
->parent
->busn_res
;
2125 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
2126 res
->flags
|= IORESOURCE_PCI_FIXED
;
2129 conflict
= request_resource_conflict(parent_res
, res
);
2132 dev_printk(KERN_DEBUG
, &b
->dev
,
2133 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2134 res
, pci_is_root_bus(b
) ? "domain " : "",
2135 parent_res
, conflict
->name
, conflict
);
2137 return conflict
== NULL
;
2140 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
2142 struct resource
*res
= &b
->busn_res
;
2143 struct resource old_res
= *res
;
2144 resource_size_t size
;
2147 if (res
->start
> bus_max
)
2150 size
= bus_max
- res
->start
+ 1;
2151 ret
= adjust_resource(res
, res
->start
, size
);
2152 dev_printk(KERN_DEBUG
, &b
->dev
,
2153 "busn_res: %pR end %s updated to %02x\n",
2154 &old_res
, ret
? "can not be" : "is", bus_max
);
2156 if (!ret
&& !res
->parent
)
2157 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
2162 void pci_bus_release_busn_res(struct pci_bus
*b
)
2164 struct resource
*res
= &b
->busn_res
;
2167 if (!res
->flags
|| !res
->parent
)
2170 ret
= release_resource(res
);
2171 dev_printk(KERN_DEBUG
, &b
->dev
,
2172 "busn_res: %pR %s released\n",
2173 res
, ret
? "can not be" : "is");
2176 struct pci_bus
*pci_scan_root_bus_msi(struct device
*parent
, int bus
,
2177 struct pci_ops
*ops
, void *sysdata
,
2178 struct list_head
*resources
, struct msi_controller
*msi
)
2180 struct resource_entry
*window
;
2185 resource_list_for_each_entry(window
, resources
)
2186 if (window
->res
->flags
& IORESOURCE_BUS
) {
2191 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
2199 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2201 pci_bus_insert_busn_res(b
, bus
, 255);
2204 max
= pci_scan_child_bus(b
);
2207 pci_bus_update_busn_res_end(b
, max
);
2212 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
2213 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2215 return pci_scan_root_bus_msi(parent
, bus
, ops
, sysdata
, resources
,
2218 EXPORT_SYMBOL(pci_scan_root_bus
);
2220 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
2223 LIST_HEAD(resources
);
2226 pci_add_resource(&resources
, &ioport_resource
);
2227 pci_add_resource(&resources
, &iomem_resource
);
2228 pci_add_resource(&resources
, &busn_resource
);
2229 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
2231 pci_scan_child_bus(b
);
2233 pci_free_resource_list(&resources
);
2237 EXPORT_SYMBOL(pci_scan_bus
);
2240 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2241 * @bridge: PCI bridge for the bus to scan
2243 * Scan a PCI bus and child buses for new devices, add them,
2244 * and enable them, resizing bridge mmio/io resource if necessary
2245 * and possible. The caller must ensure the child devices are already
2246 * removed for resizing to occur.
2248 * Returns the max number of subordinate bus discovered.
2250 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
2253 struct pci_bus
*bus
= bridge
->subordinate
;
2255 max
= pci_scan_child_bus(bus
);
2257 pci_assign_unassigned_bridge_resources(bridge
);
2259 pci_bus_add_devices(bus
);
2265 * pci_rescan_bus - scan a PCI bus for devices.
2266 * @bus: PCI bus to scan
2268 * Scan a PCI bus and child buses for new devices, adds them,
2271 * Returns the max number of subordinate bus discovered.
2273 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
2277 max
= pci_scan_child_bus(bus
);
2278 pci_assign_unassigned_bus_resources(bus
);
2279 pci_bus_add_devices(bus
);
2283 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
2286 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2287 * routines should always be executed under this mutex.
2289 static DEFINE_MUTEX(pci_rescan_remove_lock
);
2291 void pci_lock_rescan_remove(void)
2293 mutex_lock(&pci_rescan_remove_lock
);
2295 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
2297 void pci_unlock_rescan_remove(void)
2299 mutex_unlock(&pci_rescan_remove_lock
);
2301 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
2303 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
2304 const struct device
*d_b
)
2306 const struct pci_dev
*a
= to_pci_dev(d_a
);
2307 const struct pci_dev
*b
= to_pci_dev(d_b
);
2309 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
2310 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
2312 if (a
->bus
->number
< b
->bus
->number
) return -1;
2313 else if (a
->bus
->number
> b
->bus
->number
) return 1;
2315 if (a
->devfn
< b
->devfn
) return -1;
2316 else if (a
->devfn
> b
->devfn
) return 1;
2321 void __init
pci_sort_breadthfirst(void)
2323 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);