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[PATCH] PCI: Avoid leaving MASTER_ABORT disabled permanently when returning from...
[deliverable/linux.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 #ifdef HAVE_PCI_LEGACY
26 /**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34 static void pci_create_legacy_files(struct pci_bus *b)
35 {
36 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
40 b->legacy_io->attr.name = "legacy_io";
41 b->legacy_io->size = 0xffff;
42 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
43 b->legacy_io->attr.owner = THIS_MODULE;
44 b->legacy_io->read = pci_read_legacy_io;
45 b->legacy_io->write = pci_write_legacy_io;
46 class_device_create_bin_file(&b->class_dev, b->legacy_io);
47
48 /* Allocated above after the legacy_io struct */
49 b->legacy_mem = b->legacy_io + 1;
50 b->legacy_mem->attr.name = "legacy_mem";
51 b->legacy_mem->size = 1024*1024;
52 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
53 b->legacy_mem->attr.owner = THIS_MODULE;
54 b->legacy_mem->mmap = pci_mmap_legacy_mem;
55 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
56 }
57 }
58
59 void pci_remove_legacy_files(struct pci_bus *b)
60 {
61 if (b->legacy_io) {
62 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
63 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
64 kfree(b->legacy_io); /* both are allocated here */
65 }
66 }
67 #else /* !HAVE_PCI_LEGACY */
68 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
69 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
70 #endif /* HAVE_PCI_LEGACY */
71
72 /*
73 * PCI Bus Class Devices
74 */
75 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
76 char *buf)
77 {
78 int ret;
79 cpumask_t cpumask;
80
81 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
82 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
83 if (ret < PAGE_SIZE)
84 buf[ret++] = '\n';
85 return ret;
86 }
87 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
88
89 /*
90 * PCI Bus Class
91 */
92 static void release_pcibus_dev(struct class_device *class_dev)
93 {
94 struct pci_bus *pci_bus = to_pci_bus(class_dev);
95
96 if (pci_bus->bridge)
97 put_device(pci_bus->bridge);
98 kfree(pci_bus);
99 }
100
101 static struct class pcibus_class = {
102 .name = "pci_bus",
103 .release = &release_pcibus_dev,
104 };
105
106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
112 /*
113 * Translate the low bits of the PCI base
114 * to the resource type
115 */
116 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
117 {
118 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
119 return IORESOURCE_IO;
120
121 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
122 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
123
124 return IORESOURCE_MEM;
125 }
126
127 /*
128 * Find the extent of a PCI decode..
129 */
130 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
131 {
132 u32 size = mask & maxbase; /* Find the significant bits */
133 if (!size)
134 return 0;
135
136 /* Get the lowest of them to find the decode size, and
137 from that the extent. */
138 size = (size & ~(size-1)) - 1;
139
140 /* base == maxbase can be valid only if the BAR has
141 already been programmed with all 1s. */
142 if (base == maxbase && ((base | size) & mask) != mask)
143 return 0;
144
145 return size;
146 }
147
148 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
149 {
150 unsigned int pos, reg, next;
151 u32 l, sz;
152 struct resource *res;
153
154 for(pos=0; pos<howmany; pos = next) {
155 next = pos+1;
156 res = &dev->resource[pos];
157 res->name = pci_name(dev);
158 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
159 pci_read_config_dword(dev, reg, &l);
160 pci_write_config_dword(dev, reg, ~0);
161 pci_read_config_dword(dev, reg, &sz);
162 pci_write_config_dword(dev, reg, l);
163 if (!sz || sz == 0xffffffff)
164 continue;
165 if (l == 0xffffffff)
166 l = 0;
167 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
168 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
169 if (!sz)
170 continue;
171 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
172 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
173 } else {
174 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
175 if (!sz)
176 continue;
177 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
178 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
179 }
180 res->end = res->start + (unsigned long) sz;
181 res->flags |= pci_calc_resource_flags(l);
182 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
183 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
184 pci_read_config_dword(dev, reg+4, &l);
185 next++;
186 #if BITS_PER_LONG == 64
187 res->start |= ((unsigned long) l) << 32;
188 res->end = res->start + sz;
189 pci_write_config_dword(dev, reg+4, ~0);
190 pci_read_config_dword(dev, reg+4, &sz);
191 pci_write_config_dword(dev, reg+4, l);
192 sz = pci_size(l, sz, 0xffffffff);
193 if (sz) {
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)sz<<32;
196 }
197 #else
198 if (l) {
199 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
200 res->start = 0;
201 res->flags = 0;
202 continue;
203 }
204 #endif
205 }
206 }
207 if (rom) {
208 dev->rom_base_reg = rom;
209 res = &dev->resource[PCI_ROM_RESOURCE];
210 res->name = pci_name(dev);
211 pci_read_config_dword(dev, rom, &l);
212 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
213 pci_read_config_dword(dev, rom, &sz);
214 pci_write_config_dword(dev, rom, l);
215 if (l == 0xffffffff)
216 l = 0;
217 if (sz && sz != 0xffffffff) {
218 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
219 if (sz) {
220 res->flags = (l & IORESOURCE_ROM_ENABLE) |
221 IORESOURCE_MEM | IORESOURCE_PREFETCH |
222 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
223 res->start = l & PCI_ROM_ADDRESS_MASK;
224 res->end = res->start + (unsigned long) sz;
225 }
226 }
227 }
228 }
229
230 void __devinit pci_read_bridge_bases(struct pci_bus *child)
231 {
232 struct pci_dev *dev = child->self;
233 u8 io_base_lo, io_limit_lo;
234 u16 mem_base_lo, mem_limit_lo;
235 unsigned long base, limit;
236 struct resource *res;
237 int i;
238
239 if (!dev) /* It's a host bus, nothing to read */
240 return;
241
242 if (dev->transparent) {
243 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
244 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
245 child->resource[i] = child->parent->resource[i - 3];
246 }
247
248 for(i=0; i<3; i++)
249 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
250
251 res = child->resource[0];
252 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
253 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
254 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
255 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
256
257 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
258 u16 io_base_hi, io_limit_hi;
259 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
260 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
261 base |= (io_base_hi << 16);
262 limit |= (io_limit_hi << 16);
263 }
264
265 if (base <= limit) {
266 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
267 if (!res->start)
268 res->start = base;
269 if (!res->end)
270 res->end = limit + 0xfff;
271 }
272
273 res = child->resource[1];
274 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
275 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
276 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
277 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
278 if (base <= limit) {
279 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
280 res->start = base;
281 res->end = limit + 0xfffff;
282 }
283
284 res = child->resource[2];
285 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
286 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
287 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
288 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
289
290 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
291 u32 mem_base_hi, mem_limit_hi;
292 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
293 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
294
295 /*
296 * Some bridges set the base > limit by default, and some
297 * (broken) BIOSes do not initialize them. If we find
298 * this, just assume they are not being used.
299 */
300 if (mem_base_hi <= mem_limit_hi) {
301 #if BITS_PER_LONG == 64
302 base |= ((long) mem_base_hi) << 32;
303 limit |= ((long) mem_limit_hi) << 32;
304 #else
305 if (mem_base_hi || mem_limit_hi) {
306 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
307 return;
308 }
309 #endif
310 }
311 }
312 if (base <= limit) {
313 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
314 res->start = base;
315 res->end = limit + 0xfffff;
316 }
317 }
318
319 static struct pci_bus * __devinit pci_alloc_bus(void)
320 {
321 struct pci_bus *b;
322
323 b = kmalloc(sizeof(*b), GFP_KERNEL);
324 if (b) {
325 memset(b, 0, sizeof(*b));
326 INIT_LIST_HEAD(&b->node);
327 INIT_LIST_HEAD(&b->children);
328 INIT_LIST_HEAD(&b->devices);
329 }
330 return b;
331 }
332
333 static struct pci_bus * __devinit
334 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
335 {
336 struct pci_bus *child;
337 int i;
338
339 /*
340 * Allocate a new bus, and inherit stuff from the parent..
341 */
342 child = pci_alloc_bus();
343 if (!child)
344 return NULL;
345
346 child->self = bridge;
347 child->parent = parent;
348 child->ops = parent->ops;
349 child->sysdata = parent->sysdata;
350 child->bridge = get_device(&bridge->dev);
351
352 child->class_dev.class = &pcibus_class;
353 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
354 class_device_register(&child->class_dev);
355 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
356
357 /*
358 * Set up the primary, secondary and subordinate
359 * bus numbers.
360 */
361 child->number = child->secondary = busnr;
362 child->primary = parent->secondary;
363 child->subordinate = 0xff;
364
365 /* Set up default resource pointers and names.. */
366 for (i = 0; i < 4; i++) {
367 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
368 child->resource[i]->name = child->name;
369 }
370 bridge->subordinate = child;
371
372 return child;
373 }
374
375 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
376 {
377 struct pci_bus *child;
378
379 child = pci_alloc_child_bus(parent, dev, busnr);
380 if (child) {
381 spin_lock(&pci_bus_lock);
382 list_add_tail(&child->node, &parent->children);
383 spin_unlock(&pci_bus_lock);
384 }
385 return child;
386 }
387
388 static void pci_enable_crs(struct pci_dev *dev)
389 {
390 u16 cap, rpctl;
391 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
392 if (!rpcap)
393 return;
394
395 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
396 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
397 return;
398
399 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
400 rpctl |= PCI_EXP_RTCTL_CRSSVE;
401 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
402 }
403
404 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
405 {
406 struct pci_bus *parent = child->parent;
407
408 /* Attempts to fix that up are really dangerous unless
409 we're going to re-assign all bus numbers. */
410 if (!pcibios_assign_all_busses())
411 return;
412
413 while (parent->parent && parent->subordinate < max) {
414 parent->subordinate = max;
415 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
416 parent = parent->parent;
417 }
418 }
419
420 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
421
422 /*
423 * If it's a bridge, configure it and scan the bus behind it.
424 * For CardBus bridges, we don't scan behind as the devices will
425 * be handled by the bridge driver itself.
426 *
427 * We need to process bridges in two passes -- first we scan those
428 * already configured by the BIOS and after we are done with all of
429 * them, we proceed to assigning numbers to the remaining buses in
430 * order to avoid overlaps between old and new bus numbers.
431 */
432 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
433 {
434 struct pci_bus *child;
435 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
436 u32 buses, i, j = 0;
437 u16 bctl;
438
439 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
440
441 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
442 pci_name(dev), buses & 0xffffff, pass);
443
444 /* Disable MasterAbortMode during probing to avoid reporting
445 of bus errors (in some architectures) */
446 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
447 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
448 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
449
450 pci_enable_crs(dev);
451
452 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
453 unsigned int cmax, busnr;
454 /*
455 * Bus already configured by firmware, process it in the first
456 * pass and just note the configuration.
457 */
458 if (pass)
459 goto out;
460 busnr = (buses >> 8) & 0xFF;
461
462 /*
463 * If we already got to this bus through a different bridge,
464 * ignore it. This can happen with the i450NX chipset.
465 */
466 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
467 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
468 pci_domain_nr(bus), busnr);
469 goto out;
470 }
471
472 child = pci_add_new_bus(bus, dev, busnr);
473 if (!child)
474 goto out;
475 child->primary = buses & 0xFF;
476 child->subordinate = (buses >> 16) & 0xFF;
477 child->bridge_ctl = bctl;
478
479 cmax = pci_scan_child_bus(child);
480 if (cmax > max)
481 max = cmax;
482 if (child->subordinate > max)
483 max = child->subordinate;
484 } else {
485 /*
486 * We need to assign a number to this bus which we always
487 * do in the second pass.
488 */
489 if (!pass) {
490 if (pcibios_assign_all_busses())
491 /* Temporarily disable forwarding of the
492 configuration cycles on all bridges in
493 this bus segment to avoid possible
494 conflicts in the second pass between two
495 bridges programmed with overlapping
496 bus ranges. */
497 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
498 buses & ~0xffffff);
499 goto out;
500 }
501
502 /* Clear errors */
503 pci_write_config_word(dev, PCI_STATUS, 0xffff);
504
505 /* Prevent assigning a bus number that already exists.
506 * This can happen when a bridge is hot-plugged */
507 if (pci_find_bus(pci_domain_nr(bus), max+1))
508 goto out;
509 child = pci_add_new_bus(bus, dev, ++max);
510 buses = (buses & 0xff000000)
511 | ((unsigned int)(child->primary) << 0)
512 | ((unsigned int)(child->secondary) << 8)
513 | ((unsigned int)(child->subordinate) << 16);
514
515 /*
516 * yenta.c forces a secondary latency timer of 176.
517 * Copy that behaviour here.
518 */
519 if (is_cardbus) {
520 buses &= ~0xff000000;
521 buses |= CARDBUS_LATENCY_TIMER << 24;
522 }
523
524 /*
525 * We need to blast all three values with a single write.
526 */
527 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
528
529 if (!is_cardbus) {
530 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
531 /*
532 * Adjust subordinate busnr in parent buses.
533 * We do this before scanning for children because
534 * some devices may not be detected if the bios
535 * was lazy.
536 */
537 pci_fixup_parent_subordinate_busnr(child, max);
538 /* Now we can scan all subordinate buses... */
539 max = pci_scan_child_bus(child);
540 /*
541 * now fix it up again since we have found
542 * the real value of max.
543 */
544 pci_fixup_parent_subordinate_busnr(child, max);
545 } else {
546 /*
547 * For CardBus bridges, we leave 4 bus numbers
548 * as cards with a PCI-to-PCI bridge can be
549 * inserted later.
550 */
551 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
552 struct pci_bus *parent = bus;
553 if (pci_find_bus(pci_domain_nr(bus),
554 max+i+1))
555 break;
556 while (parent->parent) {
557 if ((!pcibios_assign_all_busses()) &&
558 (parent->subordinate > max) &&
559 (parent->subordinate <= max+i)) {
560 j = 1;
561 }
562 parent = parent->parent;
563 }
564 if (j) {
565 /*
566 * Often, there are two cardbus bridges
567 * -- try to leave one valid bus number
568 * for each one.
569 */
570 i /= 2;
571 break;
572 }
573 }
574 max += i;
575 pci_fixup_parent_subordinate_busnr(child, max);
576 }
577 /*
578 * Set the subordinate bus number to its real value.
579 */
580 child->subordinate = max;
581 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
582 }
583
584 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
585
586 while (bus->parent) {
587 if ((child->subordinate > bus->subordinate) ||
588 (child->number > bus->subordinate) ||
589 (child->number < bus->number) ||
590 (child->subordinate < bus->number)) {
591 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) may be "
592 "hidden behind%s bridge #%02x (-#%02x)%s\n",
593 child->number, child->subordinate,
594 bus->self->transparent ? " transparent" : " ",
595 bus->number, bus->subordinate,
596 pcibios_assign_all_busses() ? " " :
597 " (try 'pci=assign-busses')");
598 }
599 bus = bus->parent;
600 }
601
602 out:
603 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
604
605 return max;
606 }
607
608 /*
609 * Read interrupt line and base address registers.
610 * The architecture-dependent code can tweak these, of course.
611 */
612 static void pci_read_irq(struct pci_dev *dev)
613 {
614 unsigned char irq;
615
616 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
617 dev->pin = irq;
618 if (irq)
619 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
620 dev->irq = irq;
621 }
622
623 /**
624 * pci_setup_device - fill in class and map information of a device
625 * @dev: the device structure to fill
626 *
627 * Initialize the device structure with information about the device's
628 * vendor,class,memory and IO-space addresses,IRQ lines etc.
629 * Called at initialisation of the PCI subsystem and by CardBus services.
630 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
631 * or CardBus).
632 */
633 static int pci_setup_device(struct pci_dev * dev)
634 {
635 u32 class;
636
637 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
638 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
639
640 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
641 class >>= 8; /* upper 3 bytes */
642 dev->class = class;
643 class >>= 8;
644
645 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
646 dev->vendor, dev->device, class, dev->hdr_type);
647
648 /* "Unknown power state" */
649 dev->current_state = PCI_UNKNOWN;
650
651 /* Early fixups, before probing the BARs */
652 pci_fixup_device(pci_fixup_early, dev);
653 class = dev->class >> 8;
654
655 switch (dev->hdr_type) { /* header type */
656 case PCI_HEADER_TYPE_NORMAL: /* standard header */
657 if (class == PCI_CLASS_BRIDGE_PCI)
658 goto bad;
659 pci_read_irq(dev);
660 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
661 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
662 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
663 break;
664
665 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
666 if (class != PCI_CLASS_BRIDGE_PCI)
667 goto bad;
668 /* The PCI-to-PCI bridge spec requires that subtractive
669 decoding (i.e. transparent) bridge must have programming
670 interface code of 0x01. */
671 pci_read_irq(dev);
672 dev->transparent = ((dev->class & 0xff) == 1);
673 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
674 break;
675
676 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
677 if (class != PCI_CLASS_BRIDGE_CARDBUS)
678 goto bad;
679 pci_read_irq(dev);
680 pci_read_bases(dev, 1, 0);
681 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
682 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
683 break;
684
685 default: /* unknown header */
686 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
687 pci_name(dev), dev->hdr_type);
688 return -1;
689
690 bad:
691 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
692 pci_name(dev), class, dev->hdr_type);
693 dev->class = PCI_CLASS_NOT_DEFINED;
694 }
695
696 /* We found a fine healthy device, go go go... */
697 return 0;
698 }
699
700 /**
701 * pci_release_dev - free a pci device structure when all users of it are finished.
702 * @dev: device that's been disconnected
703 *
704 * Will be called only by the device core when all users of this pci device are
705 * done.
706 */
707 static void pci_release_dev(struct device *dev)
708 {
709 struct pci_dev *pci_dev;
710
711 pci_dev = to_pci_dev(dev);
712 kfree(pci_dev);
713 }
714
715 /**
716 * pci_cfg_space_size - get the configuration space size of the PCI device.
717 * @dev: PCI device
718 *
719 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
720 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
721 * access it. Maybe we don't have a way to generate extended config space
722 * accesses, or the device is behind a reverse Express bridge. So we try
723 * reading the dword at 0x100 which must either be 0 or a valid extended
724 * capability header.
725 */
726 int pci_cfg_space_size(struct pci_dev *dev)
727 {
728 int pos;
729 u32 status;
730
731 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
732 if (!pos) {
733 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
734 if (!pos)
735 goto fail;
736
737 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
738 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
739 goto fail;
740 }
741
742 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
743 goto fail;
744 if (status == 0xffffffff)
745 goto fail;
746
747 return PCI_CFG_SPACE_EXP_SIZE;
748
749 fail:
750 return PCI_CFG_SPACE_SIZE;
751 }
752
753 static void pci_release_bus_bridge_dev(struct device *dev)
754 {
755 kfree(dev);
756 }
757
758 /*
759 * Read the config data for a PCI device, sanity-check it
760 * and fill in the dev structure...
761 */
762 static struct pci_dev * __devinit
763 pci_scan_device(struct pci_bus *bus, int devfn)
764 {
765 struct pci_dev *dev;
766 u32 l;
767 u8 hdr_type;
768 int delay = 1;
769
770 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
771 return NULL;
772
773 /* some broken boards return 0 or ~0 if a slot is empty: */
774 if (l == 0xffffffff || l == 0x00000000 ||
775 l == 0x0000ffff || l == 0xffff0000)
776 return NULL;
777
778 /* Configuration request Retry Status */
779 while (l == 0xffff0001) {
780 msleep(delay);
781 delay *= 2;
782 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
783 return NULL;
784 /* Card hasn't responded in 60 seconds? Must be stuck. */
785 if (delay > 60 * 1000) {
786 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
787 "responding\n", pci_domain_nr(bus),
788 bus->number, PCI_SLOT(devfn),
789 PCI_FUNC(devfn));
790 return NULL;
791 }
792 }
793
794 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
795 return NULL;
796
797 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
798 if (!dev)
799 return NULL;
800
801 memset(dev, 0, sizeof(struct pci_dev));
802 dev->bus = bus;
803 dev->sysdata = bus->sysdata;
804 dev->dev.parent = bus->bridge;
805 dev->dev.bus = &pci_bus_type;
806 dev->devfn = devfn;
807 dev->hdr_type = hdr_type & 0x7f;
808 dev->multifunction = !!(hdr_type & 0x80);
809 dev->vendor = l & 0xffff;
810 dev->device = (l >> 16) & 0xffff;
811 dev->cfg_size = pci_cfg_space_size(dev);
812
813 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
814 set this higher, assuming the system even supports it. */
815 dev->dma_mask = 0xffffffff;
816 if (pci_setup_device(dev) < 0) {
817 kfree(dev);
818 return NULL;
819 }
820
821 return dev;
822 }
823
824 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
825 {
826 device_initialize(&dev->dev);
827 dev->dev.release = pci_release_dev;
828 pci_dev_get(dev);
829
830 dev->dev.dma_mask = &dev->dma_mask;
831 dev->dev.coherent_dma_mask = 0xffffffffull;
832
833 /* Fix up broken headers */
834 pci_fixup_device(pci_fixup_header, dev);
835
836 /*
837 * Add the device to our list of discovered devices
838 * and the bus list for fixup functions, etc.
839 */
840 INIT_LIST_HEAD(&dev->global_list);
841 spin_lock(&pci_bus_lock);
842 list_add_tail(&dev->bus_list, &bus->devices);
843 spin_unlock(&pci_bus_lock);
844 }
845
846 struct pci_dev * __devinit
847 pci_scan_single_device(struct pci_bus *bus, int devfn)
848 {
849 struct pci_dev *dev;
850
851 dev = pci_scan_device(bus, devfn);
852 if (!dev)
853 return NULL;
854
855 pci_device_add(dev, bus);
856 pci_scan_msi_device(dev);
857
858 return dev;
859 }
860
861 /**
862 * pci_scan_slot - scan a PCI slot on a bus for devices.
863 * @bus: PCI bus to scan
864 * @devfn: slot number to scan (must have zero function.)
865 *
866 * Scan a PCI slot on the specified PCI bus for devices, adding
867 * discovered devices to the @bus->devices list. New devices
868 * will have an empty dev->global_list head.
869 */
870 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
871 {
872 int func, nr = 0;
873 int scan_all_fns;
874
875 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
876
877 for (func = 0; func < 8; func++, devfn++) {
878 struct pci_dev *dev;
879
880 dev = pci_scan_single_device(bus, devfn);
881 if (dev) {
882 nr++;
883
884 /*
885 * If this is a single function device,
886 * don't scan past the first function.
887 */
888 if (!dev->multifunction) {
889 if (func > 0) {
890 dev->multifunction = 1;
891 } else {
892 break;
893 }
894 }
895 } else {
896 if (func == 0 && !scan_all_fns)
897 break;
898 }
899 }
900 return nr;
901 }
902
903 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
904 {
905 unsigned int devfn, pass, max = bus->secondary;
906 struct pci_dev *dev;
907
908 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
909
910 /* Go find them, Rover! */
911 for (devfn = 0; devfn < 0x100; devfn += 8)
912 pci_scan_slot(bus, devfn);
913
914 /*
915 * After performing arch-dependent fixup of the bus, look behind
916 * all PCI-to-PCI bridges on this bus.
917 */
918 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
919 pcibios_fixup_bus(bus);
920 for (pass=0; pass < 2; pass++)
921 list_for_each_entry(dev, &bus->devices, bus_list) {
922 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
923 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
924 max = pci_scan_bridge(bus, dev, max, pass);
925 }
926
927 /*
928 * We've scanned the bus and so we know all about what's on
929 * the other side of any bridges that may be on this bus plus
930 * any devices.
931 *
932 * Return how far we've got finding sub-buses.
933 */
934 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
935 pci_domain_nr(bus), bus->number, max);
936 return max;
937 }
938
939 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
940 {
941 unsigned int max;
942
943 max = pci_scan_child_bus(bus);
944
945 /*
946 * Make the discovered devices available.
947 */
948 pci_bus_add_devices(bus);
949
950 return max;
951 }
952
953 struct pci_bus * __devinit pci_create_bus(struct device *parent,
954 int bus, struct pci_ops *ops, void *sysdata)
955 {
956 int error;
957 struct pci_bus *b;
958 struct device *dev;
959
960 b = pci_alloc_bus();
961 if (!b)
962 return NULL;
963
964 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
965 if (!dev){
966 kfree(b);
967 return NULL;
968 }
969
970 b->sysdata = sysdata;
971 b->ops = ops;
972
973 if (pci_find_bus(pci_domain_nr(b), bus)) {
974 /* If we already got to this bus through a different bridge, ignore it */
975 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
976 goto err_out;
977 }
978 spin_lock(&pci_bus_lock);
979 list_add_tail(&b->node, &pci_root_buses);
980 spin_unlock(&pci_bus_lock);
981
982 memset(dev, 0, sizeof(*dev));
983 dev->parent = parent;
984 dev->release = pci_release_bus_bridge_dev;
985 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
986 error = device_register(dev);
987 if (error)
988 goto dev_reg_err;
989 b->bridge = get_device(dev);
990
991 b->class_dev.class = &pcibus_class;
992 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
993 error = class_device_register(&b->class_dev);
994 if (error)
995 goto class_dev_reg_err;
996 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
997 if (error)
998 goto class_dev_create_file_err;
999
1000 /* Create legacy_io and legacy_mem files for this bus */
1001 pci_create_legacy_files(b);
1002
1003 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1004 if (error)
1005 goto sys_create_link_err;
1006
1007 b->number = b->secondary = bus;
1008 b->resource[0] = &ioport_resource;
1009 b->resource[1] = &iomem_resource;
1010
1011 return b;
1012
1013 sys_create_link_err:
1014 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1015 class_dev_create_file_err:
1016 class_device_unregister(&b->class_dev);
1017 class_dev_reg_err:
1018 device_unregister(dev);
1019 dev_reg_err:
1020 spin_lock(&pci_bus_lock);
1021 list_del(&b->node);
1022 spin_unlock(&pci_bus_lock);
1023 err_out:
1024 kfree(dev);
1025 kfree(b);
1026 return NULL;
1027 }
1028 EXPORT_SYMBOL_GPL(pci_create_bus);
1029
1030 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1031 int bus, struct pci_ops *ops, void *sysdata)
1032 {
1033 struct pci_bus *b;
1034
1035 b = pci_create_bus(parent, bus, ops, sysdata);
1036 if (b)
1037 b->subordinate = pci_scan_child_bus(b);
1038 return b;
1039 }
1040 EXPORT_SYMBOL(pci_scan_bus_parented);
1041
1042 #ifdef CONFIG_HOTPLUG
1043 EXPORT_SYMBOL(pci_add_new_bus);
1044 EXPORT_SYMBOL(pci_do_scan_bus);
1045 EXPORT_SYMBOL(pci_scan_slot);
1046 EXPORT_SYMBOL(pci_scan_bridge);
1047 EXPORT_SYMBOL(pci_scan_single_device);
1048 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1049 #endif
Linux kernel - Deliverables
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