2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
24 static struct resource busn_resource
= {
28 .flags
= IORESOURCE_BUS
,
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses
);
33 EXPORT_SYMBOL(pci_root_buses
);
35 static LIST_HEAD(pci_domain_busn_res_list
);
37 struct pci_domain_busn_res
{
38 struct list_head list
;
43 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
45 struct pci_domain_busn_res
*r
;
47 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
48 if (r
->domain_nr
== domain_nr
)
51 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
55 r
->domain_nr
= domain_nr
;
58 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
60 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
65 static int find_anything(struct device
*dev
, void *data
)
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
75 int no_pci_devices(void)
80 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
81 no_devices
= (dev
== NULL
);
85 EXPORT_SYMBOL(no_pci_devices
);
90 static void release_pcibus_dev(struct device
*dev
)
92 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
94 put_device(pci_bus
->bridge
);
95 pci_bus_remove_resources(pci_bus
);
96 pci_release_bus_of_node(pci_bus
);
100 static struct class pcibus_class
= {
102 .dev_release
= &release_pcibus_dev
,
103 .dev_groups
= pcibus_groups
,
106 static int __init
pcibus_class_init(void)
108 return class_register(&pcibus_class
);
110 postcore_initcall(pcibus_class_init
);
112 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
114 u64 size
= mask
& maxbase
; /* Find the significant bits */
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size
= (size
& ~(size
-1)) - 1;
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
130 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
135 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
136 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
137 flags
|= IORESOURCE_IO
;
141 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
142 flags
|= IORESOURCE_MEM
;
143 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
144 flags
|= IORESOURCE_PREFETCH
;
146 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
148 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
151 /* 1M mem BAR treated as 32-bit BAR */
153 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
154 flags
|= IORESOURCE_MEM_64
;
157 /* mem unknown type treated as 32-bit BAR */
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
175 struct resource
*res
, unsigned int pos
)
178 u64 l64
, sz64
, mask64
;
180 struct pci_bus_region region
, inverted_region
;
182 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
184 /* No printks while decoding is disabled! */
185 if (!dev
->mmio_always_on
) {
186 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
187 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
188 pci_write_config_word(dev
, PCI_COMMAND
,
189 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
193 res
->name
= pci_name(dev
);
195 pci_read_config_dword(dev
, pos
, &l
);
196 pci_write_config_dword(dev
, pos
, l
| mask
);
197 pci_read_config_dword(dev
, pos
, &sz
);
198 pci_write_config_dword(dev
, pos
, l
);
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
206 if (sz
== 0xffffffff)
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
216 if (type
== pci_bar_unknown
) {
217 res
->flags
= decode_bar(dev
, l
);
218 res
->flags
|= IORESOURCE_SIZEALIGN
;
219 if (res
->flags
& IORESOURCE_IO
) {
220 l64
= l
& PCI_BASE_ADDRESS_IO_MASK
;
221 sz64
= sz
& PCI_BASE_ADDRESS_IO_MASK
;
222 mask64
= PCI_BASE_ADDRESS_IO_MASK
& (u32
)IO_SPACE_LIMIT
;
224 l64
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
225 sz64
= sz
& PCI_BASE_ADDRESS_MEM_MASK
;
226 mask64
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
229 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
230 l64
= l
& PCI_ROM_ADDRESS_MASK
;
231 sz64
= sz
& PCI_ROM_ADDRESS_MASK
;
232 mask64
= (u32
)PCI_ROM_ADDRESS_MASK
;
235 if (res
->flags
& IORESOURCE_MEM_64
) {
236 pci_read_config_dword(dev
, pos
+ 4, &l
);
237 pci_write_config_dword(dev
, pos
+ 4, ~0);
238 pci_read_config_dword(dev
, pos
+ 4, &sz
);
239 pci_write_config_dword(dev
, pos
+ 4, l
);
241 l64
|= ((u64
)l
<< 32);
242 sz64
|= ((u64
)sz
<< 32);
243 mask64
|= ((u64
)~0 << 32);
246 if (!dev
->mmio_always_on
&& (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
247 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
252 sz64
= pci_size(l64
, sz64
, mask64
);
254 dev_info(&dev
->dev
, FW_BUG
"reg 0x%x: invalid BAR (can't size)\n",
259 if (res
->flags
& IORESOURCE_MEM_64
) {
260 if ((sizeof(pci_bus_addr_t
) < 8 || sizeof(resource_size_t
) < 8)
261 && sz64
> 0x100000000ULL
) {
262 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
265 dev_err(&dev
->dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos
, (unsigned long long)sz64
);
270 if ((sizeof(pci_bus_addr_t
) < 8) && l
) {
271 /* Above 32-bit boundary; try to reallocate */
272 res
->flags
|= IORESOURCE_UNSET
;
275 dev_info(&dev
->dev
, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos
, (unsigned long long)l64
);
282 region
.end
= l64
+ sz64
;
284 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
285 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
293 * resource_to_bus(bus_to_resource(A)) == A
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
298 if (inverted_region
.start
!= region
.start
) {
299 res
->flags
|= IORESOURCE_UNSET
;
301 res
->end
= region
.end
- region
.start
;
302 dev_info(&dev
->dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos
, (unsigned long long)region
.start
);
313 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg 0x%x: %pR\n", pos
, res
);
315 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
318 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
320 unsigned int pos
, reg
;
322 for (pos
= 0; pos
< howmany
; pos
++) {
323 struct resource
*res
= &dev
->resource
[pos
];
324 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
325 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
329 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
330 dev
->rom_base_reg
= rom
;
331 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
332 IORESOURCE_READONLY
| IORESOURCE_SIZEALIGN
;
333 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
337 static void pci_read_bridge_io(struct pci_bus
*child
)
339 struct pci_dev
*dev
= child
->self
;
340 u8 io_base_lo
, io_limit_lo
;
341 unsigned long io_mask
, io_granularity
, base
, limit
;
342 struct pci_bus_region region
;
343 struct resource
*res
;
345 io_mask
= PCI_IO_RANGE_MASK
;
346 io_granularity
= 0x1000;
347 if (dev
->io_window_1k
) {
348 /* Support 1K I/O space granularity */
349 io_mask
= PCI_IO_1K_RANGE_MASK
;
350 io_granularity
= 0x400;
353 res
= child
->resource
[0];
354 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
355 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
356 base
= (io_base_lo
& io_mask
) << 8;
357 limit
= (io_limit_lo
& io_mask
) << 8;
359 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
360 u16 io_base_hi
, io_limit_hi
;
362 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
363 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
364 base
|= ((unsigned long) io_base_hi
<< 16);
365 limit
|= ((unsigned long) io_limit_hi
<< 16);
369 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
371 region
.end
= limit
+ io_granularity
- 1;
372 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
373 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
377 static void pci_read_bridge_mmio(struct pci_bus
*child
)
379 struct pci_dev
*dev
= child
->self
;
380 u16 mem_base_lo
, mem_limit_lo
;
381 unsigned long base
, limit
;
382 struct pci_bus_region region
;
383 struct resource
*res
;
385 res
= child
->resource
[1];
386 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
387 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
388 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
389 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
391 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
393 region
.end
= limit
+ 0xfffff;
394 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
395 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
399 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
401 struct pci_dev
*dev
= child
->self
;
402 u16 mem_base_lo
, mem_limit_lo
;
404 pci_bus_addr_t base
, limit
;
405 struct pci_bus_region region
;
406 struct resource
*res
;
408 res
= child
->resource
[2];
409 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
410 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
411 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
412 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
414 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
415 u32 mem_base_hi
, mem_limit_hi
;
417 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
418 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
421 * Some bridges set the base > limit by default, and some
422 * (broken) BIOSes do not initialize them. If we find
423 * this, just assume they are not being used.
425 if (mem_base_hi
<= mem_limit_hi
) {
426 base64
|= (u64
) mem_base_hi
<< 32;
427 limit64
|= (u64
) mem_limit_hi
<< 32;
431 base
= (pci_bus_addr_t
) base64
;
432 limit
= (pci_bus_addr_t
) limit64
;
434 if (base
!= base64
) {
435 dev_err(&dev
->dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
436 (unsigned long long) base64
);
441 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
442 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
443 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
444 res
->flags
|= IORESOURCE_MEM_64
;
446 region
.end
= limit
+ 0xfffff;
447 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
448 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
452 void pci_read_bridge_bases(struct pci_bus
*child
)
454 struct pci_dev
*dev
= child
->self
;
455 struct resource
*res
;
458 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
461 dev_info(&dev
->dev
, "PCI bridge to %pR%s\n",
463 dev
->transparent
? " (subtractive decode)" : "");
465 pci_bus_remove_resources(child
);
466 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
467 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
469 pci_read_bridge_io(child
);
470 pci_read_bridge_mmio(child
);
471 pci_read_bridge_mmio_pref(child
);
473 if (dev
->transparent
) {
474 pci_bus_for_each_resource(child
->parent
, res
, i
) {
475 if (res
&& res
->flags
) {
476 pci_bus_add_resource(child
, res
,
477 PCI_SUBTRACTIVE_DECODE
);
478 dev_printk(KERN_DEBUG
, &dev
->dev
,
479 " bridge window %pR (subtractive decode)\n",
486 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
490 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
494 INIT_LIST_HEAD(&b
->node
);
495 INIT_LIST_HEAD(&b
->children
);
496 INIT_LIST_HEAD(&b
->devices
);
497 INIT_LIST_HEAD(&b
->slots
);
498 INIT_LIST_HEAD(&b
->resources
);
499 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
500 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
501 #ifdef CONFIG_PCI_DOMAINS_GENERIC
503 b
->domain_nr
= parent
->domain_nr
;
508 static void pci_release_host_bridge_dev(struct device
*dev
)
510 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
512 if (bridge
->release_fn
)
513 bridge
->release_fn(bridge
);
515 pci_free_resource_list(&bridge
->windows
);
520 static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus
*b
)
522 struct pci_host_bridge
*bridge
;
524 bridge
= kzalloc(sizeof(*bridge
), GFP_KERNEL
);
528 INIT_LIST_HEAD(&bridge
->windows
);
533 static const unsigned char pcix_bus_speed
[] = {
534 PCI_SPEED_UNKNOWN
, /* 0 */
535 PCI_SPEED_66MHz_PCIX
, /* 1 */
536 PCI_SPEED_100MHz_PCIX
, /* 2 */
537 PCI_SPEED_133MHz_PCIX
, /* 3 */
538 PCI_SPEED_UNKNOWN
, /* 4 */
539 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
540 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
541 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
542 PCI_SPEED_UNKNOWN
, /* 8 */
543 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
544 PCI_SPEED_100MHz_PCIX_266
, /* A */
545 PCI_SPEED_133MHz_PCIX_266
, /* B */
546 PCI_SPEED_UNKNOWN
, /* C */
547 PCI_SPEED_66MHz_PCIX_533
, /* D */
548 PCI_SPEED_100MHz_PCIX_533
, /* E */
549 PCI_SPEED_133MHz_PCIX_533
/* F */
552 const unsigned char pcie_link_speed
[] = {
553 PCI_SPEED_UNKNOWN
, /* 0 */
554 PCIE_SPEED_2_5GT
, /* 1 */
555 PCIE_SPEED_5_0GT
, /* 2 */
556 PCIE_SPEED_8_0GT
, /* 3 */
557 PCI_SPEED_UNKNOWN
, /* 4 */
558 PCI_SPEED_UNKNOWN
, /* 5 */
559 PCI_SPEED_UNKNOWN
, /* 6 */
560 PCI_SPEED_UNKNOWN
, /* 7 */
561 PCI_SPEED_UNKNOWN
, /* 8 */
562 PCI_SPEED_UNKNOWN
, /* 9 */
563 PCI_SPEED_UNKNOWN
, /* A */
564 PCI_SPEED_UNKNOWN
, /* B */
565 PCI_SPEED_UNKNOWN
, /* C */
566 PCI_SPEED_UNKNOWN
, /* D */
567 PCI_SPEED_UNKNOWN
, /* E */
568 PCI_SPEED_UNKNOWN
/* F */
571 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
573 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
575 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
577 static unsigned char agp_speeds
[] = {
585 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
591 else if (agpstat
& 2)
593 else if (agpstat
& 1)
605 return agp_speeds
[index
];
608 static void pci_set_bus_speed(struct pci_bus
*bus
)
610 struct pci_dev
*bridge
= bus
->self
;
613 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
615 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
619 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
620 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
622 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
623 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
626 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
629 enum pci_bus_speed max
;
631 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
634 if (status
& PCI_X_SSTATUS_533MHZ
) {
635 max
= PCI_SPEED_133MHz_PCIX_533
;
636 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
637 max
= PCI_SPEED_133MHz_PCIX_266
;
638 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
639 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
640 max
= PCI_SPEED_133MHz_PCIX_ECC
;
642 max
= PCI_SPEED_133MHz_PCIX
;
644 max
= PCI_SPEED_66MHz_PCIX
;
647 bus
->max_bus_speed
= max
;
648 bus
->cur_bus_speed
= pcix_bus_speed
[
649 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
654 if (pci_is_pcie(bridge
)) {
658 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
659 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
661 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
662 pcie_update_link_speed(bus
, linksta
);
666 static struct irq_domain
*pci_host_bridge_msi_domain(struct pci_bus
*bus
)
668 struct irq_domain
*d
;
671 * Any firmware interface that can resolve the msi_domain
672 * should be called from here.
674 d
= pci_host_bridge_of_msi_domain(bus
);
676 d
= pci_host_bridge_acpi_msi_domain(bus
);
681 static void pci_set_bus_msi_domain(struct pci_bus
*bus
)
683 struct irq_domain
*d
;
687 * The bus can be a root bus, a subordinate bus, or a virtual bus
688 * created by an SR-IOV device. Walk up to the first bridge device
689 * found or derive the domain from the host bridge.
691 for (b
= bus
, d
= NULL
; !d
&& !pci_is_root_bus(b
); b
= b
->parent
) {
693 d
= dev_get_msi_domain(&b
->self
->dev
);
697 d
= pci_host_bridge_msi_domain(b
);
699 dev_set_msi_domain(&bus
->dev
, d
);
702 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
703 struct pci_dev
*bridge
, int busnr
)
705 struct pci_bus
*child
;
710 * Allocate a new bus, and inherit stuff from the parent..
712 child
= pci_alloc_bus(parent
);
716 child
->parent
= parent
;
717 child
->ops
= parent
->ops
;
718 child
->msi
= parent
->msi
;
719 child
->sysdata
= parent
->sysdata
;
720 child
->bus_flags
= parent
->bus_flags
;
722 /* initialize some portions of the bus device, but don't register it
723 * now as the parent is not properly set up yet.
725 child
->dev
.class = &pcibus_class
;
726 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
729 * Set up the primary, secondary and subordinate
732 child
->number
= child
->busn_res
.start
= busnr
;
733 child
->primary
= parent
->busn_res
.start
;
734 child
->busn_res
.end
= 0xff;
737 child
->dev
.parent
= parent
->bridge
;
741 child
->self
= bridge
;
742 child
->bridge
= get_device(&bridge
->dev
);
743 child
->dev
.parent
= child
->bridge
;
744 pci_set_bus_of_node(child
);
745 pci_set_bus_speed(child
);
747 /* Set up default resource pointers and names.. */
748 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
749 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
750 child
->resource
[i
]->name
= child
->name
;
752 bridge
->subordinate
= child
;
755 pci_set_bus_msi_domain(child
);
756 ret
= device_register(&child
->dev
);
759 pcibios_add_bus(child
);
761 /* Create legacy_io and legacy_mem files for this bus */
762 pci_create_legacy_files(child
);
767 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
770 struct pci_bus
*child
;
772 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
774 down_write(&pci_bus_sem
);
775 list_add_tail(&child
->node
, &parent
->children
);
776 up_write(&pci_bus_sem
);
780 EXPORT_SYMBOL(pci_add_new_bus
);
782 static void pci_enable_crs(struct pci_dev
*pdev
)
786 /* Enable CRS Software Visibility if supported */
787 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
788 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
789 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
790 PCI_EXP_RTCTL_CRSSVE
);
794 * If it's a bridge, configure it and scan the bus behind it.
795 * For CardBus bridges, we don't scan behind as the devices will
796 * be handled by the bridge driver itself.
798 * We need to process bridges in two passes -- first we scan those
799 * already configured by the BIOS and after we are done with all of
800 * them, we proceed to assigning numbers to the remaining buses in
801 * order to avoid overlaps between old and new bus numbers.
803 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
805 struct pci_bus
*child
;
806 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
809 u8 primary
, secondary
, subordinate
;
812 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
813 primary
= buses
& 0xFF;
814 secondary
= (buses
>> 8) & 0xFF;
815 subordinate
= (buses
>> 16) & 0xFF;
817 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
818 secondary
, subordinate
, pass
);
820 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
821 dev_warn(&dev
->dev
, "Primary bus is hard wired to 0\n");
822 primary
= bus
->number
;
825 /* Check if setup is sensible at all */
827 (primary
!= bus
->number
|| secondary
<= bus
->number
||
828 secondary
> subordinate
)) {
829 dev_info(&dev
->dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
830 secondary
, subordinate
);
834 /* Disable MasterAbortMode during probing to avoid reporting
835 of bus errors (in some architectures) */
836 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
837 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
838 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
842 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
843 !is_cardbus
&& !broken
) {
846 * Bus already configured by firmware, process it in the first
847 * pass and just note the configuration.
853 * The bus might already exist for two reasons: Either we are
854 * rescanning the bus or the bus is reachable through more than
855 * one bridge. The second case can happen with the i450NX
858 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
860 child
= pci_add_new_bus(bus
, dev
, secondary
);
863 child
->primary
= primary
;
864 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
865 child
->bridge_ctl
= bctl
;
868 cmax
= pci_scan_child_bus(child
);
869 if (cmax
> subordinate
)
870 dev_warn(&dev
->dev
, "bridge has subordinate %02x but max busn %02x\n",
872 /* subordinate should equal child->busn_res.end */
873 if (subordinate
> max
)
877 * We need to assign a number to this bus which we always
878 * do in the second pass.
881 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
882 /* Temporarily disable forwarding of the
883 configuration cycles on all bridges in
884 this bus segment to avoid possible
885 conflicts in the second pass between two
886 bridges programmed with overlapping
888 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
894 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
896 /* Prevent assigning a bus number that already exists.
897 * This can happen when a bridge is hot-plugged, so in
898 * this case we only re-scan this bus. */
899 child
= pci_find_bus(pci_domain_nr(bus
), max
+1);
901 child
= pci_add_new_bus(bus
, dev
, max
+1);
904 pci_bus_insert_busn_res(child
, max
+1, 0xff);
907 buses
= (buses
& 0xff000000)
908 | ((unsigned int)(child
->primary
) << 0)
909 | ((unsigned int)(child
->busn_res
.start
) << 8)
910 | ((unsigned int)(child
->busn_res
.end
) << 16);
913 * yenta.c forces a secondary latency timer of 176.
914 * Copy that behaviour here.
917 buses
&= ~0xff000000;
918 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
922 * We need to blast all three values with a single write.
924 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
927 child
->bridge_ctl
= bctl
;
928 max
= pci_scan_child_bus(child
);
931 * For CardBus bridges, we leave 4 bus numbers
932 * as cards with a PCI-to-PCI bridge can be
935 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
936 struct pci_bus
*parent
= bus
;
937 if (pci_find_bus(pci_domain_nr(bus
),
940 while (parent
->parent
) {
941 if ((!pcibios_assign_all_busses()) &&
942 (parent
->busn_res
.end
> max
) &&
943 (parent
->busn_res
.end
<= max
+i
)) {
946 parent
= parent
->parent
;
950 * Often, there are two cardbus bridges
951 * -- try to leave one valid bus number
961 * Set the subordinate bus number to its real value.
963 pci_bus_update_busn_res_end(child
, max
);
964 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
968 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
969 pci_domain_nr(bus
), child
->number
);
971 /* Has only triggered on CardBus, fixup is in yenta_socket */
972 while (bus
->parent
) {
973 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
974 (child
->number
> bus
->busn_res
.end
) ||
975 (child
->number
< bus
->number
) ||
976 (child
->busn_res
.end
< bus
->number
)) {
977 dev_info(&child
->dev
, "%pR %s hidden behind%s bridge %s %pR\n",
979 (bus
->number
> child
->busn_res
.end
&&
980 bus
->busn_res
.end
< child
->number
) ?
981 "wholly" : "partially",
982 bus
->self
->transparent
? " transparent" : "",
990 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
994 EXPORT_SYMBOL(pci_scan_bridge
);
997 * Read interrupt line and base address registers.
998 * The architecture-dependent code can tweak these, of course.
1000 static void pci_read_irq(struct pci_dev
*dev
)
1004 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
1007 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1011 void set_pcie_port_type(struct pci_dev
*pdev
)
1016 struct pci_dev
*parent
;
1018 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1021 pdev
->pcie_cap
= pos
;
1022 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
1023 pdev
->pcie_flags_reg
= reg16
;
1024 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
1025 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
1028 * A Root Port is always the upstream end of a Link. No PCIe
1029 * component has two Links. Two Links are connected by a Switch
1030 * that has a Port on each Link and internal logic to connect the
1033 type
= pci_pcie_type(pdev
);
1034 if (type
== PCI_EXP_TYPE_ROOT_PORT
)
1035 pdev
->has_secondary_link
= 1;
1036 else if (type
== PCI_EXP_TYPE_UPSTREAM
||
1037 type
== PCI_EXP_TYPE_DOWNSTREAM
) {
1038 parent
= pci_upstream_bridge(pdev
);
1041 * Usually there's an upstream device (Root Port or Switch
1042 * Downstream Port), but we can't assume one exists.
1044 if (parent
&& !parent
->has_secondary_link
)
1045 pdev
->has_secondary_link
= 1;
1049 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1053 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1054 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1055 pdev
->is_hotplug_bridge
= 1;
1059 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1062 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1063 * when forwarding a type1 configuration request the bridge must check that
1064 * the extended register address field is zero. The bridge is not permitted
1065 * to forward the transactions and must handle it as an Unsupported Request.
1066 * Some bridges do not follow this rule and simply drop the extended register
1067 * bits, resulting in the standard config space being aliased, every 256
1068 * bytes across the entire configuration space. Test for this condition by
1069 * comparing the first dword of each potential alias to the vendor/device ID.
1071 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1072 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1074 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1076 #ifdef CONFIG_PCI_QUIRKS
1080 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1082 for (pos
= PCI_CFG_SPACE_SIZE
;
1083 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1084 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1096 * pci_cfg_space_size - get the configuration space size of the PCI device.
1099 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1100 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1101 * access it. Maybe we don't have a way to generate extended config space
1102 * accesses, or the device is behind a reverse Express bridge. So we try
1103 * reading the dword at 0x100 which must either be 0 or a valid extended
1104 * capability header.
1106 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1109 int pos
= PCI_CFG_SPACE_SIZE
;
1111 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1112 return PCI_CFG_SPACE_SIZE
;
1113 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1114 return PCI_CFG_SPACE_SIZE
;
1116 return PCI_CFG_SPACE_EXP_SIZE
;
1119 int pci_cfg_space_size(struct pci_dev
*dev
)
1125 class = dev
->class >> 8;
1126 if (class == PCI_CLASS_BRIDGE_HOST
)
1127 return pci_cfg_space_size_ext(dev
);
1129 if (pci_is_pcie(dev
))
1130 return pci_cfg_space_size_ext(dev
);
1132 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1134 return PCI_CFG_SPACE_SIZE
;
1136 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1137 if (status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
))
1138 return pci_cfg_space_size_ext(dev
);
1140 return PCI_CFG_SPACE_SIZE
;
1143 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1145 static void pci_msi_setup_pci_dev(struct pci_dev
*dev
)
1148 * Disable the MSI hardware to avoid screaming interrupts
1149 * during boot. This is the power on reset default so
1150 * usually this should be a noop.
1152 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1154 pci_msi_set_enable(dev
, 0);
1156 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1158 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1162 * pci_setup_device - fill in class and map information of a device
1163 * @dev: the device structure to fill
1165 * Initialize the device structure with information about the device's
1166 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1167 * Called at initialisation of the PCI subsystem and by CardBus services.
1168 * Returns 0 on success and negative if unknown type of device (not normal,
1169 * bridge or CardBus).
1171 int pci_setup_device(struct pci_dev
*dev
)
1176 struct pci_bus_region region
;
1177 struct resource
*res
;
1179 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
1182 dev
->sysdata
= dev
->bus
->sysdata
;
1183 dev
->dev
.parent
= dev
->bus
->bridge
;
1184 dev
->dev
.bus
= &pci_bus_type
;
1185 dev
->hdr_type
= hdr_type
& 0x7f;
1186 dev
->multifunction
= !!(hdr_type
& 0x80);
1187 dev
->error_state
= pci_channel_io_normal
;
1188 set_pcie_port_type(dev
);
1190 pci_dev_assign_slot(dev
);
1191 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1192 set this higher, assuming the system even supports it. */
1193 dev
->dma_mask
= 0xffffffff;
1195 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1196 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1197 PCI_FUNC(dev
->devfn
));
1199 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1200 dev
->revision
= class & 0xff;
1201 dev
->class = class >> 8; /* upper 3 bytes */
1203 dev_printk(KERN_DEBUG
, &dev
->dev
, "[%04x:%04x] type %02x class %#08x\n",
1204 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1206 /* need to have dev->class ready */
1207 dev
->cfg_size
= pci_cfg_space_size(dev
);
1209 /* "Unknown power state" */
1210 dev
->current_state
= PCI_UNKNOWN
;
1212 /* Early fixups, before probing the BARs */
1213 pci_fixup_device(pci_fixup_early
, dev
);
1214 /* device class may be changed after fixup */
1215 class = dev
->class >> 8;
1217 switch (dev
->hdr_type
) { /* header type */
1218 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1219 if (class == PCI_CLASS_BRIDGE_PCI
)
1222 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1223 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1224 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1227 * Do the ugly legacy mode stuff here rather than broken chip
1228 * quirk code. Legacy mode ATA controllers have fixed
1229 * addresses. These are not always echoed in BAR0-3, and
1230 * BAR0-3 in a few cases contain junk!
1232 if (class == PCI_CLASS_STORAGE_IDE
) {
1234 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1235 if ((progif
& 1) == 0) {
1236 region
.start
= 0x1F0;
1238 res
= &dev
->resource
[0];
1239 res
->flags
= LEGACY_IO_RESOURCE
;
1240 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1241 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1243 region
.start
= 0x3F6;
1245 res
= &dev
->resource
[1];
1246 res
->flags
= LEGACY_IO_RESOURCE
;
1247 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1248 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1251 if ((progif
& 4) == 0) {
1252 region
.start
= 0x170;
1254 res
= &dev
->resource
[2];
1255 res
->flags
= LEGACY_IO_RESOURCE
;
1256 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1257 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1259 region
.start
= 0x376;
1261 res
= &dev
->resource
[3];
1262 res
->flags
= LEGACY_IO_RESOURCE
;
1263 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1264 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1270 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1271 if (class != PCI_CLASS_BRIDGE_PCI
)
1273 /* The PCI-to-PCI bridge spec requires that subtractive
1274 decoding (i.e. transparent) bridge must have programming
1275 interface code of 0x01. */
1277 dev
->transparent
= ((dev
->class & 0xff) == 1);
1278 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1279 set_pcie_hotplug_bridge(dev
);
1280 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1282 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1283 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1287 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1288 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1291 pci_read_bases(dev
, 1, 0);
1292 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1293 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1296 default: /* unknown header */
1297 dev_err(&dev
->dev
, "unknown header type %02x, ignoring device\n",
1302 dev_err(&dev
->dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
1303 dev
->class, dev
->hdr_type
);
1304 dev
->class = PCI_CLASS_NOT_DEFINED
<< 8;
1307 /* We found a fine healthy device, go go go... */
1311 static void pci_configure_mps(struct pci_dev
*dev
)
1313 struct pci_dev
*bridge
= pci_upstream_bridge(dev
);
1316 if (!pci_is_pcie(dev
) || !bridge
|| !pci_is_pcie(bridge
))
1319 mps
= pcie_get_mps(dev
);
1320 p_mps
= pcie_get_mps(bridge
);
1325 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
1326 dev_warn(&dev
->dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1327 mps
, pci_name(bridge
), p_mps
);
1332 * Fancier MPS configuration is done later by
1333 * pcie_bus_configure_settings()
1335 if (pcie_bus_config
!= PCIE_BUS_DEFAULT
)
1338 rc
= pcie_set_mps(dev
, p_mps
);
1340 dev_warn(&dev
->dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1345 dev_info(&dev
->dev
, "Max Payload Size set to %d (was %d, max %d)\n",
1346 p_mps
, mps
, 128 << dev
->pcie_mpss
);
1349 static struct hpp_type0 pci_default_type0
= {
1351 .cache_line_size
= 8,
1352 .latency_timer
= 0x40,
1357 static void program_hpp_type0(struct pci_dev
*dev
, struct hpp_type0
*hpp
)
1359 u16 pci_cmd
, pci_bctl
;
1362 hpp
= &pci_default_type0
;
1364 if (hpp
->revision
> 1) {
1366 "PCI settings rev %d not supported; using defaults\n",
1368 hpp
= &pci_default_type0
;
1371 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, hpp
->cache_line_size
);
1372 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, hpp
->latency_timer
);
1373 pci_read_config_word(dev
, PCI_COMMAND
, &pci_cmd
);
1374 if (hpp
->enable_serr
)
1375 pci_cmd
|= PCI_COMMAND_SERR
;
1376 if (hpp
->enable_perr
)
1377 pci_cmd
|= PCI_COMMAND_PARITY
;
1378 pci_write_config_word(dev
, PCI_COMMAND
, pci_cmd
);
1380 /* Program bridge control value */
1381 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1382 pci_write_config_byte(dev
, PCI_SEC_LATENCY_TIMER
,
1383 hpp
->latency_timer
);
1384 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &pci_bctl
);
1385 if (hpp
->enable_serr
)
1386 pci_bctl
|= PCI_BRIDGE_CTL_SERR
;
1387 if (hpp
->enable_perr
)
1388 pci_bctl
|= PCI_BRIDGE_CTL_PARITY
;
1389 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, pci_bctl
);
1393 static void program_hpp_type1(struct pci_dev
*dev
, struct hpp_type1
*hpp
)
1396 dev_warn(&dev
->dev
, "PCI-X settings not supported\n");
1399 static void program_hpp_type2(struct pci_dev
*dev
, struct hpp_type2
*hpp
)
1407 if (hpp
->revision
> 1) {
1408 dev_warn(&dev
->dev
, "PCIe settings rev %d not supported\n",
1414 * Don't allow _HPX to change MPS or MRRS settings. We manage
1415 * those to make sure they're consistent with the rest of the
1418 hpp
->pci_exp_devctl_and
|= PCI_EXP_DEVCTL_PAYLOAD
|
1419 PCI_EXP_DEVCTL_READRQ
;
1420 hpp
->pci_exp_devctl_or
&= ~(PCI_EXP_DEVCTL_PAYLOAD
|
1421 PCI_EXP_DEVCTL_READRQ
);
1423 /* Initialize Device Control Register */
1424 pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
1425 ~hpp
->pci_exp_devctl_and
, hpp
->pci_exp_devctl_or
);
1427 /* Initialize Link Control Register */
1428 if (pcie_cap_has_lnkctl(dev
))
1429 pcie_capability_clear_and_set_word(dev
, PCI_EXP_LNKCTL
,
1430 ~hpp
->pci_exp_lnkctl_and
, hpp
->pci_exp_lnkctl_or
);
1432 /* Find Advanced Error Reporting Enhanced Capability */
1433 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
1437 /* Initialize Uncorrectable Error Mask Register */
1438 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, ®32
);
1439 reg32
= (reg32
& hpp
->unc_err_mask_and
) | hpp
->unc_err_mask_or
;
1440 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, reg32
);
1442 /* Initialize Uncorrectable Error Severity Register */
1443 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, ®32
);
1444 reg32
= (reg32
& hpp
->unc_err_sever_and
) | hpp
->unc_err_sever_or
;
1445 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, reg32
);
1447 /* Initialize Correctable Error Mask Register */
1448 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®32
);
1449 reg32
= (reg32
& hpp
->cor_err_mask_and
) | hpp
->cor_err_mask_or
;
1450 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg32
);
1452 /* Initialize Advanced Error Capabilities and Control Register */
1453 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
1454 reg32
= (reg32
& hpp
->adv_err_cap_and
) | hpp
->adv_err_cap_or
;
1455 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
1458 * FIXME: The following two registers are not supported yet.
1460 * o Secondary Uncorrectable Error Severity Register
1461 * o Secondary Uncorrectable Error Mask Register
1465 static void pci_configure_device(struct pci_dev
*dev
)
1467 struct hotplug_params hpp
;
1470 pci_configure_mps(dev
);
1472 memset(&hpp
, 0, sizeof(hpp
));
1473 ret
= pci_get_hp_params(dev
, &hpp
);
1477 program_hpp_type2(dev
, hpp
.t2
);
1478 program_hpp_type1(dev
, hpp
.t1
);
1479 program_hpp_type0(dev
, hpp
.t0
);
1482 static void pci_release_capabilities(struct pci_dev
*dev
)
1484 pci_vpd_release(dev
);
1485 pci_iov_release(dev
);
1486 pci_free_cap_save_buffers(dev
);
1490 * pci_release_dev - free a pci device structure when all users of it are finished.
1491 * @dev: device that's been disconnected
1493 * Will be called only by the device core when all users of this pci device are
1496 static void pci_release_dev(struct device
*dev
)
1498 struct pci_dev
*pci_dev
;
1500 pci_dev
= to_pci_dev(dev
);
1501 pci_release_capabilities(pci_dev
);
1502 pci_release_of_node(pci_dev
);
1503 pcibios_release_device(pci_dev
);
1504 pci_bus_put(pci_dev
->bus
);
1505 kfree(pci_dev
->driver_override
);
1509 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
1511 struct pci_dev
*dev
;
1513 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1517 INIT_LIST_HEAD(&dev
->bus_list
);
1518 dev
->dev
.type
= &pci_dev_type
;
1519 dev
->bus
= pci_bus_get(bus
);
1523 EXPORT_SYMBOL(pci_alloc_dev
);
1525 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
1530 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1533 /* some broken boards return 0 or ~0 if a slot is empty: */
1534 if (*l
== 0xffffffff || *l
== 0x00000000 ||
1535 *l
== 0x0000ffff || *l
== 0xffff0000)
1539 * Configuration Request Retry Status. Some root ports return the
1540 * actual device ID instead of the synthetic ID (0xFFFF) required
1541 * by the PCIe spec. Ignore the device ID and only check for
1544 while ((*l
& 0xffff) == 0x0001) {
1550 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1552 /* Card hasn't responded in 60 seconds? Must be stuck. */
1553 if (delay
> crs_timeout
) {
1554 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not responding\n",
1555 pci_domain_nr(bus
), bus
->number
, PCI_SLOT(devfn
),
1563 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
1566 * Read the config data for a PCI device, sanity-check it
1567 * and fill in the dev structure...
1569 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1571 struct pci_dev
*dev
;
1574 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
1577 dev
= pci_alloc_dev(bus
);
1582 dev
->vendor
= l
& 0xffff;
1583 dev
->device
= (l
>> 16) & 0xffff;
1585 pci_set_of_node(dev
);
1587 if (pci_setup_device(dev
)) {
1588 pci_bus_put(dev
->bus
);
1596 static void pci_init_capabilities(struct pci_dev
*dev
)
1598 /* Enhanced Allocation */
1601 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1602 pci_msi_setup_pci_dev(dev
);
1604 /* Buffers for saving PCIe and PCI-X capabilities */
1605 pci_allocate_cap_save_buffers(dev
);
1607 /* Power Management */
1610 /* Vital Product Data */
1611 pci_vpd_pci22_init(dev
);
1613 /* Alternative Routing-ID Forwarding */
1614 pci_configure_ari(dev
);
1616 /* Single Root I/O Virtualization */
1619 /* Address Translation Services */
1622 /* Enable ACS P2P upstream forwarding */
1623 pci_enable_acs(dev
);
1625 pci_cleanup_aer_error_status_regs(dev
);
1629 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1630 * devices. Firmware interfaces that can select the MSI domain on a
1631 * per-device basis should be called from here.
1633 static struct irq_domain
*pci_dev_msi_domain(struct pci_dev
*dev
)
1635 struct irq_domain
*d
;
1638 * If a domain has been set through the pcibios_add_device
1639 * callback, then this is the one (platform code knows best).
1641 d
= dev_get_msi_domain(&dev
->dev
);
1646 * Let's see if we have a firmware interface able to provide
1649 d
= pci_msi_get_device_domain(dev
);
1656 static void pci_set_msi_domain(struct pci_dev
*dev
)
1658 struct irq_domain
*d
;
1661 * If the platform or firmware interfaces cannot supply a
1662 * device-specific MSI domain, then inherit the default domain
1663 * from the host bridge itself.
1665 d
= pci_dev_msi_domain(dev
);
1667 d
= dev_get_msi_domain(&dev
->bus
->dev
);
1669 dev_set_msi_domain(&dev
->dev
, d
);
1673 * pci_dma_configure - Setup DMA configuration
1674 * @dev: ptr to pci_dev struct of the PCI device
1676 * Function to update PCI devices's DMA configuration using the same
1677 * info from the OF node or ACPI node of host bridge's parent (if any).
1679 static void pci_dma_configure(struct pci_dev
*dev
)
1681 struct device
*bridge
= pci_get_host_bridge_device(dev
);
1683 if (IS_ENABLED(CONFIG_OF
) &&
1684 bridge
->parent
&& bridge
->parent
->of_node
) {
1685 of_dma_configure(&dev
->dev
, bridge
->parent
->of_node
);
1686 } else if (has_acpi_companion(bridge
)) {
1687 struct acpi_device
*adev
= to_acpi_device_node(bridge
->fwnode
);
1688 enum dev_dma_attr attr
= acpi_get_dma_attr(adev
);
1690 if (attr
== DEV_DMA_NOT_SUPPORTED
)
1691 dev_warn(&dev
->dev
, "DMA not supported.\n");
1693 arch_setup_dma_ops(&dev
->dev
, 0, 0, NULL
,
1694 attr
== DEV_DMA_COHERENT
);
1697 pci_put_host_bridge_device(bridge
);
1700 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1704 pci_configure_device(dev
);
1706 device_initialize(&dev
->dev
);
1707 dev
->dev
.release
= pci_release_dev
;
1709 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
1710 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1711 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1712 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1713 pci_dma_configure(dev
);
1715 pci_set_dma_max_seg_size(dev
, 65536);
1716 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1718 /* Fix up broken headers */
1719 pci_fixup_device(pci_fixup_header
, dev
);
1721 /* moved out from quirk header fixup code */
1722 pci_reassigndev_resource_alignment(dev
);
1724 /* Clear the state_saved flag. */
1725 dev
->state_saved
= false;
1727 /* Initialize various capabilities */
1728 pci_init_capabilities(dev
);
1731 * Add the device to our list of discovered devices
1732 * and the bus list for fixup functions, etc.
1734 down_write(&pci_bus_sem
);
1735 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1736 up_write(&pci_bus_sem
);
1738 ret
= pcibios_add_device(dev
);
1741 /* Setup MSI irq domain */
1742 pci_set_msi_domain(dev
);
1744 /* Notifier could use PCI capabilities */
1745 dev
->match_driver
= false;
1746 ret
= device_add(&dev
->dev
);
1750 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1752 struct pci_dev
*dev
;
1754 dev
= pci_get_slot(bus
, devfn
);
1760 dev
= pci_scan_device(bus
, devfn
);
1764 pci_device_add(dev
, bus
);
1768 EXPORT_SYMBOL(pci_scan_single_device
);
1770 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
1776 if (pci_ari_enabled(bus
)) {
1779 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1783 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
1784 next_fn
= PCI_ARI_CAP_NFN(cap
);
1786 return 0; /* protect against malformed list */
1791 /* dev may be NULL for non-contiguous multifunction devices */
1792 if (!dev
|| dev
->multifunction
)
1793 return (fn
+ 1) % 8;
1798 static int only_one_child(struct pci_bus
*bus
)
1800 struct pci_dev
*parent
= bus
->self
;
1802 if (!parent
|| !pci_is_pcie(parent
))
1804 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_ROOT_PORT
)
1806 if (parent
->has_secondary_link
&&
1807 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
1813 * pci_scan_slot - scan a PCI slot on a bus for devices.
1814 * @bus: PCI bus to scan
1815 * @devfn: slot number to scan (must have zero function.)
1817 * Scan a PCI slot on the specified PCI bus for devices, adding
1818 * discovered devices to the @bus->devices list. New devices
1819 * will not have is_added set.
1821 * Returns the number of new devices found.
1823 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1825 unsigned fn
, nr
= 0;
1826 struct pci_dev
*dev
;
1828 if (only_one_child(bus
) && (devfn
> 0))
1829 return 0; /* Already scanned the entire slot */
1831 dev
= pci_scan_single_device(bus
, devfn
);
1837 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
1838 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1842 dev
->multifunction
= 1;
1846 /* only one slot has pcie device */
1847 if (bus
->self
&& nr
)
1848 pcie_aspm_init_link_state(bus
->self
);
1852 EXPORT_SYMBOL(pci_scan_slot
);
1854 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
1858 if (!pci_is_pcie(dev
))
1862 * We don't have a way to change MPS settings on devices that have
1863 * drivers attached. A hot-added device might support only the minimum
1864 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1865 * where devices may be hot-added, we limit the fabric MPS to 128 so
1866 * hot-added devices will work correctly.
1868 * However, if we hot-add a device to a slot directly below a Root
1869 * Port, it's impossible for there to be other existing devices below
1870 * the port. We don't limit the MPS in this case because we can
1871 * reconfigure MPS on both the Root Port and the hot-added device,
1872 * and there are no other devices involved.
1874 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1876 if (dev
->is_hotplug_bridge
&&
1877 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
1880 if (*smpss
> dev
->pcie_mpss
)
1881 *smpss
= dev
->pcie_mpss
;
1886 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
1890 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
1891 mps
= 128 << dev
->pcie_mpss
;
1893 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
1895 /* For "Performance", the assumption is made that
1896 * downstream communication will never be larger than
1897 * the MRRS. So, the MPS only needs to be configured
1898 * for the upstream communication. This being the case,
1899 * walk from the top down and set the MPS of the child
1900 * to that of the parent bus.
1902 * Configure the device MPS with the smaller of the
1903 * device MPSS or the bridge MPS (which is assumed to be
1904 * properly configured at this point to the largest
1905 * allowable MPS based on its parent bus).
1907 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
1910 rc
= pcie_set_mps(dev
, mps
);
1912 dev_err(&dev
->dev
, "Failed attempting to set the MPS\n");
1915 static void pcie_write_mrrs(struct pci_dev
*dev
)
1919 /* In the "safe" case, do not configure the MRRS. There appear to be
1920 * issues with setting MRRS to 0 on a number of devices.
1922 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
1925 /* For Max performance, the MRRS must be set to the largest supported
1926 * value. However, it cannot be configured larger than the MPS the
1927 * device or the bus can support. This should already be properly
1928 * configured by a prior call to pcie_write_mps.
1930 mrrs
= pcie_get_mps(dev
);
1932 /* MRRS is a R/W register. Invalid values can be written, but a
1933 * subsequent read will verify if the value is acceptable or not.
1934 * If the MRRS value provided is not acceptable (e.g., too large),
1935 * shrink the value until it is acceptable to the HW.
1937 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
1938 rc
= pcie_set_readrq(dev
, mrrs
);
1942 dev_warn(&dev
->dev
, "Failed attempting to set the MRRS\n");
1947 dev_err(&dev
->dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1950 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
1954 if (!pci_is_pcie(dev
))
1957 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
1958 pcie_bus_config
== PCIE_BUS_DEFAULT
)
1961 mps
= 128 << *(u8
*)data
;
1962 orig_mps
= pcie_get_mps(dev
);
1964 pcie_write_mps(dev
, mps
);
1965 pcie_write_mrrs(dev
);
1967 dev_info(&dev
->dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1968 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
1969 orig_mps
, pcie_get_readrq(dev
));
1974 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1975 * parents then children fashion. If this changes, then this code will not
1978 void pcie_bus_configure_settings(struct pci_bus
*bus
)
1985 if (!pci_is_pcie(bus
->self
))
1988 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1989 * to be aware of the MPS of the destination. To work around this,
1990 * simply force the MPS of the entire system to the smallest possible.
1992 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
1995 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
1996 smpss
= bus
->self
->pcie_mpss
;
1998 pcie_find_smpss(bus
->self
, &smpss
);
1999 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
2002 pcie_bus_configure_set(bus
->self
, &smpss
);
2003 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
2005 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
2007 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
2009 unsigned int devfn
, pass
, max
= bus
->busn_res
.start
;
2010 struct pci_dev
*dev
;
2012 dev_dbg(&bus
->dev
, "scanning bus\n");
2014 /* Go find them, Rover! */
2015 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
2016 pci_scan_slot(bus
, devfn
);
2018 /* Reserve buses for SR-IOV capability. */
2019 max
+= pci_iov_bus_range(bus
);
2022 * After performing arch-dependent fixup of the bus, look behind
2023 * all PCI-to-PCI bridges on this bus.
2025 if (!bus
->is_added
) {
2026 dev_dbg(&bus
->dev
, "fixups for bus\n");
2027 pcibios_fixup_bus(bus
);
2031 for (pass
= 0; pass
< 2; pass
++)
2032 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
2033 if (pci_is_bridge(dev
))
2034 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
2038 * We've scanned the bus and so we know all about what's on
2039 * the other side of any bridges that may be on this bus plus
2042 * Return how far we've got finding sub-buses.
2044 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
2047 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
2050 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2051 * @bridge: Host bridge to set up.
2053 * Default empty implementation. Replace with an architecture-specific setup
2054 * routine, if necessary.
2056 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
2061 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
2065 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
2069 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
2070 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2073 struct pci_host_bridge
*bridge
;
2074 struct pci_bus
*b
, *b2
;
2075 struct resource_entry
*window
, *n
;
2076 struct resource
*res
;
2077 resource_size_t offset
;
2081 b
= pci_alloc_bus(NULL
);
2085 b
->sysdata
= sysdata
;
2087 b
->number
= b
->busn_res
.start
= bus
;
2088 pci_bus_assign_domain_nr(b
, parent
);
2089 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
2091 /* If we already got to this bus through a different bridge, ignore it */
2092 dev_dbg(&b2
->dev
, "bus already known\n");
2096 bridge
= pci_alloc_host_bridge(b
);
2100 bridge
->dev
.parent
= parent
;
2101 bridge
->dev
.release
= pci_release_host_bridge_dev
;
2102 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
2103 error
= pcibios_root_bridge_prepare(bridge
);
2109 error
= device_register(&bridge
->dev
);
2111 put_device(&bridge
->dev
);
2114 b
->bridge
= get_device(&bridge
->dev
);
2115 device_enable_async_suspend(b
->bridge
);
2116 pci_set_bus_of_node(b
);
2117 pci_set_bus_msi_domain(b
);
2120 set_dev_node(b
->bridge
, pcibus_to_node(b
));
2122 b
->dev
.class = &pcibus_class
;
2123 b
->dev
.parent
= b
->bridge
;
2124 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
2125 error
= device_register(&b
->dev
);
2127 goto class_dev_reg_err
;
2131 /* Create legacy_io and legacy_mem files for this bus */
2132 pci_create_legacy_files(b
);
2135 dev_info(parent
, "PCI host bridge to bus %s\n", dev_name(&b
->dev
));
2137 printk(KERN_INFO
"PCI host bridge to bus %s\n", dev_name(&b
->dev
));
2139 /* Add initial resources to the bus */
2140 resource_list_for_each_entry_safe(window
, n
, resources
) {
2141 list_move_tail(&window
->node
, &bridge
->windows
);
2143 offset
= window
->offset
;
2144 if (res
->flags
& IORESOURCE_BUS
)
2145 pci_bus_insert_busn_res(b
, bus
, res
->end
);
2147 pci_bus_add_resource(b
, res
, 0);
2149 if (resource_type(res
) == IORESOURCE_IO
)
2150 fmt
= " (bus address [%#06llx-%#06llx])";
2152 fmt
= " (bus address [%#010llx-%#010llx])";
2153 snprintf(bus_addr
, sizeof(bus_addr
), fmt
,
2154 (unsigned long long) (res
->start
- offset
),
2155 (unsigned long long) (res
->end
- offset
));
2158 dev_info(&b
->dev
, "root bus resource %pR%s\n", res
, bus_addr
);
2161 down_write(&pci_bus_sem
);
2162 list_add_tail(&b
->node
, &pci_root_buses
);
2163 up_write(&pci_bus_sem
);
2168 put_device(&bridge
->dev
);
2169 device_unregister(&bridge
->dev
);
2174 EXPORT_SYMBOL_GPL(pci_create_root_bus
);
2176 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
2178 struct resource
*res
= &b
->busn_res
;
2179 struct resource
*parent_res
, *conflict
;
2183 res
->flags
= IORESOURCE_BUS
;
2185 if (!pci_is_root_bus(b
))
2186 parent_res
= &b
->parent
->busn_res
;
2188 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
2189 res
->flags
|= IORESOURCE_PCI_FIXED
;
2192 conflict
= request_resource_conflict(parent_res
, res
);
2195 dev_printk(KERN_DEBUG
, &b
->dev
,
2196 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2197 res
, pci_is_root_bus(b
) ? "domain " : "",
2198 parent_res
, conflict
->name
, conflict
);
2200 return conflict
== NULL
;
2203 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
2205 struct resource
*res
= &b
->busn_res
;
2206 struct resource old_res
= *res
;
2207 resource_size_t size
;
2210 if (res
->start
> bus_max
)
2213 size
= bus_max
- res
->start
+ 1;
2214 ret
= adjust_resource(res
, res
->start
, size
);
2215 dev_printk(KERN_DEBUG
, &b
->dev
,
2216 "busn_res: %pR end %s updated to %02x\n",
2217 &old_res
, ret
? "can not be" : "is", bus_max
);
2219 if (!ret
&& !res
->parent
)
2220 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
2225 void pci_bus_release_busn_res(struct pci_bus
*b
)
2227 struct resource
*res
= &b
->busn_res
;
2230 if (!res
->flags
|| !res
->parent
)
2233 ret
= release_resource(res
);
2234 dev_printk(KERN_DEBUG
, &b
->dev
,
2235 "busn_res: %pR %s released\n",
2236 res
, ret
? "can not be" : "is");
2239 struct pci_bus
*pci_scan_root_bus_msi(struct device
*parent
, int bus
,
2240 struct pci_ops
*ops
, void *sysdata
,
2241 struct list_head
*resources
, struct msi_controller
*msi
)
2243 struct resource_entry
*window
;
2248 resource_list_for_each_entry(window
, resources
)
2249 if (window
->res
->flags
& IORESOURCE_BUS
) {
2254 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
2262 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2264 pci_bus_insert_busn_res(b
, bus
, 255);
2267 max
= pci_scan_child_bus(b
);
2270 pci_bus_update_busn_res_end(b
, max
);
2275 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
2276 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2278 return pci_scan_root_bus_msi(parent
, bus
, ops
, sysdata
, resources
,
2281 EXPORT_SYMBOL(pci_scan_root_bus
);
2283 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
2286 LIST_HEAD(resources
);
2289 pci_add_resource(&resources
, &ioport_resource
);
2290 pci_add_resource(&resources
, &iomem_resource
);
2291 pci_add_resource(&resources
, &busn_resource
);
2292 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
2294 pci_scan_child_bus(b
);
2296 pci_free_resource_list(&resources
);
2300 EXPORT_SYMBOL(pci_scan_bus
);
2303 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2304 * @bridge: PCI bridge for the bus to scan
2306 * Scan a PCI bus and child buses for new devices, add them,
2307 * and enable them, resizing bridge mmio/io resource if necessary
2308 * and possible. The caller must ensure the child devices are already
2309 * removed for resizing to occur.
2311 * Returns the max number of subordinate bus discovered.
2313 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
2316 struct pci_bus
*bus
= bridge
->subordinate
;
2318 max
= pci_scan_child_bus(bus
);
2320 pci_assign_unassigned_bridge_resources(bridge
);
2322 pci_bus_add_devices(bus
);
2328 * pci_rescan_bus - scan a PCI bus for devices.
2329 * @bus: PCI bus to scan
2331 * Scan a PCI bus and child buses for new devices, adds them,
2334 * Returns the max number of subordinate bus discovered.
2336 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
2340 max
= pci_scan_child_bus(bus
);
2341 pci_assign_unassigned_bus_resources(bus
);
2342 pci_bus_add_devices(bus
);
2346 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
2349 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2350 * routines should always be executed under this mutex.
2352 static DEFINE_MUTEX(pci_rescan_remove_lock
);
2354 void pci_lock_rescan_remove(void)
2356 mutex_lock(&pci_rescan_remove_lock
);
2358 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
2360 void pci_unlock_rescan_remove(void)
2362 mutex_unlock(&pci_rescan_remove_lock
);
2364 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
2366 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
2367 const struct device
*d_b
)
2369 const struct pci_dev
*a
= to_pci_dev(d_a
);
2370 const struct pci_dev
*b
= to_pci_dev(d_b
);
2372 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
2373 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
2375 if (a
->bus
->number
< b
->bus
->number
) return -1;
2376 else if (a
->bus
->number
> b
->bus
->number
) return 1;
2378 if (a
->devfn
< b
->devfn
) return -1;
2379 else if (a
->devfn
> b
->devfn
) return 1;
2384 void __init
pci_sort_breadthfirst(void)
2386 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);