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pci/of: Match PCI devices to OF nodes dynamically
[deliverable/linux.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class
47 */
48 static void release_pcibus_dev(struct device *dev)
49 {
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 pci_release_bus_of_node(pci_bus);
56 kfree(pci_bus);
57 }
58
59 static struct class pcibus_class = {
60 .name = "pci_bus",
61 .dev_release = &release_pcibus_dev,
62 .dev_attrs = pcibus_dev_attrs,
63 };
64
65 static int __init pcibus_class_init(void)
66 {
67 return class_register(&pcibus_class);
68 }
69 postcore_initcall(pcibus_class_init);
70
71 /*
72 * Translate the low bits of the PCI base
73 * to the resource type
74 */
75 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
76 {
77 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
78 return IORESOURCE_IO;
79
80 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
81 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
82
83 return IORESOURCE_MEM;
84 }
85
86 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
87 {
88 u64 size = mask & maxbase; /* Find the significant bits */
89 if (!size)
90 return 0;
91
92 /* Get the lowest of them to find the decode size, and
93 from that the extent. */
94 size = (size & ~(size-1)) - 1;
95
96 /* base == maxbase can be valid only if the BAR has
97 already been programmed with all 1s. */
98 if (base == maxbase && ((base | size) & mask) != mask)
99 return 0;
100
101 return size;
102 }
103
104 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
105 {
106 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
107 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
108 return pci_bar_io;
109 }
110
111 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
112
113 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
114 return pci_bar_mem64;
115 return pci_bar_mem32;
116 }
117
118 /**
119 * pci_read_base - read a PCI BAR
120 * @dev: the PCI device
121 * @type: type of the BAR
122 * @res: resource buffer to be filled in
123 * @pos: BAR position in the config space
124 *
125 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
126 */
127 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
128 struct resource *res, unsigned int pos)
129 {
130 u32 l, sz, mask;
131 u16 orig_cmd;
132
133 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
134
135 if (!dev->mmio_always_on) {
136 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
137 pci_write_config_word(dev, PCI_COMMAND,
138 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
139 }
140
141 res->name = pci_name(dev);
142
143 pci_read_config_dword(dev, pos, &l);
144 pci_write_config_dword(dev, pos, l | mask);
145 pci_read_config_dword(dev, pos, &sz);
146 pci_write_config_dword(dev, pos, l);
147
148 if (!dev->mmio_always_on)
149 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
150
151 /*
152 * All bits set in sz means the device isn't working properly.
153 * If the BAR isn't implemented, all bits must be 0. If it's a
154 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
155 * 1 must be clear.
156 */
157 if (!sz || sz == 0xffffffff)
158 goto fail;
159
160 /*
161 * I don't know how l can have all bits set. Copied from old code.
162 * Maybe it fixes a bug on some ancient platform.
163 */
164 if (l == 0xffffffff)
165 l = 0;
166
167 if (type == pci_bar_unknown) {
168 type = decode_bar(res, l);
169 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
170 if (type == pci_bar_io) {
171 l &= PCI_BASE_ADDRESS_IO_MASK;
172 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
173 } else {
174 l &= PCI_BASE_ADDRESS_MEM_MASK;
175 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
176 }
177 } else {
178 res->flags |= (l & IORESOURCE_ROM_ENABLE);
179 l &= PCI_ROM_ADDRESS_MASK;
180 mask = (u32)PCI_ROM_ADDRESS_MASK;
181 }
182
183 if (type == pci_bar_mem64) {
184 u64 l64 = l;
185 u64 sz64 = sz;
186 u64 mask64 = mask | (u64)~0 << 32;
187
188 pci_read_config_dword(dev, pos + 4, &l);
189 pci_write_config_dword(dev, pos + 4, ~0);
190 pci_read_config_dword(dev, pos + 4, &sz);
191 pci_write_config_dword(dev, pos + 4, l);
192
193 l64 |= ((u64)l << 32);
194 sz64 |= ((u64)sz << 32);
195
196 sz64 = pci_size(l64, sz64, mask64);
197
198 if (!sz64)
199 goto fail;
200
201 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
202 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
203 pos);
204 goto fail;
205 }
206
207 res->flags |= IORESOURCE_MEM_64;
208 if ((sizeof(resource_size_t) < 8) && l) {
209 /* Address above 32-bit boundary; disable the BAR */
210 pci_write_config_dword(dev, pos, 0);
211 pci_write_config_dword(dev, pos + 4, 0);
212 res->start = 0;
213 res->end = sz64;
214 } else {
215 res->start = l64;
216 res->end = l64 + sz64;
217 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
218 pos, res);
219 }
220 } else {
221 sz = pci_size(l, sz, mask);
222
223 if (!sz)
224 goto fail;
225
226 res->start = l;
227 res->end = l + sz;
228
229 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
230 }
231
232 out:
233 return (type == pci_bar_mem64) ? 1 : 0;
234 fail:
235 res->flags = 0;
236 goto out;
237 }
238
239 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
240 {
241 unsigned int pos, reg;
242
243 for (pos = 0; pos < howmany; pos++) {
244 struct resource *res = &dev->resource[pos];
245 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
246 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
247 }
248
249 if (rom) {
250 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
251 dev->rom_base_reg = rom;
252 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
253 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
254 IORESOURCE_SIZEALIGN;
255 __pci_read_base(dev, pci_bar_mem32, res, rom);
256 }
257 }
258
259 static void __devinit pci_read_bridge_io(struct pci_bus *child)
260 {
261 struct pci_dev *dev = child->self;
262 u8 io_base_lo, io_limit_lo;
263 unsigned long base, limit;
264 struct resource *res;
265
266 res = child->resource[0];
267 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
268 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
269 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
270 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
271
272 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
273 u16 io_base_hi, io_limit_hi;
274 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
275 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
276 base |= (io_base_hi << 16);
277 limit |= (io_limit_hi << 16);
278 }
279
280 if (base && base <= limit) {
281 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
282 if (!res->start)
283 res->start = base;
284 if (!res->end)
285 res->end = limit + 0xfff;
286 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
287 } else {
288 dev_printk(KERN_DEBUG, &dev->dev,
289 " bridge window [io %#06lx-%#06lx] (disabled)\n",
290 base, limit);
291 }
292 }
293
294 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
295 {
296 struct pci_dev *dev = child->self;
297 u16 mem_base_lo, mem_limit_lo;
298 unsigned long base, limit;
299 struct resource *res;
300
301 res = child->resource[1];
302 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
303 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
304 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
305 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
306 if (base && base <= limit) {
307 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
308 res->start = base;
309 res->end = limit + 0xfffff;
310 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
311 } else {
312 dev_printk(KERN_DEBUG, &dev->dev,
313 " bridge window [mem %#010lx-%#010lx] (disabled)\n",
314 base, limit + 0xfffff);
315 }
316 }
317
318 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
319 {
320 struct pci_dev *dev = child->self;
321 u16 mem_base_lo, mem_limit_lo;
322 unsigned long base, limit;
323 struct resource *res;
324
325 res = child->resource[2];
326 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
327 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
328 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
329 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
330
331 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
332 u32 mem_base_hi, mem_limit_hi;
333 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
334 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
335
336 /*
337 * Some bridges set the base > limit by default, and some
338 * (broken) BIOSes do not initialize them. If we find
339 * this, just assume they are not being used.
340 */
341 if (mem_base_hi <= mem_limit_hi) {
342 #if BITS_PER_LONG == 64
343 base |= ((long) mem_base_hi) << 32;
344 limit |= ((long) mem_limit_hi) << 32;
345 #else
346 if (mem_base_hi || mem_limit_hi) {
347 dev_err(&dev->dev, "can't handle 64-bit "
348 "address space for bridge\n");
349 return;
350 }
351 #endif
352 }
353 }
354 if (base && base <= limit) {
355 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
356 IORESOURCE_MEM | IORESOURCE_PREFETCH;
357 if (res->flags & PCI_PREF_RANGE_TYPE_64)
358 res->flags |= IORESOURCE_MEM_64;
359 res->start = base;
360 res->end = limit + 0xfffff;
361 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
362 } else {
363 dev_printk(KERN_DEBUG, &dev->dev,
364 " bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
365 base, limit + 0xfffff);
366 }
367 }
368
369 void __devinit pci_read_bridge_bases(struct pci_bus *child)
370 {
371 struct pci_dev *dev = child->self;
372 struct resource *res;
373 int i;
374
375 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
376 return;
377
378 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
379 child->secondary, child->subordinate,
380 dev->transparent ? " (subtractive decode)" : "");
381
382 pci_bus_remove_resources(child);
383 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
384 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
385
386 pci_read_bridge_io(child);
387 pci_read_bridge_mmio(child);
388 pci_read_bridge_mmio_pref(child);
389
390 if (dev->transparent) {
391 pci_bus_for_each_resource(child->parent, res, i) {
392 if (res) {
393 pci_bus_add_resource(child, res,
394 PCI_SUBTRACTIVE_DECODE);
395 dev_printk(KERN_DEBUG, &dev->dev,
396 " bridge window %pR (subtractive decode)\n",
397 res);
398 }
399 }
400 }
401 }
402
403 static struct pci_bus * pci_alloc_bus(void)
404 {
405 struct pci_bus *b;
406
407 b = kzalloc(sizeof(*b), GFP_KERNEL);
408 if (b) {
409 INIT_LIST_HEAD(&b->node);
410 INIT_LIST_HEAD(&b->children);
411 INIT_LIST_HEAD(&b->devices);
412 INIT_LIST_HEAD(&b->slots);
413 INIT_LIST_HEAD(&b->resources);
414 b->max_bus_speed = PCI_SPEED_UNKNOWN;
415 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
416 }
417 return b;
418 }
419
420 static unsigned char pcix_bus_speed[] = {
421 PCI_SPEED_UNKNOWN, /* 0 */
422 PCI_SPEED_66MHz_PCIX, /* 1 */
423 PCI_SPEED_100MHz_PCIX, /* 2 */
424 PCI_SPEED_133MHz_PCIX, /* 3 */
425 PCI_SPEED_UNKNOWN, /* 4 */
426 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
427 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
428 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
429 PCI_SPEED_UNKNOWN, /* 8 */
430 PCI_SPEED_66MHz_PCIX_266, /* 9 */
431 PCI_SPEED_100MHz_PCIX_266, /* A */
432 PCI_SPEED_133MHz_PCIX_266, /* B */
433 PCI_SPEED_UNKNOWN, /* C */
434 PCI_SPEED_66MHz_PCIX_533, /* D */
435 PCI_SPEED_100MHz_PCIX_533, /* E */
436 PCI_SPEED_133MHz_PCIX_533 /* F */
437 };
438
439 static unsigned char pcie_link_speed[] = {
440 PCI_SPEED_UNKNOWN, /* 0 */
441 PCIE_SPEED_2_5GT, /* 1 */
442 PCIE_SPEED_5_0GT, /* 2 */
443 PCIE_SPEED_8_0GT, /* 3 */
444 PCI_SPEED_UNKNOWN, /* 4 */
445 PCI_SPEED_UNKNOWN, /* 5 */
446 PCI_SPEED_UNKNOWN, /* 6 */
447 PCI_SPEED_UNKNOWN, /* 7 */
448 PCI_SPEED_UNKNOWN, /* 8 */
449 PCI_SPEED_UNKNOWN, /* 9 */
450 PCI_SPEED_UNKNOWN, /* A */
451 PCI_SPEED_UNKNOWN, /* B */
452 PCI_SPEED_UNKNOWN, /* C */
453 PCI_SPEED_UNKNOWN, /* D */
454 PCI_SPEED_UNKNOWN, /* E */
455 PCI_SPEED_UNKNOWN /* F */
456 };
457
458 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
459 {
460 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
461 }
462 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
463
464 static unsigned char agp_speeds[] = {
465 AGP_UNKNOWN,
466 AGP_1X,
467 AGP_2X,
468 AGP_4X,
469 AGP_8X
470 };
471
472 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
473 {
474 int index = 0;
475
476 if (agpstat & 4)
477 index = 3;
478 else if (agpstat & 2)
479 index = 2;
480 else if (agpstat & 1)
481 index = 1;
482 else
483 goto out;
484
485 if (agp3) {
486 index += 2;
487 if (index == 5)
488 index = 0;
489 }
490
491 out:
492 return agp_speeds[index];
493 }
494
495
496 static void pci_set_bus_speed(struct pci_bus *bus)
497 {
498 struct pci_dev *bridge = bus->self;
499 int pos;
500
501 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
502 if (!pos)
503 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
504 if (pos) {
505 u32 agpstat, agpcmd;
506
507 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
508 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
509
510 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
511 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
512 }
513
514 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
515 if (pos) {
516 u16 status;
517 enum pci_bus_speed max;
518 pci_read_config_word(bridge, pos + 2, &status);
519
520 if (status & 0x8000) {
521 max = PCI_SPEED_133MHz_PCIX_533;
522 } else if (status & 0x4000) {
523 max = PCI_SPEED_133MHz_PCIX_266;
524 } else if (status & 0x0002) {
525 if (((status >> 12) & 0x3) == 2) {
526 max = PCI_SPEED_133MHz_PCIX_ECC;
527 } else {
528 max = PCI_SPEED_133MHz_PCIX;
529 }
530 } else {
531 max = PCI_SPEED_66MHz_PCIX;
532 }
533
534 bus->max_bus_speed = max;
535 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
536
537 return;
538 }
539
540 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
541 if (pos) {
542 u32 linkcap;
543 u16 linksta;
544
545 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
546 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
547
548 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
549 pcie_update_link_speed(bus, linksta);
550 }
551 }
552
553
554 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
555 struct pci_dev *bridge, int busnr)
556 {
557 struct pci_bus *child;
558 int i;
559
560 /*
561 * Allocate a new bus, and inherit stuff from the parent..
562 */
563 child = pci_alloc_bus();
564 if (!child)
565 return NULL;
566
567 child->parent = parent;
568 child->ops = parent->ops;
569 child->sysdata = parent->sysdata;
570 child->bus_flags = parent->bus_flags;
571
572 /* initialize some portions of the bus device, but don't register it
573 * now as the parent is not properly set up yet. This device will get
574 * registered later in pci_bus_add_devices()
575 */
576 child->dev.class = &pcibus_class;
577 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
578
579 /*
580 * Set up the primary, secondary and subordinate
581 * bus numbers.
582 */
583 child->number = child->secondary = busnr;
584 child->primary = parent->secondary;
585 child->subordinate = 0xff;
586
587 if (!bridge)
588 return child;
589
590 child->self = bridge;
591 child->bridge = get_device(&bridge->dev);
592 pci_set_bus_of_node(child);
593 pci_set_bus_speed(child);
594
595 /* Set up default resource pointers and names.. */
596 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
597 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
598 child->resource[i]->name = child->name;
599 }
600 bridge->subordinate = child;
601
602 return child;
603 }
604
605 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
606 {
607 struct pci_bus *child;
608
609 child = pci_alloc_child_bus(parent, dev, busnr);
610 if (child) {
611 down_write(&pci_bus_sem);
612 list_add_tail(&child->node, &parent->children);
613 up_write(&pci_bus_sem);
614 }
615 return child;
616 }
617
618 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
619 {
620 struct pci_bus *parent = child->parent;
621
622 /* Attempts to fix that up are really dangerous unless
623 we're going to re-assign all bus numbers. */
624 if (!pcibios_assign_all_busses())
625 return;
626
627 while (parent->parent && parent->subordinate < max) {
628 parent->subordinate = max;
629 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
630 parent = parent->parent;
631 }
632 }
633
634 /*
635 * If it's a bridge, configure it and scan the bus behind it.
636 * For CardBus bridges, we don't scan behind as the devices will
637 * be handled by the bridge driver itself.
638 *
639 * We need to process bridges in two passes -- first we scan those
640 * already configured by the BIOS and after we are done with all of
641 * them, we proceed to assigning numbers to the remaining buses in
642 * order to avoid overlaps between old and new bus numbers.
643 */
644 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
645 {
646 struct pci_bus *child;
647 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
648 u32 buses, i, j = 0;
649 u16 bctl;
650 u8 primary, secondary, subordinate;
651 int broken = 0;
652
653 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
654 primary = buses & 0xFF;
655 secondary = (buses >> 8) & 0xFF;
656 subordinate = (buses >> 16) & 0xFF;
657
658 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
659 secondary, subordinate, pass);
660
661 /* Check if setup is sensible at all */
662 if (!pass &&
663 (primary != bus->number || secondary <= bus->number)) {
664 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
665 broken = 1;
666 }
667
668 /* Disable MasterAbortMode during probing to avoid reporting
669 of bus errors (in some architectures) */
670 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
671 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
672 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
673
674 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
675 !is_cardbus && !broken) {
676 unsigned int cmax;
677 /*
678 * Bus already configured by firmware, process it in the first
679 * pass and just note the configuration.
680 */
681 if (pass)
682 goto out;
683
684 /*
685 * If we already got to this bus through a different bridge,
686 * don't re-add it. This can happen with the i450NX chipset.
687 *
688 * However, we continue to descend down the hierarchy and
689 * scan remaining child buses.
690 */
691 child = pci_find_bus(pci_domain_nr(bus), secondary);
692 if (!child) {
693 child = pci_add_new_bus(bus, dev, secondary);
694 if (!child)
695 goto out;
696 child->primary = primary;
697 child->subordinate = subordinate;
698 child->bridge_ctl = bctl;
699 }
700
701 cmax = pci_scan_child_bus(child);
702 if (cmax > max)
703 max = cmax;
704 if (child->subordinate > max)
705 max = child->subordinate;
706 } else {
707 /*
708 * We need to assign a number to this bus which we always
709 * do in the second pass.
710 */
711 if (!pass) {
712 if (pcibios_assign_all_busses() || broken)
713 /* Temporarily disable forwarding of the
714 configuration cycles on all bridges in
715 this bus segment to avoid possible
716 conflicts in the second pass between two
717 bridges programmed with overlapping
718 bus ranges. */
719 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
720 buses & ~0xffffff);
721 goto out;
722 }
723
724 /* Clear errors */
725 pci_write_config_word(dev, PCI_STATUS, 0xffff);
726
727 /* Prevent assigning a bus number that already exists.
728 * This can happen when a bridge is hot-plugged */
729 if (pci_find_bus(pci_domain_nr(bus), max+1))
730 goto out;
731 child = pci_add_new_bus(bus, dev, ++max);
732 if (!child)
733 goto out;
734 buses = (buses & 0xff000000)
735 | ((unsigned int)(child->primary) << 0)
736 | ((unsigned int)(child->secondary) << 8)
737 | ((unsigned int)(child->subordinate) << 16);
738
739 /*
740 * yenta.c forces a secondary latency timer of 176.
741 * Copy that behaviour here.
742 */
743 if (is_cardbus) {
744 buses &= ~0xff000000;
745 buses |= CARDBUS_LATENCY_TIMER << 24;
746 }
747
748 /*
749 * We need to blast all three values with a single write.
750 */
751 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
752
753 if (!is_cardbus) {
754 child->bridge_ctl = bctl;
755 /*
756 * Adjust subordinate busnr in parent buses.
757 * We do this before scanning for children because
758 * some devices may not be detected if the bios
759 * was lazy.
760 */
761 pci_fixup_parent_subordinate_busnr(child, max);
762 /* Now we can scan all subordinate buses... */
763 max = pci_scan_child_bus(child);
764 /*
765 * now fix it up again since we have found
766 * the real value of max.
767 */
768 pci_fixup_parent_subordinate_busnr(child, max);
769 } else {
770 /*
771 * For CardBus bridges, we leave 4 bus numbers
772 * as cards with a PCI-to-PCI bridge can be
773 * inserted later.
774 */
775 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
776 struct pci_bus *parent = bus;
777 if (pci_find_bus(pci_domain_nr(bus),
778 max+i+1))
779 break;
780 while (parent->parent) {
781 if ((!pcibios_assign_all_busses()) &&
782 (parent->subordinate > max) &&
783 (parent->subordinate <= max+i)) {
784 j = 1;
785 }
786 parent = parent->parent;
787 }
788 if (j) {
789 /*
790 * Often, there are two cardbus bridges
791 * -- try to leave one valid bus number
792 * for each one.
793 */
794 i /= 2;
795 break;
796 }
797 }
798 max += i;
799 pci_fixup_parent_subordinate_busnr(child, max);
800 }
801 /*
802 * Set the subordinate bus number to its real value.
803 */
804 child->subordinate = max;
805 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
806 }
807
808 sprintf(child->name,
809 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
810 pci_domain_nr(bus), child->number);
811
812 /* Has only triggered on CardBus, fixup is in yenta_socket */
813 while (bus->parent) {
814 if ((child->subordinate > bus->subordinate) ||
815 (child->number > bus->subordinate) ||
816 (child->number < bus->number) ||
817 (child->subordinate < bus->number)) {
818 dev_info(&child->dev, "[bus %02x-%02x] %s "
819 "hidden behind%s bridge %s [bus %02x-%02x]\n",
820 child->number, child->subordinate,
821 (bus->number > child->subordinate &&
822 bus->subordinate < child->number) ?
823 "wholly" : "partially",
824 bus->self->transparent ? " transparent" : "",
825 dev_name(&bus->dev),
826 bus->number, bus->subordinate);
827 }
828 bus = bus->parent;
829 }
830
831 out:
832 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
833
834 return max;
835 }
836
837 /*
838 * Read interrupt line and base address registers.
839 * The architecture-dependent code can tweak these, of course.
840 */
841 static void pci_read_irq(struct pci_dev *dev)
842 {
843 unsigned char irq;
844
845 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
846 dev->pin = irq;
847 if (irq)
848 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
849 dev->irq = irq;
850 }
851
852 void set_pcie_port_type(struct pci_dev *pdev)
853 {
854 int pos;
855 u16 reg16;
856
857 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
858 if (!pos)
859 return;
860 pdev->is_pcie = 1;
861 pdev->pcie_cap = pos;
862 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
863 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
864 }
865
866 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
867 {
868 int pos;
869 u16 reg16;
870 u32 reg32;
871
872 pos = pci_pcie_cap(pdev);
873 if (!pos)
874 return;
875 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
876 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
877 return;
878 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
879 if (reg32 & PCI_EXP_SLTCAP_HPC)
880 pdev->is_hotplug_bridge = 1;
881 }
882
883 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
884
885 /**
886 * pci_setup_device - fill in class and map information of a device
887 * @dev: the device structure to fill
888 *
889 * Initialize the device structure with information about the device's
890 * vendor,class,memory and IO-space addresses,IRQ lines etc.
891 * Called at initialisation of the PCI subsystem and by CardBus services.
892 * Returns 0 on success and negative if unknown type of device (not normal,
893 * bridge or CardBus).
894 */
895 int pci_setup_device(struct pci_dev *dev)
896 {
897 u32 class;
898 u8 hdr_type;
899 struct pci_slot *slot;
900 int pos = 0;
901
902 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
903 return -EIO;
904
905 dev->sysdata = dev->bus->sysdata;
906 dev->dev.parent = dev->bus->bridge;
907 dev->dev.bus = &pci_bus_type;
908 dev->hdr_type = hdr_type & 0x7f;
909 dev->multifunction = !!(hdr_type & 0x80);
910 dev->error_state = pci_channel_io_normal;
911 set_pcie_port_type(dev);
912
913 list_for_each_entry(slot, &dev->bus->slots, list)
914 if (PCI_SLOT(dev->devfn) == slot->number)
915 dev->slot = slot;
916
917 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
918 set this higher, assuming the system even supports it. */
919 dev->dma_mask = 0xffffffff;
920
921 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
922 dev->bus->number, PCI_SLOT(dev->devfn),
923 PCI_FUNC(dev->devfn));
924
925 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
926 dev->revision = class & 0xff;
927 class >>= 8; /* upper 3 bytes */
928 dev->class = class;
929 class >>= 8;
930
931 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
932 dev->vendor, dev->device, dev->hdr_type, class);
933
934 /* need to have dev->class ready */
935 dev->cfg_size = pci_cfg_space_size(dev);
936
937 /* "Unknown power state" */
938 dev->current_state = PCI_UNKNOWN;
939
940 /* Early fixups, before probing the BARs */
941 pci_fixup_device(pci_fixup_early, dev);
942 /* device class may be changed after fixup */
943 class = dev->class >> 8;
944
945 switch (dev->hdr_type) { /* header type */
946 case PCI_HEADER_TYPE_NORMAL: /* standard header */
947 if (class == PCI_CLASS_BRIDGE_PCI)
948 goto bad;
949 pci_read_irq(dev);
950 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
951 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
952 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
953
954 /*
955 * Do the ugly legacy mode stuff here rather than broken chip
956 * quirk code. Legacy mode ATA controllers have fixed
957 * addresses. These are not always echoed in BAR0-3, and
958 * BAR0-3 in a few cases contain junk!
959 */
960 if (class == PCI_CLASS_STORAGE_IDE) {
961 u8 progif;
962 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
963 if ((progif & 1) == 0) {
964 dev->resource[0].start = 0x1F0;
965 dev->resource[0].end = 0x1F7;
966 dev->resource[0].flags = LEGACY_IO_RESOURCE;
967 dev->resource[1].start = 0x3F6;
968 dev->resource[1].end = 0x3F6;
969 dev->resource[1].flags = LEGACY_IO_RESOURCE;
970 }
971 if ((progif & 4) == 0) {
972 dev->resource[2].start = 0x170;
973 dev->resource[2].end = 0x177;
974 dev->resource[2].flags = LEGACY_IO_RESOURCE;
975 dev->resource[3].start = 0x376;
976 dev->resource[3].end = 0x376;
977 dev->resource[3].flags = LEGACY_IO_RESOURCE;
978 }
979 }
980 break;
981
982 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
983 if (class != PCI_CLASS_BRIDGE_PCI)
984 goto bad;
985 /* The PCI-to-PCI bridge spec requires that subtractive
986 decoding (i.e. transparent) bridge must have programming
987 interface code of 0x01. */
988 pci_read_irq(dev);
989 dev->transparent = ((dev->class & 0xff) == 1);
990 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
991 set_pcie_hotplug_bridge(dev);
992 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
993 if (pos) {
994 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
995 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
996 }
997 break;
998
999 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1000 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1001 goto bad;
1002 pci_read_irq(dev);
1003 pci_read_bases(dev, 1, 0);
1004 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1005 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1006 break;
1007
1008 default: /* unknown header */
1009 dev_err(&dev->dev, "unknown header type %02x, "
1010 "ignoring device\n", dev->hdr_type);
1011 return -EIO;
1012
1013 bad:
1014 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1015 "type %02x)\n", class, dev->hdr_type);
1016 dev->class = PCI_CLASS_NOT_DEFINED;
1017 }
1018
1019 /* We found a fine healthy device, go go go... */
1020 return 0;
1021 }
1022
1023 static void pci_release_capabilities(struct pci_dev *dev)
1024 {
1025 pci_vpd_release(dev);
1026 pci_iov_release(dev);
1027 }
1028
1029 /**
1030 * pci_release_dev - free a pci device structure when all users of it are finished.
1031 * @dev: device that's been disconnected
1032 *
1033 * Will be called only by the device core when all users of this pci device are
1034 * done.
1035 */
1036 static void pci_release_dev(struct device *dev)
1037 {
1038 struct pci_dev *pci_dev;
1039
1040 pci_dev = to_pci_dev(dev);
1041 pci_release_capabilities(pci_dev);
1042 pci_release_of_node(pci_dev);
1043 kfree(pci_dev);
1044 }
1045
1046 /**
1047 * pci_cfg_space_size - get the configuration space size of the PCI device.
1048 * @dev: PCI device
1049 *
1050 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1051 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1052 * access it. Maybe we don't have a way to generate extended config space
1053 * accesses, or the device is behind a reverse Express bridge. So we try
1054 * reading the dword at 0x100 which must either be 0 or a valid extended
1055 * capability header.
1056 */
1057 int pci_cfg_space_size_ext(struct pci_dev *dev)
1058 {
1059 u32 status;
1060 int pos = PCI_CFG_SPACE_SIZE;
1061
1062 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1063 goto fail;
1064 if (status == 0xffffffff)
1065 goto fail;
1066
1067 return PCI_CFG_SPACE_EXP_SIZE;
1068
1069 fail:
1070 return PCI_CFG_SPACE_SIZE;
1071 }
1072
1073 int pci_cfg_space_size(struct pci_dev *dev)
1074 {
1075 int pos;
1076 u32 status;
1077 u16 class;
1078
1079 class = dev->class >> 8;
1080 if (class == PCI_CLASS_BRIDGE_HOST)
1081 return pci_cfg_space_size_ext(dev);
1082
1083 pos = pci_pcie_cap(dev);
1084 if (!pos) {
1085 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1086 if (!pos)
1087 goto fail;
1088
1089 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1090 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1091 goto fail;
1092 }
1093
1094 return pci_cfg_space_size_ext(dev);
1095
1096 fail:
1097 return PCI_CFG_SPACE_SIZE;
1098 }
1099
1100 static void pci_release_bus_bridge_dev(struct device *dev)
1101 {
1102 kfree(dev);
1103 }
1104
1105 struct pci_dev *alloc_pci_dev(void)
1106 {
1107 struct pci_dev *dev;
1108
1109 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1110 if (!dev)
1111 return NULL;
1112
1113 INIT_LIST_HEAD(&dev->bus_list);
1114
1115 return dev;
1116 }
1117 EXPORT_SYMBOL(alloc_pci_dev);
1118
1119 /*
1120 * Read the config data for a PCI device, sanity-check it
1121 * and fill in the dev structure...
1122 */
1123 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1124 {
1125 struct pci_dev *dev;
1126 u32 l;
1127 int delay = 1;
1128
1129 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1130 return NULL;
1131
1132 /* some broken boards return 0 or ~0 if a slot is empty: */
1133 if (l == 0xffffffff || l == 0x00000000 ||
1134 l == 0x0000ffff || l == 0xffff0000)
1135 return NULL;
1136
1137 /* Configuration request Retry Status */
1138 while (l == 0xffff0001) {
1139 msleep(delay);
1140 delay *= 2;
1141 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1142 return NULL;
1143 /* Card hasn't responded in 60 seconds? Must be stuck. */
1144 if (delay > 60 * 1000) {
1145 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1146 "responding\n", pci_domain_nr(bus),
1147 bus->number, PCI_SLOT(devfn),
1148 PCI_FUNC(devfn));
1149 return NULL;
1150 }
1151 }
1152
1153 dev = alloc_pci_dev();
1154 if (!dev)
1155 return NULL;
1156
1157 dev->bus = bus;
1158 dev->devfn = devfn;
1159 dev->vendor = l & 0xffff;
1160 dev->device = (l >> 16) & 0xffff;
1161
1162 pci_set_of_node(dev);
1163
1164 if (pci_setup_device(dev)) {
1165 kfree(dev);
1166 return NULL;
1167 }
1168
1169 return dev;
1170 }
1171
1172 static void pci_init_capabilities(struct pci_dev *dev)
1173 {
1174 /* MSI/MSI-X list */
1175 pci_msi_init_pci_dev(dev);
1176
1177 /* Buffers for saving PCIe and PCI-X capabilities */
1178 pci_allocate_cap_save_buffers(dev);
1179
1180 /* Power Management */
1181 pci_pm_init(dev);
1182 platform_pci_wakeup_init(dev);
1183
1184 /* Vital Product Data */
1185 pci_vpd_pci22_init(dev);
1186
1187 /* Alternative Routing-ID Forwarding */
1188 pci_enable_ari(dev);
1189
1190 /* Single Root I/O Virtualization */
1191 pci_iov_init(dev);
1192
1193 /* Enable ACS P2P upstream forwarding */
1194 pci_enable_acs(dev);
1195 }
1196
1197 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1198 {
1199 device_initialize(&dev->dev);
1200 dev->dev.release = pci_release_dev;
1201 pci_dev_get(dev);
1202
1203 dev->dev.dma_mask = &dev->dma_mask;
1204 dev->dev.dma_parms = &dev->dma_parms;
1205 dev->dev.coherent_dma_mask = 0xffffffffull;
1206
1207 pci_set_dma_max_seg_size(dev, 65536);
1208 pci_set_dma_seg_boundary(dev, 0xffffffff);
1209
1210 /* Fix up broken headers */
1211 pci_fixup_device(pci_fixup_header, dev);
1212
1213 /* Clear the state_saved flag. */
1214 dev->state_saved = false;
1215
1216 /* Initialize various capabilities */
1217 pci_init_capabilities(dev);
1218
1219 /*
1220 * Add the device to our list of discovered devices
1221 * and the bus list for fixup functions, etc.
1222 */
1223 down_write(&pci_bus_sem);
1224 list_add_tail(&dev->bus_list, &bus->devices);
1225 up_write(&pci_bus_sem);
1226 }
1227
1228 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1229 {
1230 struct pci_dev *dev;
1231
1232 dev = pci_get_slot(bus, devfn);
1233 if (dev) {
1234 pci_dev_put(dev);
1235 return dev;
1236 }
1237
1238 dev = pci_scan_device(bus, devfn);
1239 if (!dev)
1240 return NULL;
1241
1242 pci_device_add(dev, bus);
1243
1244 return dev;
1245 }
1246 EXPORT_SYMBOL(pci_scan_single_device);
1247
1248 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1249 {
1250 u16 cap;
1251 unsigned pos, next_fn;
1252
1253 if (!dev)
1254 return 0;
1255
1256 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1257 if (!pos)
1258 return 0;
1259 pci_read_config_word(dev, pos + 4, &cap);
1260 next_fn = cap >> 8;
1261 if (next_fn <= fn)
1262 return 0;
1263 return next_fn;
1264 }
1265
1266 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1267 {
1268 return (fn + 1) % 8;
1269 }
1270
1271 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1272 {
1273 return 0;
1274 }
1275
1276 static int only_one_child(struct pci_bus *bus)
1277 {
1278 struct pci_dev *parent = bus->self;
1279 if (!parent || !pci_is_pcie(parent))
1280 return 0;
1281 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1282 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1283 return 1;
1284 return 0;
1285 }
1286
1287 /**
1288 * pci_scan_slot - scan a PCI slot on a bus for devices.
1289 * @bus: PCI bus to scan
1290 * @devfn: slot number to scan (must have zero function.)
1291 *
1292 * Scan a PCI slot on the specified PCI bus for devices, adding
1293 * discovered devices to the @bus->devices list. New devices
1294 * will not have is_added set.
1295 *
1296 * Returns the number of new devices found.
1297 */
1298 int pci_scan_slot(struct pci_bus *bus, int devfn)
1299 {
1300 unsigned fn, nr = 0;
1301 struct pci_dev *dev;
1302 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1303
1304 if (only_one_child(bus) && (devfn > 0))
1305 return 0; /* Already scanned the entire slot */
1306
1307 dev = pci_scan_single_device(bus, devfn);
1308 if (!dev)
1309 return 0;
1310 if (!dev->is_added)
1311 nr++;
1312
1313 if (pci_ari_enabled(bus))
1314 next_fn = next_ari_fn;
1315 else if (dev->multifunction)
1316 next_fn = next_trad_fn;
1317
1318 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1319 dev = pci_scan_single_device(bus, devfn + fn);
1320 if (dev) {
1321 if (!dev->is_added)
1322 nr++;
1323 dev->multifunction = 1;
1324 }
1325 }
1326
1327 /* only one slot has pcie device */
1328 if (bus->self && nr)
1329 pcie_aspm_init_link_state(bus->self);
1330
1331 return nr;
1332 }
1333
1334 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1335 {
1336 unsigned int devfn, pass, max = bus->secondary;
1337 struct pci_dev *dev;
1338
1339 dev_dbg(&bus->dev, "scanning bus\n");
1340
1341 /* Go find them, Rover! */
1342 for (devfn = 0; devfn < 0x100; devfn += 8)
1343 pci_scan_slot(bus, devfn);
1344
1345 /* Reserve buses for SR-IOV capability. */
1346 max += pci_iov_bus_range(bus);
1347
1348 /*
1349 * After performing arch-dependent fixup of the bus, look behind
1350 * all PCI-to-PCI bridges on this bus.
1351 */
1352 if (!bus->is_added) {
1353 dev_dbg(&bus->dev, "fixups for bus\n");
1354 pcibios_fixup_bus(bus);
1355 if (pci_is_root_bus(bus))
1356 bus->is_added = 1;
1357 }
1358
1359 for (pass=0; pass < 2; pass++)
1360 list_for_each_entry(dev, &bus->devices, bus_list) {
1361 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1362 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1363 max = pci_scan_bridge(bus, dev, max, pass);
1364 }
1365
1366 /*
1367 * We've scanned the bus and so we know all about what's on
1368 * the other side of any bridges that may be on this bus plus
1369 * any devices.
1370 *
1371 * Return how far we've got finding sub-buses.
1372 */
1373 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1374 return max;
1375 }
1376
1377 struct pci_bus * pci_create_bus(struct device *parent,
1378 int bus, struct pci_ops *ops, void *sysdata)
1379 {
1380 int error;
1381 struct pci_bus *b, *b2;
1382 struct device *dev;
1383
1384 b = pci_alloc_bus();
1385 if (!b)
1386 return NULL;
1387
1388 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1389 if (!dev){
1390 kfree(b);
1391 return NULL;
1392 }
1393
1394 b->sysdata = sysdata;
1395 b->ops = ops;
1396
1397 b2 = pci_find_bus(pci_domain_nr(b), bus);
1398 if (b2) {
1399 /* If we already got to this bus through a different bridge, ignore it */
1400 dev_dbg(&b2->dev, "bus already known\n");
1401 goto err_out;
1402 }
1403
1404 down_write(&pci_bus_sem);
1405 list_add_tail(&b->node, &pci_root_buses);
1406 up_write(&pci_bus_sem);
1407
1408 dev->parent = parent;
1409 dev->release = pci_release_bus_bridge_dev;
1410 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1411 error = device_register(dev);
1412 if (error)
1413 goto dev_reg_err;
1414 b->bridge = get_device(dev);
1415 device_enable_async_suspend(b->bridge);
1416 pci_set_bus_of_node(b);
1417
1418 if (!parent)
1419 set_dev_node(b->bridge, pcibus_to_node(b));
1420
1421 b->dev.class = &pcibus_class;
1422 b->dev.parent = b->bridge;
1423 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1424 error = device_register(&b->dev);
1425 if (error)
1426 goto class_dev_reg_err;
1427
1428 /* Create legacy_io and legacy_mem files for this bus */
1429 pci_create_legacy_files(b);
1430
1431 b->number = b->secondary = bus;
1432 b->resource[0] = &ioport_resource;
1433 b->resource[1] = &iomem_resource;
1434
1435 return b;
1436
1437 class_dev_reg_err:
1438 device_unregister(dev);
1439 dev_reg_err:
1440 down_write(&pci_bus_sem);
1441 list_del(&b->node);
1442 up_write(&pci_bus_sem);
1443 err_out:
1444 kfree(dev);
1445 kfree(b);
1446 return NULL;
1447 }
1448
1449 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1450 int bus, struct pci_ops *ops, void *sysdata)
1451 {
1452 struct pci_bus *b;
1453
1454 b = pci_create_bus(parent, bus, ops, sysdata);
1455 if (b)
1456 b->subordinate = pci_scan_child_bus(b);
1457 return b;
1458 }
1459 EXPORT_SYMBOL(pci_scan_bus_parented);
1460
1461 #ifdef CONFIG_HOTPLUG
1462 /**
1463 * pci_rescan_bus - scan a PCI bus for devices.
1464 * @bus: PCI bus to scan
1465 *
1466 * Scan a PCI bus and child buses for new devices, adds them,
1467 * and enables them.
1468 *
1469 * Returns the max number of subordinate bus discovered.
1470 */
1471 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1472 {
1473 unsigned int max;
1474 struct pci_dev *dev;
1475
1476 max = pci_scan_child_bus(bus);
1477
1478 down_read(&pci_bus_sem);
1479 list_for_each_entry(dev, &bus->devices, bus_list)
1480 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1481 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1482 if (dev->subordinate)
1483 pci_bus_size_bridges(dev->subordinate);
1484 up_read(&pci_bus_sem);
1485
1486 pci_bus_assign_resources(bus);
1487 pci_enable_bridges(bus);
1488 pci_bus_add_devices(bus);
1489
1490 return max;
1491 }
1492 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1493
1494 EXPORT_SYMBOL(pci_add_new_bus);
1495 EXPORT_SYMBOL(pci_scan_slot);
1496 EXPORT_SYMBOL(pci_scan_bridge);
1497 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1498 #endif
1499
1500 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1501 {
1502 const struct pci_dev *a = to_pci_dev(d_a);
1503 const struct pci_dev *b = to_pci_dev(d_b);
1504
1505 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1506 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1507
1508 if (a->bus->number < b->bus->number) return -1;
1509 else if (a->bus->number > b->bus->number) return 1;
1510
1511 if (a->devfn < b->devfn) return -1;
1512 else if (a->devfn > b->devfn) return 1;
1513
1514 return 0;
1515 }
1516
1517 void __init pci_sort_breadthfirst(void)
1518 {
1519 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1520 }
Linux kernel - Deliverables
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