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PCI: drivers/pci/quirks.c: coding-style cleanup
[deliverable/linux.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include "pci.h"
25
26 /* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31 {
32 dev->broken_parity_status = 1; /* This device gives false positives */
33 }
34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
37 /* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39 static void quirk_passive_release(struct pci_dev *dev)
40 {
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54 }
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
56 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
57
58 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA
60 ask them for me please -- Alan
61
62 This appears to be BIOS not version dependent. So presumably there is a
63 chipset level fix */
64 int isa_dma_bridge_buggy;
65 EXPORT_SYMBOL(isa_dma_bridge_buggy);
66
67 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
68 {
69 if (!isa_dma_bridge_buggy) {
70 isa_dma_bridge_buggy=1;
71 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
72 }
73 }
74 /*
75 * Its not totally clear which chipsets are the problematic ones
76 * We know 82C586 and 82C596 variants are affected.
77 */
78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
85
86 int pci_pci_problems;
87 EXPORT_SYMBOL(pci_pci_problems);
88
89 /*
90 * Chipsets where PCI->PCI transfers vanish or hang
91 */
92 static void __devinit quirk_nopcipci(struct pci_dev *dev)
93 {
94 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
95 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
96 pci_pci_problems |= PCIPCI_FAIL;
97 }
98 }
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
101
102 static void __devinit quirk_nopciamd(struct pci_dev *dev)
103 {
104 u8 rev;
105 pci_read_config_byte(dev, 0x08, &rev);
106 if (rev == 0x13) {
107 /* Erratum 24 */
108 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n");
109 pci_pci_problems |= PCIAGP_FAIL;
110 }
111 }
112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
113
114 /*
115 * Triton requires workarounds to be used by the drivers
116 */
117 static void __devinit quirk_triton(struct pci_dev *dev)
118 {
119 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
120 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
121 pci_pci_problems |= PCIPCI_TRITON;
122 }
123 }
124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
128
129 /*
130 * VIA Apollo KT133 needs PCI latency patch
131 * Made according to a windows driver based patch by George E. Breese
132 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
133 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
134 * the info on which Mr Breese based his work.
135 *
136 * Updated based on further information from the site and also on
137 * information provided by VIA
138 */
139 static void quirk_vialatency(struct pci_dev *dev)
140 {
141 struct pci_dev *p;
142 u8 busarb;
143 /* Ok we have a potential problem chipset here. Now see if we have
144 a buggy southbridge */
145
146 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
147 if (p!=NULL) {
148 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
149 /* Check for buggy part revisions */
150 if (p->revision < 0x40 || p->revision > 0x42)
151 goto exit;
152 } else {
153 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
154 if (p==NULL) /* No problem parts */
155 goto exit;
156 /* Check for buggy part revisions */
157 if (p->revision < 0x10 || p->revision > 0x12)
158 goto exit;
159 }
160
161 /*
162 * Ok we have the problem. Now set the PCI master grant to
163 * occur every master grant. The apparent bug is that under high
164 * PCI load (quite common in Linux of course) you can get data
165 * loss when the CPU is held off the bus for 3 bus master requests
166 * This happens to include the IDE controllers....
167 *
168 * VIA only apply this fix when an SB Live! is present but under
169 * both Linux and Windows this isnt enough, and we have seen
170 * corruption without SB Live! but with things like 3 UDMA IDE
171 * controllers. So we ignore that bit of the VIA recommendation..
172 */
173
174 pci_read_config_byte(dev, 0x76, &busarb);
175 /* Set bit 4 and bi 5 of byte 76 to 0x01
176 "Master priority rotation on every PCI master grant */
177 busarb &= ~(1<<5);
178 busarb |= (1<<4);
179 pci_write_config_byte(dev, 0x76, busarb);
180 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
181 exit:
182 pci_dev_put(p);
183 }
184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
187 /* Must restore this on a resume from RAM */
188 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
191
192 /*
193 * VIA Apollo VP3 needs ETBF on BT848/878
194 */
195 static void __devinit quirk_viaetbf(struct pci_dev *dev)
196 {
197 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
198 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
199 pci_pci_problems |= PCIPCI_VIAETBF;
200 }
201 }
202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
203
204 static void __devinit quirk_vsfx(struct pci_dev *dev)
205 {
206 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_VSFX;
209 }
210 }
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
212
213 /*
214 * Ali Magik requires workarounds to be used by the drivers
215 * that DMA to AGP space. Latency must be set to 0xA and triton
216 * workaround applied too
217 * [Info kindly provided by ALi]
218 */
219 static void __init quirk_alimagik(struct pci_dev *dev)
220 {
221 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
222 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
223 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
224 }
225 }
226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
228
229 /*
230 * Natoma has some interesting boundary conditions with Zoran stuff
231 * at least
232 */
233 static void __devinit quirk_natoma(struct pci_dev *dev)
234 {
235 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
236 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
237 pci_pci_problems |= PCIPCI_NATOMA;
238 }
239 }
240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
246
247 /*
248 * This chip can cause PCI parity errors if config register 0xA0 is read
249 * while DMAs are occurring.
250 */
251 static void __devinit quirk_citrine(struct pci_dev *dev)
252 {
253 dev->cfg_size = 0xA0;
254 }
255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
256
257 /*
258 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
259 * If it's needed, re-allocate the region.
260 */
261 static void __devinit quirk_s3_64M(struct pci_dev *dev)
262 {
263 struct resource *r = &dev->resource[0];
264
265 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
266 r->start = 0;
267 r->end = 0x3ffffff;
268 }
269 }
270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
272
273 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
274 unsigned size, int nr, const char *name)
275 {
276 region &= ~(size-1);
277 if (region) {
278 struct pci_bus_region bus_region;
279 struct resource *res = dev->resource + nr;
280
281 res->name = pci_name(dev);
282 res->start = region;
283 res->end = region + size - 1;
284 res->flags = IORESOURCE_IO;
285
286 /* Convert from PCI bus to resource space. */
287 bus_region.start = res->start;
288 bus_region.end = res->end;
289 pcibios_bus_to_resource(dev, res, &bus_region);
290
291 pci_claim_resource(dev, nr);
292 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
293 }
294 }
295
296 /*
297 * ATI Northbridge setups MCE the processor if you even
298 * read somewhere between 0x3b0->0x3bb or read 0x3d3
299 */
300 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
301 {
302 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
303 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
304 request_region(0x3b0, 0x0C, "RadeonIGP");
305 request_region(0x3d3, 0x01, "RadeonIGP");
306 }
307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
308
309 /*
310 * Let's make the southbridge information explicit instead
311 * of having to worry about people probing the ACPI areas,
312 * for example.. (Yes, it happens, and if you read the wrong
313 * ACPI register it will put the machine to sleep with no
314 * way of waking it up again. Bummer).
315 *
316 * ALI M7101: Two IO regions pointed to by words at
317 * 0xE0 (64 bytes of ACPI registers)
318 * 0xE2 (32 bytes of SMB registers)
319 */
320 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
321 {
322 u16 region;
323
324 pci_read_config_word(dev, 0xE0, &region);
325 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
326 pci_read_config_word(dev, 0xE2, &region);
327 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
328 }
329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
330
331 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
332 {
333 u32 devres;
334 u32 mask, size, base;
335
336 pci_read_config_dword(dev, port, &devres);
337 if ((devres & enable) != enable)
338 return;
339 mask = (devres >> 16) & 15;
340 base = devres & 0xffff;
341 size = 16;
342 for (;;) {
343 unsigned bit = size >> 1;
344 if ((bit & mask) == bit)
345 break;
346 size = bit;
347 }
348 /*
349 * For now we only print it out. Eventually we'll want to
350 * reserve it (at least if it's in the 0x1000+ range), but
351 * let's get enough confirmation reports first.
352 */
353 base &= -size;
354 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
355 }
356
357 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
358 {
359 u32 devres;
360 u32 mask, size, base;
361
362 pci_read_config_dword(dev, port, &devres);
363 if ((devres & enable) != enable)
364 return;
365 base = devres & 0xffff0000;
366 mask = (devres & 0x3f) << 16;
367 size = 128 << 16;
368 for (;;) {
369 unsigned bit = size >> 1;
370 if ((bit & mask) == bit)
371 break;
372 size = bit;
373 }
374 /*
375 * For now we only print it out. Eventually we'll want to
376 * reserve it, but let's get enough confirmation reports first.
377 */
378 base &= -size;
379 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
380 }
381
382 /*
383 * PIIX4 ACPI: Two IO regions pointed to by longwords at
384 * 0x40 (64 bytes of ACPI registers)
385 * 0x90 (16 bytes of SMB registers)
386 * and a few strange programmable PIIX4 device resources.
387 */
388 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
389 {
390 u32 region, res_a;
391
392 pci_read_config_dword(dev, 0x40, &region);
393 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
394 pci_read_config_dword(dev, 0x90, &region);
395 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
396
397 /* Device resource A has enables for some of the other ones */
398 pci_read_config_dword(dev, 0x5c, &res_a);
399
400 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
401 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
402
403 /* Device resource D is just bitfields for static resources */
404
405 /* Device 12 enabled? */
406 if (res_a & (1 << 29)) {
407 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
408 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
409 }
410 /* Device 13 enabled? */
411 if (res_a & (1 << 30)) {
412 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
413 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
414 }
415 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
416 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
417 }
418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
420
421 /*
422 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
423 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
424 * 0x58 (64 bytes of GPIO I/O space)
425 */
426 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
427 {
428 u32 region;
429
430 pci_read_config_dword(dev, 0x40, &region);
431 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
432
433 pci_read_config_dword(dev, 0x58, &region);
434 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
435 }
436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
446
447 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
448 {
449 u32 region;
450
451 pci_read_config_dword(dev, 0x40, &region);
452 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
453
454 pci_read_config_dword(dev, 0x48, &region);
455 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
456 }
457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
471
472 /*
473 * VIA ACPI: One IO region pointed to by longword at
474 * 0x48 or 0x20 (256 bytes of ACPI registers)
475 */
476 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
477 {
478 u32 region;
479
480 if (dev->revision & 0x10) {
481 pci_read_config_dword(dev, 0x48, &region);
482 region &= PCI_BASE_ADDRESS_IO_MASK;
483 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
484 }
485 }
486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
487
488 /*
489 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
490 * 0x48 (256 bytes of ACPI registers)
491 * 0x70 (128 bytes of hardware monitoring register)
492 * 0x90 (16 bytes of SMB registers)
493 */
494 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
495 {
496 u16 hm;
497 u32 smb;
498
499 quirk_vt82c586_acpi(dev);
500
501 pci_read_config_word(dev, 0x70, &hm);
502 hm &= PCI_BASE_ADDRESS_IO_MASK;
503 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
504
505 pci_read_config_dword(dev, 0x90, &smb);
506 smb &= PCI_BASE_ADDRESS_IO_MASK;
507 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
508 }
509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
510
511 /*
512 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
513 * 0x88 (128 bytes of power management registers)
514 * 0xd0 (16 bytes of SMB registers)
515 */
516 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
517 {
518 u16 pm, smb;
519
520 pci_read_config_word(dev, 0x88, &pm);
521 pm &= PCI_BASE_ADDRESS_IO_MASK;
522 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
523
524 pci_read_config_word(dev, 0xd0, &smb);
525 smb &= PCI_BASE_ADDRESS_IO_MASK;
526 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
527 }
528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
529
530
531 #ifdef CONFIG_X86_IO_APIC
532
533 #include <asm/io_apic.h>
534
535 /*
536 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
537 * devices to the external APIC.
538 *
539 * TODO: When we have device-specific interrupt routers,
540 * this code will go away from quirks.
541 */
542 static void quirk_via_ioapic(struct pci_dev *dev)
543 {
544 u8 tmp;
545
546 if (nr_ioapics < 1)
547 tmp = 0; /* nothing routed to external APIC */
548 else
549 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
550
551 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
552 tmp == 0 ? "Disa" : "Ena");
553
554 /* Offset 0x58: External APIC IRQ output control */
555 pci_write_config_byte (dev, 0x58, tmp);
556 }
557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
558 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
559
560 /*
561 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
562 * This leads to doubled level interrupt rates.
563 * Set this bit to get rid of cycle wastage.
564 * Otherwise uncritical.
565 */
566 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
567 {
568 u8 misc_control2;
569 #define BYPASS_APIC_DEASSERT 8
570
571 pci_read_config_byte(dev, 0x5B, &misc_control2);
572 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
573 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
574 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
575 }
576 }
577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
578 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
579
580 /*
581 * The AMD io apic can hang the box when an apic irq is masked.
582 * We check all revs >= B0 (yet not in the pre production!) as the bug
583 * is currently marked NoFix
584 *
585 * We have multiple reports of hangs with this chipset that went away with
586 * noapic specified. For the moment we assume it's the erratum. We may be wrong
587 * of course. However the advice is demonstrably good even if so..
588 */
589 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
590 {
591 if (dev->revision >= 0x02) {
592 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
593 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
594 }
595 }
596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
597
598 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
599 {
600 if (dev->devfn == 0 && dev->bus->number == 0)
601 sis_apic_bug = 1;
602 }
603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
604
605 #define AMD8131_revA0 0x01
606 #define AMD8131_revB0 0x11
607 #define AMD8131_MISC 0x40
608 #define AMD8131_NIOAMODE_BIT 0
609 static void quirk_amd_8131_ioapic(struct pci_dev *dev)
610 {
611 unsigned char tmp;
612
613 if (nr_ioapics == 0)
614 return;
615
616 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
617 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
618 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
619 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
620 pci_write_config_byte( dev, AMD8131_MISC, tmp);
621 }
622 }
623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
624 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
625 #endif /* CONFIG_X86_IO_APIC */
626
627 /*
628 * Some settings of MMRBC can lead to data corruption so block changes.
629 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
630 */
631 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
632 {
633 if (dev->subordinate && dev->revision <= 0x12) {
634 printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X "
635 "MMRBC\n", dev->revision);
636 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
637 }
638 }
639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
640
641 /*
642 * FIXME: it is questionable that quirk_via_acpi
643 * is needed. It shows up as an ISA bridge, and does not
644 * support the PCI_INTERRUPT_LINE register at all. Therefore
645 * it seems like setting the pci_dev's 'irq' to the
646 * value of the ACPI SCI interrupt is only done for convenience.
647 * -jgarzik
648 */
649 static void __devinit quirk_via_acpi(struct pci_dev *d)
650 {
651 /*
652 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
653 */
654 u8 irq;
655 pci_read_config_byte(d, 0x42, &irq);
656 irq &= 0xf;
657 if (irq && (irq != 2))
658 d->irq = irq;
659 }
660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
662
663
664 /*
665 * VIA bridges which have VLink
666 */
667
668 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
669
670 static void quirk_via_bridge(struct pci_dev *dev)
671 {
672 /* See what bridge we have and find the device ranges */
673 switch (dev->device) {
674 case PCI_DEVICE_ID_VIA_82C686:
675 /* The VT82C686 is special, it attaches to PCI and can have
676 any device number. All its subdevices are functions of
677 that single device. */
678 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
679 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
680 break;
681 case PCI_DEVICE_ID_VIA_8237:
682 case PCI_DEVICE_ID_VIA_8237A:
683 via_vlink_dev_lo = 15;
684 break;
685 case PCI_DEVICE_ID_VIA_8235:
686 via_vlink_dev_lo = 16;
687 break;
688 case PCI_DEVICE_ID_VIA_8231:
689 case PCI_DEVICE_ID_VIA_8233_0:
690 case PCI_DEVICE_ID_VIA_8233A:
691 case PCI_DEVICE_ID_VIA_8233C_0:
692 via_vlink_dev_lo = 17;
693 break;
694 }
695 }
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
704
705 /**
706 * quirk_via_vlink - VIA VLink IRQ number update
707 * @dev: PCI device
708 *
709 * If the device we are dealing with is on a PIC IRQ we need to
710 * ensure that the IRQ line register which usually is not relevant
711 * for PCI cards, is actually written so that interrupts get sent
712 * to the right place.
713 * We only do this on systems where a VIA south bridge was detected,
714 * and only for VIA devices on the motherboard (see quirk_via_bridge
715 * above).
716 */
717
718 static void quirk_via_vlink(struct pci_dev *dev)
719 {
720 u8 irq, new_irq;
721
722 /* Check if we have VLink at all */
723 if (via_vlink_dev_lo == -1)
724 return;
725
726 new_irq = dev->irq;
727
728 /* Don't quirk interrupts outside the legacy IRQ range */
729 if (!new_irq || new_irq > 15)
730 return;
731
732 /* Internal device ? */
733 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
734 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
735 return;
736
737 /* This is an internal VLink device on a PIC interrupt. The BIOS
738 ought to have set this but may not have, so we redo it */
739
740 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
741 if (new_irq != irq) {
742 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n",
743 pci_name(dev), irq, new_irq);
744 udelay(15); /* unknown if delay really needed */
745 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
746 }
747 }
748 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
749
750 /*
751 * VIA VT82C598 has its device ID settable and many BIOSes
752 * set it to the ID of VT82C597 for backward compatibility.
753 * We need to switch it off to be able to recognize the real
754 * type of the chip.
755 */
756 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
757 {
758 pci_write_config_byte(dev, 0xfc, 0);
759 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
760 }
761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
762
763 /*
764 * CardBus controllers have a legacy base address that enables them
765 * to respond as i82365 pcmcia controllers. We don't want them to
766 * do this even if the Linux CardBus driver is not loaded, because
767 * the Linux i82365 driver does not (and should not) handle CardBus.
768 */
769 static void quirk_cardbus_legacy(struct pci_dev *dev)
770 {
771 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
772 return;
773 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
774 }
775 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
776 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
777
778 /*
779 * Following the PCI ordering rules is optional on the AMD762. I'm not
780 * sure what the designers were smoking but let's not inhale...
781 *
782 * To be fair to AMD, it follows the spec by default, its BIOS people
783 * who turn it off!
784 */
785 static void quirk_amd_ordering(struct pci_dev *dev)
786 {
787 u32 pcic;
788 pci_read_config_dword(dev, 0x4C, &pcic);
789 if ((pcic&6)!=6) {
790 pcic |= 6;
791 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
792 pci_write_config_dword(dev, 0x4C, pcic);
793 pci_read_config_dword(dev, 0x84, &pcic);
794 pcic |= (1<<23); /* Required in this mode */
795 pci_write_config_dword(dev, 0x84, pcic);
796 }
797 }
798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
799 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
800
801 /*
802 * DreamWorks provided workaround for Dunord I-3000 problem
803 *
804 * This card decodes and responds to addresses not apparently
805 * assigned to it. We force a larger allocation to ensure that
806 * nothing gets put too close to it.
807 */
808 static void __devinit quirk_dunord ( struct pci_dev * dev )
809 {
810 struct resource *r = &dev->resource [1];
811 r->start = 0;
812 r->end = 0xffffff;
813 }
814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
815
816 /*
817 * i82380FB mobile docking controller: its PCI-to-PCI bridge
818 * is subtractive decoding (transparent), and does indicate this
819 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
820 * instead of 0x01.
821 */
822 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
823 {
824 dev->transparent = 1;
825 }
826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
828
829 /*
830 * Common misconfiguration of the MediaGX/Geode PCI master that will
831 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
832 * datasheets found at http://www.national.com/ds/GX for info on what
833 * these bits do. <christer@weinigel.se>
834 */
835 static void quirk_mediagx_master(struct pci_dev *dev)
836 {
837 u8 reg;
838 pci_read_config_byte(dev, 0x41, &reg);
839 if (reg & 2) {
840 reg &= ~2;
841 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
842 pci_write_config_byte(dev, 0x41, reg);
843 }
844 }
845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
846 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
847
848 /*
849 * Ensure C0 rev restreaming is off. This is normally done by
850 * the BIOS but in the odd case it is not the results are corruption
851 * hence the presence of a Linux check
852 */
853 static void quirk_disable_pxb(struct pci_dev *pdev)
854 {
855 u16 config;
856
857 if (pdev->revision != 0x04) /* Only C0 requires this */
858 return;
859 pci_read_config_word(pdev, 0x40, &config);
860 if (config & (1<<6)) {
861 config &= ~(1<<6);
862 pci_write_config_word(pdev, 0x40, config);
863 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
864 }
865 }
866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
867 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
868
869
870 static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
871 {
872 /* set sb600 sata to ahci mode */
873 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
874 u8 tmp;
875
876 pci_read_config_byte(pdev, 0x40, &tmp);
877 pci_write_config_byte(pdev, 0x40, tmp|1);
878 pci_write_config_byte(pdev, 0x9, 1);
879 pci_write_config_byte(pdev, 0xa, 6);
880 pci_write_config_byte(pdev, 0x40, tmp);
881
882 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
883 }
884 }
885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata);
886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata);
887
888 /*
889 * Serverworks CSB5 IDE does not fully support native mode
890 */
891 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
892 {
893 u8 prog;
894 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
895 if (prog & 5) {
896 prog &= ~5;
897 pdev->class &= ~5;
898 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
899 /* PCI layer will sort out resources */
900 }
901 }
902 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
903
904 /*
905 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
906 */
907 static void __init quirk_ide_samemode(struct pci_dev *pdev)
908 {
909 u8 prog;
910
911 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
912
913 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
914 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
915 prog &= ~5;
916 pdev->class &= ~5;
917 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
918 }
919 }
920 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
921
922 /* This was originally an Alpha specific thing, but it really fits here.
923 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
924 */
925 static void __init quirk_eisa_bridge(struct pci_dev *dev)
926 {
927 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
928 }
929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
930
931
932 /*
933 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
934 * is not activated. The myth is that Asus said that they do not want the
935 * users to be irritated by just another PCI Device in the Win98 device
936 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
937 * package 2.7.0 for details)
938 *
939 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
940 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
941 * becomes necessary to do this tweak in two steps -- the chosen trigger
942 * is either the Host bridge (preferred) or on-board VGA controller.
943 *
944 * Note that we used to unhide the SMBus that way on Toshiba laptops
945 * (Satellite A40 and Tecra M2) but then found that the thermal management
946 * was done by SMM code, which could cause unsynchronized concurrent
947 * accesses to the SMBus registers, with potentially bad effects. Thus you
948 * should be very careful when adding new entries: if SMM is accessing the
949 * Intel SMBus, this is a very good reason to leave it hidden.
950 */
951 static int asus_hides_smbus;
952
953 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
954 {
955 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
956 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
957 switch(dev->subsystem_device) {
958 case 0x8025: /* P4B-LX */
959 case 0x8070: /* P4B */
960 case 0x8088: /* P4B533 */
961 case 0x1626: /* L3C notebook */
962 asus_hides_smbus = 1;
963 }
964 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
965 switch(dev->subsystem_device) {
966 case 0x80b1: /* P4GE-V */
967 case 0x80b2: /* P4PE */
968 case 0x8093: /* P4B533-V */
969 asus_hides_smbus = 1;
970 }
971 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
972 switch(dev->subsystem_device) {
973 case 0x8030: /* P4T533 */
974 asus_hides_smbus = 1;
975 }
976 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
977 switch (dev->subsystem_device) {
978 case 0x8070: /* P4G8X Deluxe */
979 asus_hides_smbus = 1;
980 }
981 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
982 switch (dev->subsystem_device) {
983 case 0x80c9: /* PU-DLS */
984 asus_hides_smbus = 1;
985 }
986 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
987 switch (dev->subsystem_device) {
988 case 0x1751: /* M2N notebook */
989 case 0x1821: /* M5N notebook */
990 asus_hides_smbus = 1;
991 }
992 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
993 switch (dev->subsystem_device) {
994 case 0x184b: /* W1N notebook */
995 case 0x186a: /* M6Ne notebook */
996 asus_hides_smbus = 1;
997 }
998 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
999 switch (dev->subsystem_device) {
1000 case 0x80f2: /* P4P800-X */
1001 asus_hides_smbus = 1;
1002 }
1003 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1004 switch (dev->subsystem_device) {
1005 case 0x1882: /* M6V notebook */
1006 case 0x1977: /* A6VA notebook */
1007 asus_hides_smbus = 1;
1008 }
1009 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1010 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1011 switch(dev->subsystem_device) {
1012 case 0x088C: /* HP Compaq nc8000 */
1013 case 0x0890: /* HP Compaq nc6000 */
1014 asus_hides_smbus = 1;
1015 }
1016 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1017 switch (dev->subsystem_device) {
1018 case 0x12bc: /* HP D330L */
1019 case 0x12bd: /* HP D530 */
1020 asus_hides_smbus = 1;
1021 }
1022 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1023 switch (dev->subsystem_device) {
1024 case 0x099c: /* HP Compaq nx6110 */
1025 asus_hides_smbus = 1;
1026 }
1027 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1028 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1029 switch(dev->subsystem_device) {
1030 case 0xC00C: /* Samsung P35 notebook */
1031 asus_hides_smbus = 1;
1032 }
1033 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1034 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1035 switch(dev->subsystem_device) {
1036 case 0x0058: /* Compaq Evo N620c */
1037 asus_hides_smbus = 1;
1038 }
1039 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1040 switch(dev->subsystem_device) {
1041 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1042 /* Motherboard doesn't have Host bridge
1043 * subvendor/subdevice IDs, therefore checking
1044 * its on-board VGA controller */
1045 asus_hides_smbus = 1;
1046 }
1047 }
1048 }
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1058
1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1060
1061 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1062 {
1063 u16 val;
1064
1065 if (likely(!asus_hides_smbus))
1066 return;
1067
1068 pci_read_config_word(dev, 0xF2, &val);
1069 if (val & 0x8) {
1070 pci_write_config_word(dev, 0xF2, val & (~0x8));
1071 pci_read_config_word(dev, 0xF2, &val);
1072 if (val & 0x8)
1073 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1074 else
1075 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1076 }
1077 }
1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1085 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1086 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1087 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1088 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1089 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1090 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1091 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1092
1093 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1094 {
1095 u32 val, rcba;
1096 void __iomem *base;
1097
1098 if (likely(!asus_hides_smbus))
1099 return;
1100 pci_read_config_dword(dev, 0xF0, &rcba);
1101 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1102 if (base == NULL) return;
1103 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1104 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1105 iounmap(base);
1106 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1107 }
1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1109 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1110
1111 /*
1112 * SiS 96x south bridge: BIOS typically hides SMBus device...
1113 */
1114 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1115 {
1116 u8 val = 0;
1117 pci_read_config_byte(dev, 0x77, &val);
1118 if (val & 0x10) {
1119 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1120 pci_write_config_byte(dev, 0x77, val & ~0x10);
1121 }
1122 }
1123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1127 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1128 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1129 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1130 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1131
1132 /*
1133 * ... This is further complicated by the fact that some SiS96x south
1134 * bridges pretend to be 85C503/5513 instead. In that case see if we
1135 * spotted a compatible north bridge to make sure.
1136 * (pci_find_device doesn't work yet)
1137 *
1138 * We can also enable the sis96x bit in the discovery register..
1139 */
1140 #define SIS_DETECT_REGISTER 0x40
1141
1142 static void quirk_sis_503(struct pci_dev *dev)
1143 {
1144 u8 reg;
1145 u16 devid;
1146
1147 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1148 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1149 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1150 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1151 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1152 return;
1153 }
1154
1155 /*
1156 * Ok, it now shows up as a 96x.. run the 96x quirk by
1157 * hand in case it has already been processed.
1158 * (depends on link order, which is apparently not guaranteed)
1159 */
1160 dev->device = devid;
1161 quirk_sis_96x_smbus(dev);
1162 }
1163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1164 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1165
1166
1167 /*
1168 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1169 * and MC97 modem controller are disabled when a second PCI soundcard is
1170 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1171 * -- bjd
1172 */
1173 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1174 {
1175 u8 val;
1176 int asus_hides_ac97 = 0;
1177
1178 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1179 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1180 asus_hides_ac97 = 1;
1181 }
1182
1183 if (!asus_hides_ac97)
1184 return;
1185
1186 pci_read_config_byte(dev, 0x50, &val);
1187 if (val & 0xc0) {
1188 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1189 pci_read_config_byte(dev, 0x50, &val);
1190 if (val & 0xc0)
1191 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1192 else
1193 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1194 }
1195 }
1196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1197 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1198
1199 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1200
1201 /*
1202 * If we are using libata we can drive this chip properly but must
1203 * do this early on to make the additional device appear during
1204 * the PCI scanning.
1205 */
1206 static void quirk_jmicron_ata(struct pci_dev *pdev)
1207 {
1208 u32 conf1, conf5, class;
1209 u8 hdr;
1210
1211 /* Only poke fn 0 */
1212 if (PCI_FUNC(pdev->devfn))
1213 return;
1214
1215 pci_read_config_dword(pdev, 0x40, &conf1);
1216 pci_read_config_dword(pdev, 0x80, &conf5);
1217
1218 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1219 conf5 &= ~(1 << 24); /* Clear bit 24 */
1220
1221 switch (pdev->device) {
1222 case PCI_DEVICE_ID_JMICRON_JMB360:
1223 /* The controller should be in single function ahci mode */
1224 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1225 break;
1226
1227 case PCI_DEVICE_ID_JMICRON_JMB365:
1228 case PCI_DEVICE_ID_JMICRON_JMB366:
1229 /* Redirect IDE second PATA port to the right spot */
1230 conf5 |= (1 << 24);
1231 /* Fall through */
1232 case PCI_DEVICE_ID_JMICRON_JMB361:
1233 case PCI_DEVICE_ID_JMICRON_JMB363:
1234 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1235 /* Set the class codes correctly and then direct IDE 0 */
1236 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1237 break;
1238
1239 case PCI_DEVICE_ID_JMICRON_JMB368:
1240 /* The controller should be in single function IDE mode */
1241 conf1 |= 0x00C00000; /* Set 22, 23 */
1242 break;
1243 }
1244
1245 pci_write_config_dword(pdev, 0x40, conf1);
1246 pci_write_config_dword(pdev, 0x80, conf5);
1247
1248 /* Update pdev accordingly */
1249 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1250 pdev->hdr_type = hdr & 0x7f;
1251 pdev->multifunction = !!(hdr & 0x80);
1252
1253 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1254 pdev->class = class >> 8;
1255 }
1256 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1257 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1258 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1259 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1260 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1261 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1262 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1263 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1264 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1265 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1266 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1267 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1268
1269 #endif
1270
1271 #ifdef CONFIG_X86_IO_APIC
1272 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1273 {
1274 int i;
1275
1276 if ((pdev->class >> 8) != 0xff00)
1277 return;
1278
1279 /* the first BAR is the location of the IO APIC...we must
1280 * not touch this (and it's already covered by the fixmap), so
1281 * forcibly insert it into the resource tree */
1282 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1283 insert_resource(&iomem_resource, &pdev->resource[0]);
1284
1285 /* The next five BARs all seem to be rubbish, so just clean
1286 * them out */
1287 for (i=1; i < 6; i++) {
1288 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1289 }
1290
1291 }
1292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1293 #endif
1294
1295 int pcie_mch_quirk;
1296 EXPORT_SYMBOL(pcie_mch_quirk);
1297
1298 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1299 {
1300 pcie_mch_quirk = 1;
1301 }
1302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1305
1306
1307 /*
1308 * It's possible for the MSI to get corrupted if shpc and acpi
1309 * are used together on certain PXH-based systems.
1310 */
1311 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1312 {
1313 pci_msi_off(dev);
1314
1315 dev->no_msi = 1;
1316
1317 printk(KERN_WARNING "PCI: PXH quirk detected, "
1318 "disabling MSI for SHPC device\n");
1319 }
1320 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1321 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1322 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1323 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1324 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1325
1326 /*
1327 * Some Intel PCI Express chipsets have trouble with downstream
1328 * device power management.
1329 */
1330 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1331 {
1332 pci_pm_d3_delay = 120;
1333 dev->no_d1d2 = 1;
1334 }
1335
1336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1357
1358 /*
1359 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1360 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1361 * Re-allocate the region if needed...
1362 */
1363 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1364 {
1365 struct resource *r = &dev->resource[0];
1366
1367 if (r->start & 0x8) {
1368 r->start = 0;
1369 r->end = 0xf;
1370 }
1371 }
1372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1373 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1374 quirk_tc86c001_ide);
1375
1376 static void __devinit quirk_netmos(struct pci_dev *dev)
1377 {
1378 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1379 unsigned int num_serial = dev->subsystem_device & 0xf;
1380
1381 /*
1382 * These Netmos parts are multiport serial devices with optional
1383 * parallel ports. Even when parallel ports are present, they
1384 * are identified as class SERIAL, which means the serial driver
1385 * will claim them. To prevent this, mark them as class OTHER.
1386 * These combo devices should be claimed by parport_serial.
1387 *
1388 * The subdevice ID is of the form 0x00PS, where <P> is the number
1389 * of parallel ports and <S> is the number of serial ports.
1390 */
1391 switch (dev->device) {
1392 case PCI_DEVICE_ID_NETMOS_9735:
1393 case PCI_DEVICE_ID_NETMOS_9745:
1394 case PCI_DEVICE_ID_NETMOS_9835:
1395 case PCI_DEVICE_ID_NETMOS_9845:
1396 case PCI_DEVICE_ID_NETMOS_9855:
1397 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1398 num_parallel) {
1399 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1400 "%u serial); changing class SERIAL to OTHER "
1401 "(use parport_serial)\n",
1402 dev->device, num_parallel, num_serial);
1403 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1404 (dev->class & 0xff);
1405 }
1406 }
1407 }
1408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1409
1410 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1411 {
1412 u16 command;
1413 u8 __iomem *csr;
1414 u8 cmd_hi;
1415
1416 switch (dev->device) {
1417 /* PCI IDs taken from drivers/net/e100.c */
1418 case 0x1029:
1419 case 0x1030 ... 0x1034:
1420 case 0x1038 ... 0x103E:
1421 case 0x1050 ... 0x1057:
1422 case 0x1059:
1423 case 0x1064 ... 0x106B:
1424 case 0x1091 ... 0x1095:
1425 case 0x1209:
1426 case 0x1229:
1427 case 0x2449:
1428 case 0x2459:
1429 case 0x245D:
1430 case 0x27DC:
1431 break;
1432 default:
1433 return;
1434 }
1435
1436 /*
1437 * Some firmware hands off the e100 with interrupts enabled,
1438 * which can cause a flood of interrupts if packets are
1439 * received before the driver attaches to the device. So
1440 * disable all e100 interrupts here. The driver will
1441 * re-enable them when it's ready.
1442 */
1443 pci_read_config_word(dev, PCI_COMMAND, &command);
1444
1445 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1446 return;
1447
1448 /* Convert from PCI bus to resource space. */
1449 csr = ioremap(pci_resource_start(dev, 0), 8);
1450 if (!csr) {
1451 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1452 pci_name(dev));
1453 return;
1454 }
1455
1456 cmd_hi = readb(csr + 3);
1457 if (cmd_hi == 0) {
1458 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1459 "enabled, disabling\n", pci_name(dev));
1460 writeb(1, csr + 3);
1461 }
1462
1463 iounmap(csr);
1464 }
1465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1466
1467 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1468 {
1469 /* rev 1 ncr53c810 chips don't set the class at all which means
1470 * they don't get their resources remapped. Fix that here.
1471 */
1472
1473 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1474 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1475 dev->class = PCI_CLASS_STORAGE_SCSI;
1476 }
1477 }
1478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1479
1480 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1481 {
1482 while (f < end) {
1483 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1484 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1485 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1486 f->hook(dev);
1487 }
1488 f++;
1489 }
1490 }
1491
1492 extern struct pci_fixup __start_pci_fixups_early[];
1493 extern struct pci_fixup __end_pci_fixups_early[];
1494 extern struct pci_fixup __start_pci_fixups_header[];
1495 extern struct pci_fixup __end_pci_fixups_header[];
1496 extern struct pci_fixup __start_pci_fixups_final[];
1497 extern struct pci_fixup __end_pci_fixups_final[];
1498 extern struct pci_fixup __start_pci_fixups_enable[];
1499 extern struct pci_fixup __end_pci_fixups_enable[];
1500 extern struct pci_fixup __start_pci_fixups_resume[];
1501 extern struct pci_fixup __end_pci_fixups_resume[];
1502
1503
1504 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1505 {
1506 struct pci_fixup *start, *end;
1507
1508 switch(pass) {
1509 case pci_fixup_early:
1510 start = __start_pci_fixups_early;
1511 end = __end_pci_fixups_early;
1512 break;
1513
1514 case pci_fixup_header:
1515 start = __start_pci_fixups_header;
1516 end = __end_pci_fixups_header;
1517 break;
1518
1519 case pci_fixup_final:
1520 start = __start_pci_fixups_final;
1521 end = __end_pci_fixups_final;
1522 break;
1523
1524 case pci_fixup_enable:
1525 start = __start_pci_fixups_enable;
1526 end = __end_pci_fixups_enable;
1527 break;
1528
1529 case pci_fixup_resume:
1530 start = __start_pci_fixups_resume;
1531 end = __end_pci_fixups_resume;
1532 break;
1533
1534 default:
1535 /* stupid compiler warning, you would think with an enum... */
1536 return;
1537 }
1538 pci_do_fixups(dev, start, end);
1539 }
1540 EXPORT_SYMBOL(pci_fixup_device);
1541
1542 /* Enable 1k I/O space granularity on the Intel P64H2 */
1543 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1544 {
1545 u16 en1k;
1546 u8 io_base_lo, io_limit_lo;
1547 unsigned long base, limit;
1548 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1549
1550 pci_read_config_word(dev, 0x40, &en1k);
1551
1552 if (en1k & 0x200) {
1553 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1554
1555 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1556 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1557 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1558 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1559
1560 if (base <= limit) {
1561 res->start = base;
1562 res->end = limit + 0x3ff;
1563 }
1564 }
1565 }
1566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1567
1568 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1569 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1570 * in drivers/pci/setup-bus.c
1571 */
1572 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1573 {
1574 u16 en1k, iobl_adr, iobl_adr_1k;
1575 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1576
1577 pci_read_config_word(dev, 0x40, &en1k);
1578
1579 if (en1k & 0x200) {
1580 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1581
1582 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1583
1584 if (iobl_adr != iobl_adr_1k) {
1585 printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n",
1586 iobl_adr,iobl_adr_1k);
1587 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1588 }
1589 }
1590 }
1591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1592
1593 /* Under some circumstances, AER is not linked with extended capabilities.
1594 * Force it to be linked by setting the corresponding control bit in the
1595 * config space.
1596 */
1597 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1598 {
1599 uint8_t b;
1600 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1601 if (!(b & 0x20)) {
1602 pci_write_config_byte(dev, 0xf41, b | 0x20);
1603 printk(KERN_INFO
1604 "PCI: Linking AER extended capability on %s\n",
1605 pci_name(dev));
1606 }
1607 }
1608 }
1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1610 quirk_nvidia_ck804_pcie_aer_ext_cap);
1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1612 quirk_nvidia_ck804_pcie_aer_ext_cap);
1613
1614 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1615 {
1616 /*
1617 * Disable PCI Bus Parking and PCI Master read caching on CX700
1618 * which causes unspecified timing errors with a VT6212L on the PCI
1619 * bus leading to USB2.0 packet loss. The defaults are that these
1620 * features are turned off but some BIOSes turn them on.
1621 */
1622
1623 uint8_t b;
1624 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1625 if (b & 0x40) {
1626 /* Turn off PCI Bus Parking */
1627 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1628
1629 /* Turn off PCI Master read caching */
1630 pci_write_config_byte(dev, 0x72, 0x0);
1631 pci_write_config_byte(dev, 0x75, 0x1);
1632 pci_write_config_byte(dev, 0x77, 0x0);
1633
1634 printk(KERN_INFO
1635 "PCI: VIA CX700 PCI parking/caching fixup on %s\n",
1636 pci_name(dev));
1637 }
1638 }
1639 }
1640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1641
1642 #ifdef CONFIG_PCI_MSI
1643 /* Some chipsets do not support MSI. We cannot easily rely on setting
1644 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1645 * some other busses controlled by the chipset even if Linux is not
1646 * aware of it. Instead of setting the flag on all busses in the
1647 * machine, simply disable MSI globally.
1648 */
1649 static void __init quirk_disable_all_msi(struct pci_dev *dev)
1650 {
1651 pci_no_msi();
1652 printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n");
1653 }
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1658
1659 /* Disable MSI on chipsets that are known to not support it */
1660 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1661 {
1662 if (dev->subordinate) {
1663 printk(KERN_WARNING "PCI: MSI quirk detected. "
1664 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1665 pci_name(dev));
1666 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1667 }
1668 }
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1670
1671 /* Go through the list of Hypertransport capabilities and
1672 * return 1 if a HT MSI capability is found and enabled */
1673 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1674 {
1675 int pos, ttl = 48;
1676
1677 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1678 while (pos && ttl--) {
1679 u8 flags;
1680
1681 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1682 &flags) == 0)
1683 {
1684 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n",
1685 flags & HT_MSI_FLAGS_ENABLE ?
1686 "enabled" : "disabled", pci_name(dev));
1687 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1688 }
1689
1690 pos = pci_find_next_ht_capability(dev, pos,
1691 HT_CAPTYPE_MSI_MAPPING);
1692 }
1693 return 0;
1694 }
1695
1696 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1697 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1698 {
1699 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1700 printk(KERN_WARNING "PCI: MSI quirk detected. "
1701 "MSI disabled on chipset %s.\n",
1702 pci_name(dev));
1703 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1704 }
1705 }
1706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1707 quirk_msi_ht_cap);
1708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,
1709 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1710 quirk_msi_ht_cap);
1711
1712 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1713 * MSI are supported if the MSI capability set in any of these mappings.
1714 */
1715 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1716 {
1717 struct pci_dev *pdev;
1718
1719 if (!dev->subordinate)
1720 return;
1721
1722 /* check HT MSI cap on this chipset and the root one.
1723 * a single one having MSI is enough to be sure that MSI are supported.
1724 */
1725 pdev = pci_get_slot(dev->bus, 0);
1726 if (!pdev)
1727 return;
1728 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1729 printk(KERN_WARNING "PCI: MSI quirk detected. "
1730 "MSI disabled on chipset %s.\n",
1731 pci_name(dev));
1732 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1733 }
1734 pci_dev_put(pdev);
1735 }
1736 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1737 quirk_nvidia_ck804_msi_ht_cap);
1738
1739 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1740 {
1741 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1742 }
1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1744 PCI_DEVICE_ID_TIGON3_5780,
1745 quirk_msi_intx_disable_bug);
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1747 PCI_DEVICE_ID_TIGON3_5780S,
1748 quirk_msi_intx_disable_bug);
1749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1750 PCI_DEVICE_ID_TIGON3_5714,
1751 quirk_msi_intx_disable_bug);
1752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1753 PCI_DEVICE_ID_TIGON3_5714S,
1754 quirk_msi_intx_disable_bug);
1755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1756 PCI_DEVICE_ID_TIGON3_5715,
1757 quirk_msi_intx_disable_bug);
1758 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1759 PCI_DEVICE_ID_TIGON3_5715S,
1760 quirk_msi_intx_disable_bug);
1761
1762 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
1763 quirk_msi_intx_disable_bug);
1764 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
1765 quirk_msi_intx_disable_bug);
1766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
1767 quirk_msi_intx_disable_bug);
1768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
1769 quirk_msi_intx_disable_bug);
1770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
1771 quirk_msi_intx_disable_bug);
1772 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4395,
1773 quirk_msi_intx_disable_bug);
1774
1775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1776 quirk_msi_intx_disable_bug);
1777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
1778 quirk_msi_intx_disable_bug);
1779 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
1780 quirk_msi_intx_disable_bug);
1781
1782 #endif /* CONFIG_PCI_MSI */
Linux kernel - Deliverables
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